JPH01177713A - Delay circuit for semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To obtain a large delay amount without nousing lots of cells by forming a capacitor by a cross part between signal and power source wires in the circuit of master slice system comprising cells, signal wires and power source wires. CONSTITUTION:An output 12 of an inverter circuit 1 is connected to an input of an inverter circuit 2 and a capacitor 3 is connected between the output 12 and a power source potential VSS. The capacitor 3 is formed by opposing the signal and power source wires in crossing. In the input of a signal of input waveform 51 to the input 11 of the circuit 1, the output 12 outputs an output waveform 53 retarded by a delay time t0 being the delay time of the circuit 1 itself and the result is inputted to the circuit 2. In the presence of the capacitor 3, however, the output waveform 52 in addition of the delay time t1 due to charge/discharge of the capacitor 3 is outputted to the circuit 2. That is, the capacitor 3 retards the output.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and particularly to a delay circuit for a semiconductor integrated circuit.

[Prior Art] Conventionally, this type of delay circuit has been constructed by connecting a necessary number of basic circuits such as inverter circuits and non-inverter circuits in series.

[Problems to be Solved by the Invention] The conventional delay circuit described above obtains a desired delay time by using a large number of basic circuits, and therefore has the disadvantage of requiring a large number of cells.

[Means for Solving the Problems] The present invention has been made for the purpose of solving the above-mentioned conventional problems and providing a delay circuit for a semiconductor integrated circuit that can obtain a delay time without requiring a large number of cells. In order to achieve this purpose, a master slice type delay circuit for semiconductor integrated circuits consisting of a cell, a signal wiring, and a power supply wiring has a structure in which a capacitor is formed by the intersection of the signal wiring and the power supply wiring. There is.

[Example] Next, an example of the present invention will be described with reference to the drawings.

Fig. 1 is a circuit diagram of an embodiment of the present invention, Fig. 2 is a plan view showing a capacitor of this embodiment, Fig. 3 is a cross-sectional view of Fig. 2, and Fig. 4 is a cross-sectional view of Fig. 2. The perspective view and FIG. 5 are waveform charts for explaining the operation of this embodiment.

In the figure, 1.2 is an inverter circuit, 3 is a capacitor, 4 is a first aluminum wiring, 5 is a second aluminum wiring, and 6 is an insulating film.

The delay circuit of this embodiment connects the output 12 of the inverter circuit 1 to the input of the inverter circuit 2 as shown in FIG.
A capacitor 3 is connected between the output 12 and the power supply potential Vss. When a signal with an input waveform 51 as shown in FIG. 5 is input to the human power 11 of the inverter circuit 1,
When the capacitor 3 is not present, the output waveform 53 is delayed by the delay time of the inverter circuit 1 itself and is input to the inverter circuit 2, but when the capacitor 3 is present, the output waveform 53 is delayed by Delay time due to charging and discharging 1. An output waveform 52 is outputted and inputted to the inverter circuit 2. That is, the output can be delayed by the capacitor 3.

Next, the structure of the capacitor 3 will be explained using FIGS. 2, 3, and 4. In general, in a master slice type semiconductor integrated circuit, cell rows in the X direction are arranged at regular intervals in the X direction, and multiple pairs of power supply wiring in the X direction are arranged in the X direction. It is used in the X direction to connect cells. A first aluminum wire is assigned as a signal wire in the X direction, and a second aluminum wire is assigned as a power supply wire in the X direction.

In this embodiment, the capacitor 3 is composed of the first aluminum wiring and the second aluminum wiring. That is, one electrode of the capacitor 3 is formed by the first aluminum wiring 4 which is the signal wiring, and the other electrode is formed by the second aluminum wiring 5 which is the power supply potential VSS, and an insulating film 6 is formed at the intersection of the two. is used as a capacitor 3.

Further, the width of the intersection portion of the first aluminum wiring 4 that intersects with the second aluminum wiring 5, which is wide, is made wider. This increases the cross-section area and functions as a capacitor.

Therefore, by widening the intersection between the first aluminum wiring 4 and the second aluminum wiring 5, the capacitance of the capacitor can be increased.

[Effects of the Invention] As explained above, the present invention provides a delay circuit for a master slice type semiconductor integrated circuit consisting of a cell, a signal wiring, and a power wiring, in which a capacitor is formed by the intersection of the signal wiring and the power wiring. This has the effect of providing a delay circuit that can obtain a large amount of delay without using a large number of cells.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing one embodiment of the present invention, Figures 2 and 3 are circuit diagrams showing one embodiment of the present invention.
4 are a plan view, a sectional view, and a perspective view of the capacitor shown in FIG. 1, respectively, and FIG. 5 is a waveform diagram showing the operation of the circuit shown in FIG. 1. 1.2: Inverter circuit 3: Capacitor 4: First aluminum wiring 5: Second aluminum wiring 6: Insulating film

Claims (1)

[Claims] A delay circuit for a semiconductor integrated circuit of a master slice type comprising a cell, a signal wiring, and a power supply wiring, characterized in that a capacitor is formed by an intersection of the signal wiring and the power supply wiring.