JPH01176562A - Image formation apparatus - Google Patents

Abstract

PURPOSE:To make it possible to latch image data in a stable area without a phase delay at all times, by providing a phase selecting means for selecting a phase of an inner clock. CONSTITUTION:In a printer of this invention, an inner clock WCLKO is selectively reversed to a pixel clock WCLKL by a phase selecting reversing circuit 280, by which pixel clock image data XWDAT is latched. Accordingly, the phase delay of the image data XWDAT by half a period when the fall of the pixel clock XWCLK is made a reference is removed. With only the phase delay by the cable length, the image data is prevented from being latched in an unstable area.

Description

[Detailed description of the invention] kinky eyes The present invention relates to an image forming apparatus such as a laser printer.

blood rice technician Generally, electrophotographic copying equipment, laser printers.

When using an image forming device with a built-in video interface, such as a facsimile device, connected to a host, a pixel clock is sent to the host, and image data transferred from the host is synchronized with this pixel clock. It starts with an internal clock and scans the photoreceptor with a light beam using the image data as a write signal to form an image.

By the way, as for the configuration of the host side that transfers image data to such an image forming apparatus, there is a case where image data is transferred based on the fall of the pixel clock from the image forming apparatus, and a case where the image data is transferred based on the fall of the pixel clock from the image forming apparatus, and a case where the image data is transferred based on the fall of the pixel clock from the image forming apparatus. Two methods can be considered: a case where image data is transferred based on the rising and falling of the black shift.

Therefore, for example, when an image forming apparatus processes image data based on the falling edge of the pixel clock, and when the host side transfers image data based on the rising edge of the pixel clock from the image forming apparatus, the falling edge of the pixel clock The phase of the image data is delayed by half a cycle, and a phase delay of twice the length of the cable is added to this, resulting in latching in unstable areas, making it impossible to form images accurately and reducing image quality. arise.

This invention was made in view of the above points, and aims to improve image quality by eliminating the above-mentioned phase lag and making it possible to always latch image data in a stable area. shall be.

In order to achieve the above object, this invention has a built-in video interface, and sends a pixel clock, which is an inverted version of the internal clock, to the host side from the video interface, and synchronizes with the falling edge of this pixel clock. The image forming apparatus forms an image by latching image data transferred from a host side using the internal clock, and includes a phase selection means for selecting the phase of the internal clock.

Hereinafter, a detailed explanation will be given based on one embodiment of the present invention.

FIG. 1 is an external perspective view showing an example of a laser printer as an image forming apparatus embodying the present invention.

This laser printer is connected to a host (not shown), such as a word processor or personal computer.

Images are formed (printed) on various types of paper such as sheet paper and envelopes based on image information provided as image data from various information processing devices such as office computers, data processors, workstations, and image editing processing devices. ).

This laser printer is divided into an upper unit 1 and a lower unit 2. Inside the cover 3 of the upper unit 1 and inside the cover 4 of the lower unit 2, there are mechanical parts and parts for forming images, which will be described in detail later. It houses a control unit that controls this mechanism.

Moreover, the cover 3 of the unit 1 has an operation panel 5 on the front.
A font cartridge insertion slot 6 and an emulation card insertion lower are formed at the back of the right side, and an upper paper ejection tray 8 for storing ejected paper is formed in a part of the upper part.

The operation panel 5 includes a rotary type paper size selection switch 10 for instructing the paper size to this printer, a switch group 11 for giving various other instructions, and a switch for changing the photoconductor and paper size selection switch 10. end,
A display 12 made of a light emitting diode (LED) or the like is attached to display various error statuses such as jam and toner end, paper size, etc.

The font cartridge insertion slot 6 is for inserting a font cartridge having a RAM or ROM that stores character fonts, and the emulation card insertion slot 6 is for inserting a font cartridge having a RAM or ROM that stores character fonts. This is for inserting an emulation card to ensure consistency between the two.

In addition, a paper feed tray 13 for placing and holding paper is removably installed on the right side of the lower unit 2, and on the left side of the front, the paper is ejected toward the outside of the printer (in the direction of arrow A).
and an upper paper discharge tray 8.

The upper unit 1 and the lower unit 2 are hinged at the back part 4 and fixedly held together by a lock mechanism on the front side, and a lock lever protrudes from the front surface of the cover 6.
By pushing up the knob 15, the locking mechanism is released and the upper unit 1 can be rotated and lifted from the lower unit 2 as shown in FIG. 2, thereby facilitating maintenance work and parts replacement. We are making it possible to do so.

FIG. 3 is a configuration diagram showing the image forming mechanism section of this laser printer.

In this laser printer, when a print is started, a drum-shaped photoreceptor 21 disposed approximately in the center of the lower unit 2 is rotated in the direction of the arrow by a main motor (not shown).

At this time, first, the surface of the photoreceptor 21 is uniformly charged by electric discharge from the charge wire 23 stretched parallel to the photoreceptor 21 in the charger 22, and then the surface of the photoreceptor 21 is charged according to the written image by the laser writing device 24, which will be described in detail later. The laser beam is emitted onto the photoconductor 21 through the second cylindrical lens 108 to scan the photoconductor 21 (main scan), and then the photoconductor 21 is scanned by the laser beam (scanning beam) and the photoconductor 21 is scanned (main scan). By rotating in the direction of the arrow (sub-scanning),
An electrostatic latent image is formed on the photoreceptor 21 according to the written image.

Then, toner 27 is attached to the electrostatic latent image on the photoreceptor 21 by the developing device 26, and the toner image is visualized as a toner image. This developing device 26 includes a toner replenishing roller 2 that rotates toner 27 contained in a toner storage tank 28 in the direction of the arrow.
9 replenishes the developing roller 30 and the toner layer thickness control blade 32 regulates the toner layer thickness on the surface of the developing roller roller 0 to a constant thickness. Rotate in the direction shown to remove toner 2.
This is a contact development type developing device in which the photoreceptor 7 is deposited on the photoreceptor 21.

The developing device 26 includes a stirring plate 36 for stirring the toner 27 contained in the toner storage tank 28, and a toner cartridge 34 is mounted on the upper part.

On the other hand, the uppermost paper of the sheets of paper 36 placed on the paper feed 1-lay 13 is separated by the paper feed roller 67 and the friction pad 38 rotating in the direction of the arrow, and separated by the upper conveyance roller 38. and the lower conveyance roller 40, and further conveyed to the transfer position via the conveyance surface 41 by the upper conveyance roller 39 and the lower conveyance roller 40.

Then, this paper is brought into contact with the photoreceptor 20 at the transfer position to be superimposed on the toner image, and a predetermined voltage is applied to the transfer charger 43 at a predetermined timing to attract the toner toward the paper, and the toner is placed on the photoreceptor 21. Transfer the toner image onto paper.

Immediately after this transfer process is completed, the photoreceptor 21 is irradiated through the paper and the paper by a static elimination lamp 44 made of a light emitting diode (LED) disposed downstream of the transfer charger 46, and the residual charge on the photoreceptor 21 and the paper are removed. Charges on the paper as it passes are removed, and the paper is separated from the photoreceptor 21 by its own weight.

After that, the paper that has been separated by its own weight from the photoconductor 21 is transferred to the conveying surface 47.
It is sent between the heating roller 50 and pressure roller 51 of the fixing device 48 via the fixing device 48 . A heater 52 is provided inside the heating roller 50 to heat the surface of the heating roller 50.
The toner image is melted and fixed onto the paper by applying pressure to the paper and the toner image while heating the paper and the toner image with the pressure roller 51 and the pressure roller 51 .

The surface of the heating roller 50 is made of a conductive material such as Teflon, which is a roller base mixed with carbon, to improve stackability after paper ejection by eliminating charges on the paper during fixing.

This fixed paper is peeled off from the heating roller 50 by a peeling claw 53 and sent to a paper discharge roller 55. A paper ejection switching claw 56 is provided at a downstream position of the paper ejection roller 55.

This paper ejection switching claw 56 is connected to the paper ejection switching knob 1 shown in FIG.
4, and by turning the paper discharge switching knob 14, the paper discharge switching claw 56 is rotated between the position shown by the solid line and the position shown by the broken line.

When the paper ejection switching claw 56 is in the position shown by the solid line, the paper ejected from the paper ejection roller 55 passes through the conveyance path 60 formed by the paper ejection guide member 57 and the paper ejection guide members 58 and 59. Then, the paper is discharged onto the upper paper discharge tray 8 by the upper paper discharge roller 61 in an inverted state (face-down paper discharge). Further, when the paper ejection switching claw 5 is at the position shown by the broken line, the paper ejected from the paper ejection roller 55 is directly ejected in the direction of arrow A (face-up paper ejection).

Note that you are free to select any paper ejection mode, but
Face-down paper ejection, in which pages are stacked, is suitable for plain paper, while face-up paper ejection, in which pages are stacked in reverse, can be ejected for plain paper, but is suitable when using relatively stiff paper such as envelopes. ing.

On the other hand, the cleaning blade 63 removes toner remaining on the surface of the photoreceptor 21 after the transfer process is completed, and the photoreceptor 21 is ready for the next image forming process. Note that the photoreceptor 21
The residual toner removed from above is sent to a toner collection tank 65 by a toner collection roller 64 and stored therein.

FIG. 4 is an exploded perspective view of the main parts of the upper unit 1.

Referring also to FIG. 3 mentioned above, the upper unit frame 70 provided in the cover 3 of the upper unit 1 has a laser writing device 24 on the bottom, a second cylindrical lens 108 to be described later, an ozone blower fan 71 and a suction. A fan unit 72 is attached, a lock lever 76 is attached to the front surface on the near side, and a paper discharge guide member 57 is attached to the front surface.

Further, an electrical chassis 74 is mounted inside the cover 3 of the upper unit 1 above the upper unit frame 70, and within this electrical chassis 74 are a main control board 75 forming a main controller which forms a control section of the printer, and a video interface board. 76 is installed.

5 and 6 are a plan view and a perspective view of the main parts of the laser writing device 24. FIG.

This laser writing device 24 includes a laser diode (LD) unit 101 attached to the side surface of a case 100, and a first cylindrical lens 102 attached near the center of the bottom surface.
．． First mirror 103. A spherical lens 104, a polygon mirror 106 rotated in the direction of the arrow by a polygon motor 105 attached to the rear of the bottom, a second mirror 107 attached to the front, and a third mirror 110 attached to the side of the bottom. Third cylindrical lens 1 attached to the side
11 and an optical fiber 112.

The laser diode (LD) unit 101 includes a laser diode (LD) inside, a collimating lens that converts a diverging beam emitted from the laser diode into a parallel beam, and a collimating lens that changes the shape of the laser beam that has passed through the collimating lens. It integrally incorporates an aperture member that is shaped into a shape that is long in the scanning direction and short in the sub-scanning direction, and also includes a printed circuit board 114 that forms part of an automatic output control circuit (APC) that controls the output of the LD. be.

Note that a monitoring photodiode that receives laser light emitted backward from the laser diode (LD) is integrated into the laser diode (LD).

Further, the first cylindrical lens 102 directs the laser beam emitted from the 1l-LD unit 101 to the photoreceptor 2.
1 in the sub-scanning direction.

The spherical lens 104 narrows down the laser light reflected by the first mirror 103, forms a laser beam, refracts it obliquely upward by about 5 degrees, and makes it incident on the mirror surface 106a of the polygon mirror 106.

The polygon mirror 106 uses a rounded polygon mirror formed by curving each mirror surface 106a, and is a post-object type optical deflector (a post-object type optical deflector (light beam This is a type of optical deflector in which a deflector is placed after condensing the beam.

The second mirror 107 reflects the laser beam (scanning beam) reflected by the polygon mirror 106 onto the photoreceptor 21 .

Further, the third mirror 110 is disposed outside the scanning area on the photoreceptor 21 by the laser beam reflected by the polygon mirror 106, and directs the incident laser beam to the optical fiber 11.
Reflect towards the 2nd side.

The other end of the optical fiber 112 is connected to a fiber connector 115 mounted on the main control board 75 shown in FIG. , to a synchronization detection sensor consisting of a photodiode, which will be described later, provided on the main control board 75. These constitute a synchronization detection mechanism for keeping the scanning start position constant.

In this laser writing device 24, the LD unit 1
Laser light emitted from a laser diode (LD) 01 according to written information is collimated by an internal collimating lens, shaped by an aperture member, and emitted. The laser light emitted from this LD unit 101 is
The light passes through the first cylindrical lens 102, is reflected by the first mirror 103, is condensed by the spherical lens 104, is refracted upward, and is incident on the mirror surface 106a of the polygon mirror 10B.

The mirror surface 10a of this polygon mirror 106 is
The laser beam reflected by the second mirror 107 is further reflected by the second mirror 107 and is irradiated onto the photoreceptor 21 via the second cylindrical lens 108 .

At this time, the rotation of the polygon mirror 106 in the direction of the arrow turns the laser beam into a scanning beam that scans the photoreceptor 21 in the direction of the arrow B (main scanning), and the scanning beam scans the photoreceptor 21 (main scanning). ) is polygon mirror 10
6 is repeated every 10 days a, and at the same time the photoreceptor 2
1 rotates in the direction perpendicular to the main scanning direction (sub-scanning direction) as described above, thereby forming an electrostatic latent image on the photoreceptor 21 according to the written image.

In addition, the scanning beam reflected by the polygon mirror 106 (
The laser beam) is incident on the third mirror 110 before scanning on the photoreceptor 21, and is incident on the third cylindrical lens 11.
1 to the optical fiber 112 and enters the main controller.
It is guided by a synchronization detection sensor on the troll board 75, and the scan start timing is controlled based on the synchronization detection result.

In this way, this laser writing device 24 emits a laser beam from an oblique direction onto a line connecting the center position in the width direction of the photoreceptor and the rotation center of the polygon mirror 106, and then directs the laser beam from there toward the rotation center of the polygon mirror. The laser beam is reflected by the polygon mirror 106, and the laser beam is refracted upward so that it enters the mirror surface 106a of the polygon mirror 106 obliquely from below, and the laser beam reflected by the polygon mirror 106 is guided onto the photoreceptor 21 via the mirror 107. Since the laser beam incident on the polygon mirror 106 and the polygon mirror 10
Since the reflected laser beams from 6 do not intersect in a so-called three-dimensional intersection, it is possible to miniaturize the writing device and improve writing accuracy.

FIG. 7 is a block diagram showing the control section of this laser printer.

First, regarding the power supply system, a power supply voltage is input from a commercial power supply to the power input section 122 via the AC plug 121. This power input section 122 removes noise from the input voltage through a main switch 126 and a noise filter 124, and then disconnects the main power when the upper unit 1 is separated from the lower unit 2 and lifted. It is supplied to a main controller power supply unit 126 via an interlock switch 125, and directly to a video interface power supply unit 127.

The main controller power supply unit 126 includes a noise filter 130, a constant voltage circuit 131 that generates a constant voltage by converting input voltage from AC to DC, and a heating roller 50 for controlling the fixing temperature of the fixing device 48. It includes a high-speed solid state relay (SSR) 132 and the like as a switching element for controlling on/off power supply to the heater 52.

The video interface power supply unit 127 includes a noise filter 163, a constant voltage circuit 134 that converts an input voltage from AC/DC to generate a constant voltage, and the like.

The main controller power supply unit 126 is
A main controller 135 formed on the main control board 75, a power pack for charging charger 22 and developing bias (charging/developing power pack) 137,
A power pack 138 for the transfer charger 43, a driver for the main motor 169, a crystal oscillator for generating a reference signal for constant speed control, and an encoder.

Power supply voltage is supplied to a main motor unit 140 including a power circuit, a servo circuit, etc., a group of various operating devices 141, an ozone blower fan 71, a suction fan (not shown), a heater 52 of the fixing device 48, and the like.

Further, the video interface power supply unit 127 is
A power supply voltage is supplied to the video interface 136 formed on the video interface board.

The various operating equipment group 141 includes a paper feed clutch 142 for controlling the rotation of the paper feed roller 37, a paper transport latch 143 for controlling the rotation of the lower transport roller 40,
It is comprised of a total counter solenoid 144 for counting up a total counter (not shown) that displays the number of prints, and a latching solenoid 145 provided in the suction fan unit 72.

Next, the control system will be described.

The main controller 135 includes a video interface connector 161 for connecting to a video interface 136 to be described later, and a CPU, ROM, RAM, and
(hereinafter simply referred to as rCPUJ)
) 162, a write control section 163, a display driver 164, a synchronization detection circuit 165, a polygon motor driver 166, and the like.

The video interface connector 161 sends a pixel clock to the host HT through the video interface 136, and receives image data sent from the host HT through the video interface 136.

The CPU 1B2 controls image forming processes such as charging, exposure, development, transfer, paper feeding, and fixing. In other words, this CPU
Based on the image clock (pixel clock) from the write control section 163, the IB2 sends the data received from the host HT to the write control section 16B to write an image.

The CPU 1f 32 also controls the lighting of the display group 12B that constitutes the display group 12 provided on the operation panel 5 via the display driver 164, and also takes in size selection information from the paper size selection switch 10.

Furthermore, this CPU 162 has a charging/developing power pack 137. Transfer power pack 138. Main motor driver 140. Various operating equipment group 141 and fixing control 5sR
132 etc. is controlled.

Furthermore, each of the CPU 1 [32 includes resist sensors 171 . Paper discharge sensor 17
2. Toner over sensor 173. Paper end sensor 1
74. Various detection information from a latch sensor 175, a toner end sensor 176 such as a microsinch, and a fixing temperature sensor 177 such as a thermistor is input.

Here, the mounting of each sensor will be explained with reference to FIG. 3 regarding the position and the like.

The registration sensor 171 is arranged upstream of the conveyance rollers 39 and 40, and detects whether or not the paper is fed between the conveyance rollers ``!;9.40''.
lower conveyance roller 4 based on the timing when the paper is detected.
Controls the start of 0.

A paper ejection sensor 172 is disposed near the exit of the fixing device 48 and detects whether or not paper is sent out from the fixing device 48.

The toner overflow sensor 173 is disposed above a swing 178 provided at the top of the toner collection tank 65 and lifted up when the toner is full, and detects when the toner collection tank 65 is overflowing with toner.

A paper end sensor 174 is disposed at the tip of the paper feed tray 13 and determines whether there is any paper on the paper feed tray 13.

The latch sensor 175 is disposed above the latch solenoid 145 and detects the operating state of the latch solenoid 145.

The toner end sensor 176 detects the absence of toner in the toner storage tank 28 of the developing device.

The fixing temperature sensor 177 is connected to the heating roller 5 of the fixing device 48.
Detects surface temperature of 0.

Next, the write control unit 163 drives and controls the laser diode (LD) of the laser writing device 24 via the LD auxiliary circuit 180 based on the data from the CPU 182 to emit a laser beam according to the write data. In addition, the drive start timing of the laser diode (LD) of the laser writing device 24 is determined according to a synchronization detection signal output from the synchronization detection circuit 165 based on the laser light incident from the laser writing device 24 via the optical fiber 112. Furthermore, the driving of the polygon motor 105 of the laser writing device 24, that is, the rotation of the polygon mirror 106, is controlled via the polygon motor driver 16.

In addition, two voltage conversion circuits 178 and 179 consisting of a three-terminal regulator, a DC/DC converter, etc. are provided within the main controller 135. These voltage conversion circuits 178 and 179 generate various voltages.

The video interface 136 is connected to the main controller 1
35, the received pixel clock, etc. is sent to the host HT, and the image data (
image data) is received and the main controller 135
A video interface (I
/F) A circuit 191, a connector 192 for connecting to the host HT, a connector 193 for connecting to the main controller 135, and a connector 194 for inputting power (5V) from the power supply unit 127. There is.

In other words, this laser printer does not generate image data from code data within the printer, but receives and prints image data generated externally.

FIG. 8 is a block diagram showing details of the write control section 16B in the main controller 135.

The write control IC 201 is a one-chip LSI circuit that controls the laser writing device 24.
It is equipped with a crystal oscillator 202 with an oscillation frequency of 20 MHz, generates a reference clock internally, and receives image data XWDATA sent from the video interface 136.

In addition, image data XWDAT! f is image data WDAT
This is the inversion of A. In this specification, data and signals such as image data and pixel clocks are
An "X" is added to the beginning of the signal name to indicate inversion.

The write control IC 201 also uses an internal clock (also referred to as an image scanning clock, image clock, or write clock) WCLKO output from a voltage-controlled oscillator (VCO) of the clock generation circuit 203 and an output from the synchronization detection circuit 165. synchronization detection signal DETP and L
Laser diode (LD) 210 in D unit 101
A monitor signal output from a monitor circuit 204 forming a part of a reference value setting circuit that sets the light emission intensity of 2 to a reference value (this signal becomes a count mode switching signal for an internal up/down counter as described later); and the feedback signal FG from the feedback signal generation circuit 205.

The clock generation circuit 203 generates an internal clock WCLKO having a frequency according to the control voltage signal ○UTD given from the write control IC 201 by VCO, and outputs it to the write control IC 201, and also outputs the internal clock WC to the write control IC 201.
Pixel clock WCLKL that is selectively inverted from LKO
also occurs.

The synchronization detection circuit 165 is based on the output of the photodiode 165A that receives the laser beam for synchronization detection guided from the laser writing device 24 via the optical fiber 112.
A synchronization detection signal DETP is output to the write control IC 201.

The monitor circuit 204 includes a laser diode (LD) 210
A monitor signal (up/down switching signal) is output to the write control IC 201 based on the output of the monitor photodiode 211 that receives the laser beam emitted backward from the write control IC 201 .

A feedback signal generation circuit 205 receives a feedback signal FGI from the polygon motor 105.

Based on FG2, a feedback signal FG is generated and output to the write control IC 201.

Then, the write control IC 201 controls the clock generation circuit 2
A clock signal XWCLK, which is an inversion of the internal clock WCLKO input from 03, is sent to the video interface 136 in order to synchronize with the transfer of image data.

Further, a reference value D/A converter 215 that forms part of a power modulation circuit that controls the emission intensity of the laser diode 210
outputs reference value data for controlling the emission intensity of the laser diode 210 to the reference value, and outputs reference value data for controlling the emission intensity of the laser diode 210 to a reference value, Correction data for correcting and controlling the intensity according to the scanning speed is output.

Furthermore, write data WDAT is sent to the modulation circuit 218.
It outputs modulation data (image data) VIDOB according to A, and also outputs drive data to the polygon motor driver 166 to control the rotation speed, that is, the scanning speed of the polygon motor 105.

The two reference value D/A converters 215 and the correction D/A converter 215
The A converter 216 performs D/A conversion on the reference value data and correction data given from the write control IC 201, converting them into analog reference value signals and correction signals, and adds the reference value signals and correction signals. It is output as a light emission intensity signal to a semiconductor laser (LD) drive circuit 217 that drives a radar diode (LD) 210.

Modulation circuit 218 generates modulation signal VIDEO based on modulation data VIDEOB from write control IC 201 and outputs it to semiconductor laser drive circuit 217 .

This semiconductor laser drive circuit 217 supplies a drive current to a laser diode (
LD) 210, and in response to the modulation signal VIDEO from the modulation circuit 218
On/off control of the current flowing through 210 is performed.

Here, regarding an example of the modulation circuit 218, FIG.
This will be explained with reference to FIG.

This modulation circuit 218 includes D-type flip-flop circuits (hereinafter referred to as rD-FF circuits) 221 and 222, a delay element 223, and a NAND circuit 224.

The D-FF circuit 221 inputs pixel data (modulation data) VIDEOB from the write control IC 201 to an input terminal, and receives an internal clock WC from the clock generation circuit 203.
Input LKO to clock terminal CK.

The D-FF circuit 222 inputs the Q output of the D-FF circuit 221 to the input terminal, and inputs the pixel clock WCLKL obtained by selecting the phase (for example, inverting) the internal clock WCLK○ from the clock generation circuit 206 to the clock terminal GK. do.

The delay element 223 delays the six outputs of the D-FF circuit 221 by a predetermined delay time td and outputs the delayed outputs.

This delay time td is a time that satisfies the relationship O<t d<t, where t is the per-two false width of the internal clock WCLKO. The NAND circuit 224 is the D-FF circuit 22
The ζ output of 2 and the output of the delay element 226 are ANDed and the inverted signal is output as the modulation signal VIDE○.

Therefore, in this modulation circuit 218, referring also to FIG. 10, the pixel data (modulation data) VIDEOB shown in FIG. synchronized with
The D-FF circuit 222 delays and inverts the internal clock WCLKO by a half-lock (pulse width t), and inputs it to the NAND circuit 224 as the ζ output of the D-FF circuit 222, as shown in FIG. .

On the other hand, the Q output of the D-FF circuit 221 shown in FIG. ), the delay time t
The signal is delayed by d and input to the NAND circuit 224.

Thereby, the NAND circuit 224 is connected to the D-FF circuit 222.
6 outputs and the output of the delay element 223 are taken and inverted, so the NAND circuit 224 outputs a modulated signal whose lighting time is shorter than the pixel data length by the time Δt, as shown in FIG. VIDEO is output.

This enables the on/off of the light source (laser diode) within one pixel when achieving uniform writing speed by changing the frequency of the internal clock WCLKO without using the f0 lens for optical scanning, as described later. The ratio can be improved.

For example, the period Tk of the internal clock WCLKO is set to T1 to T.
When changing to n stages of n, the duty ratio of the internal clock for each period is 50%, and the pulse width is t k = t k
- When 1/2 (k = 1 to n), the on/off ratio of the laser diode 210 is Tk-(tk
−td)/Tk=50%+td/Tk.

For example, when achieving an on/off ratio of 70% for the laser diode 210 with T = 400 ns and Tn = 600 ns, td = 96 ns, and the on/off ratio of the laser diode 210 from T1 to Tnk is 70 over 4. %, which increases the accuracy of the on/off ratio.

Returning to FIG. 8, the terminal P1 of the write control IC 201
is connected to ground via a jumper line UPI to specify the pixel density, and the level input to the terminal P1 depending on the presence or absence of the jumper line JPI is used as pixel density information. In other words, connect this jumper wire JPI to terminal P
For example, 240 DPI is specified as the pixel density when the terminal P1 is set to the ground level, that is, the low level "L", and 300 DPI is specified as the pixel density when the jumper wire JPI is cut and the terminal P1 is set to the high level "H". In addition, the pixel density is set to 1.
80DPI/200DPI, 400DPI/480DPI
It is also possible to perform switching of I or a combination of these.

Similarly, a switch SWI used to set the power (output) of the laser diode 210 is attached to the terminal P2 of the write control IC 201. Also, the terminal P3 of the write control IC 201. P4 is a jumper line JP3. Connected to ground via JP4.

Furthermore, the terminal P5 of the write control c201 is connected to ground via a jumper wire JP5 to specify the printing speed (linear speed), and depending on the presence or absence of this jumper wire JP5, the level of manual input to the terminal P5 can be set to the linear speed. Use as information. In other words, when this jumper wire JP5 is connected and the terminal P5 is set to the ground level, that is, the low level "L", for example, 48 mm/see is specified as the linear speed, and the Janno dog wire JP5 is disconnected and the terminal P5 is set to the high level. For example, 36 mm/see is specified as the linear velocity when the speed is set to ゛H°.

Furthermore, the terminal P6 of the write control IC 201 is connected to ground via a jumper line JP6 in order to specify the pixel density in the main scanning direction, and the level input to the terminal P6 is determined depending on the presence or absence of this jumper line JP6. Used as direction pixel density information.

In addition, the signals output from each part of the write control unit 16B, that is, the synchronization detection signal DETP from the write control IC 201, and the frequency divider that forms a phase-locked loop circuit together with C○ of the clock generation circuit 203. The clock CLKA output from the internal clock WCL
Clock WCLKO/8.K divided by 8. Modulation data (
Image data) VIDEOB, write position (print start) signal LGATE, voltage signal 0UTD for VC○ of the clock generation circuit 203, and monitor output LDECT from the monitor circuit 204 are provided on the main control board 75 shown in FIG. They are grouped and output to check connectors 225-227.

By using the check pin as a connector in this way, checking can be easily performed.

FIG. 11A is a block diagram specifically showing the internal structure of the write control IC 201 and tarlock generation circuit 203.

The oscillator 231 generates a frequency f by the crystal oscillator 202. A reference clock fR is generated.

The divider 262 divides the reference tarokk fR from the oscillator 231 using the division ratio Li set by the division ratio setting circuit 263 to obtain the frequency f. / Outputs the clock fl of Li. Polygon motor drive circuit (polygon motor driver) 16
6 is the frequency f from the frequency divider 232. The polygon motor 105 is rotated at a speed according to the clock fL of /Li, and the polygon mirror 106 is rotated at a predetermined speed.

The frequency divider 235 divides the reference clock fR from the oscillator 231 using the division ratio N1 set by the division ratio setting circuit 266 to obtain the frequency f. /N unit position control clock fN is output. The frequency division ratio setting circuit 236 sets the frequency division ratio Ni of the frequency divider 2:55 according to the count value of a frequency modulation up/down counter 241, which will be described later.

The frequency divider 2 to 7 divides the position control clock fN from the frequency divider 235 by the frequency division ratio Mi set by the frequency division ratio setting circuit 268 to obtain the frequency fo / (N x - M 1). Outputs clock fM. A frequency division ratio setting circuit 238 sets a frequency division ratio Mi of the frequency divider 237 according to a count value of a frequency modulation up/down counter 241, which will be described later.

When the intensity modulation up/down counter 240 is enabled by an enable signal EN from a modulation operation management circuit 244, which will be described later, it receives an up/down switching signal U/down from an up/down switching circuit 242, which will be described later.
In the operation mode corresponding to D, the clock fM from the divider 237 is counted up or down, and this count value is applied to the laser diode 21 according to the change in the scanning speed.
Correction D/A as correction data to correct the emission intensity of 0
Output to converter 216. Further, this intensity modulation up/down counter 240 is connected to a reference value setting circuit 25 which will be described later.
When the mode setting signal from 1 is input, the correction data is set to "O".

When the frequency modulation up/down counter 241 is enabled by an enable signal EN from a modulation operation management circuit 244 (described later), the frequency modulation up/down counter 241 performs an up/down counter (described later).
Up/down switching signal U from down switching circuit 242
/D, the clock fM from the divider 237 is up-counted or down-counted, and this count value is output to the frequency division ratio setting circuit 2''; 6,238 and the up/down switching circuit 242.

The up/down switching circuit 242 is an up/down switch for frequency modulation.
The intensity modulation up/down counter 240 and the frequency modulation up/down counter 24 are activated in response to the current value of the down counter 241, that is, near the extreme value of the scanning speed.
It outputs an up/down switching signal U/D for switching the count mode of 1 from up mode to down mode or from down mode to up mode.

The position control counter 243 counts the position control clock fN from the frequency divider 235. Modulation operation management circuit 2
Reference numeral 44 indicates an intensity modulation up/down counter 2 at a constant timing based on the count value of the position control counter 243 and the synchronization detection signal DETP from the synchronization detection circuit 5 mentioned above, that is, based on the synchronization detection signal DETPJ.
40 and frequency modulation up/down counter 241, and outputs an enable signal EN for enabling the frequency modulation up/down counter 241 and disabling them at the end of scanning.

The clock generation circuit 203 in FIG. 8 is composed of a voltage controlled oscillator (VCO) 20'' of a phase locked loop circuit (PLL circuit) 245 and a phase selection inversion circuit 280.

Then, the phase detection circuit (PD) 24 of the PLL circuit 245
B compares the phases of the position control clock fN from the divider 235 and the clock CLKA from the internal frequency divider 249, and outputs the phase difference to the low-pass filter (LPF) 247 as a pulse signal.

The LPF 247 passes a low band frequency signal among the pulse signals from the PD 2413 and outputs it to the voltage controlled oscillator (VCO) 203 as a voltage signal 0UTD.

-36= The VCO 203 generates a clock with a frequency according to the output voltage of the LPF 247, and uses this clock as the internal clock WC.
Output as LKO.

The frequency divider 249 is the internal clock WCL from the VCO 203.
A clock CLKA obtained by dividing K by the division ratio is output.

Also, the internal clock WC output from the VCO20"l
LKO is selectively inverted through a phase selection inversion circuit 280 and sent to the aforementioned modulation circuit 218 as a pixel clock WCLKL, and the pixel clock inverted by an inverter 281 is sent to the video interface 136 in FIG.

The phase selection inversion circuit 280 in this embodiment includes an exclusive OR circuit EXOR, one input terminal thereof, and a power supply Vc.
It is composed of three terminals A, B, and C, each connected to c+ground.

When the host side transfers data based on the fall of the pixel clock XWCLK, short-circuit terminals A and C with a jumper wire,
0 is output as is as the pixel clock WCLKL.

In addition, when the host side transfers data based on the rising edge of the pixel clock XWCLK, short the terminals A and B with a jumper wire, and
is inverted in phase by an exclusive OR circuit EXOR and output as a pixel clock WCLKL.

The data write position control circuit 250 outputs a write position signal (print start signal) LGATE based on the count value of the position control counter 243 and the clock CLKA from the PLL circuit 245.

The reference value setting circuit 251 is a monitor photodiode 21
A reference value D/A converter (DA
C) Output reference value data for controlling the emission intensity of the 215 laser diode 210 to the reference value.

The adder 252 adds the analog correction signal from the D/A converter 216 and the analog reference value signal from the D/A converter 215, and outputs the signal from the laser diode (
LD) ilKl rotation 217.

Note that this adder 252 is conceptual, and the D/A
By connecting the output terminal of the converter 216 and the output terminal of the D/A converter 215, an added value of the correction signal and the reference signal can be obtained.

The write mode setting circuit 253 controls the division ratio setting circuits 233 and 23 based on the input pixel density information and linear velocity information.
8, 238, modulation operation management circuit 244, and data write position management circuit 250, write mode setting information is output.

The frequency division ratio setting circuit 236 switches the frequency division ratio Li according to this write mode setting information. The frequency division ratio setting circuit 2'56 switches the switching mode of the frequency division ratio N1 according to this write mode setting information. The frequency division ratio setting circuit 238 receives this write mode setting information and switches the switching mode of the frequency division ratio Mi accordingly.

The modulation operation management circuit 244 switches the modulation operation management mode based on this write mode setting information. The data write position management circuit 250 switches the write start according to this write mode setting information.

In this embodiment, the pixel density information and linear velocity information are input to the write mode setting circuit 253 through the jumper line JPI as described above.

This is done depending on the presence or absence of JP5, but for example, input using a switch such as a DIP switch, or cp
It can also be input from uIB2 or host HT.

FIG. 11B is a diagram similar to FIG. 11A in another embodiment of the present invention, and the only difference from FIG. 11A is the phase selection inversion circuit 280'.

The phase selection inversion circuit 280' in this embodiment is composed of an inverter N and a pair of switches SW, in which when one is turned on, the other is turned off.

When the host side transfers data based on the fall of the pixel clock
0 is output as is as the pixel clock WCLKL.

In addition, when the host side transfers data based on the rising edge of the pixel clock XWCLK, turn off the switch SW□.

SW2 is turned on to invert the phase of internal clock WCLKO by exclusive OR circuit EXOR and output it as pixel clock WCLKL.

FIG. 12 is a block diagram showing the reference value setting circuit 251.

A comparator 262 compares a monitor voltage VM obtained by amplifying the detection output of the monitor photodiode 211 with an amplifier 261 and a reference value VREF.
The edge detection circuit 266 outputs a signal instructing up mode when VM<VREF and a signal instructing down mode when VM≧VREF as an up/down switching signal U/D to the down counter 270. When the rise (or fall) of the up/down switching signal U/D from the comparator 262 is detected, the reset signal is sent to the S-R type flip-flop circuit 2.
68.

The edge detection circuit 264 detects the rising edge of the frame synchronization signal FSYNC, and outputs this detection signal to the OR circuit 265.
frame synchronization signal FSYN in the AND circuit 266 via
The logical product with C is taken and outputted to the flip-flop circuit 268 as a set signal. The output setting timing generation circuit 267 receives the frame synchronization signal 5YNC, operates in standby mode, and outputs an output setting timing signal to the OR circuit 265 at a constant cycle.

Flip-flop circuit 268 outputs mode setting signal MD depending on the set/reset state.

AND circuit 269 ANDs the mode setting signal from flip-flop circuit 268 and the non-scanning signal and outputs an enable signal to up/down counter 270.

When the up/down counter 270 is enabled by the output of the AND circuit 269, the comparator 26
The clock is counted up or down in a count mode according to the up/down switching signal U/D from 2, and this count value is output to the D/A converter 215 as reference value data.

In addition, the carry/down of this up/down counter 270
A carry signal and a borrow signal from the borrow terminal are applied to the light emitting diode 271 to display the deterioration determination of the laser diode 210. This light emitting diode 271 is connected to the main control board 7 as shown in FIG.
5.

Next, the operation of this embodiment configured as described above will be explained with reference to FIG. 13 and subsequent figures.

When the laser writing device 24 of this printer uses an R polygon mirror with a curved mirror surface 106a as the polygon mirror 106 and does not use the fF) lens, the scanning speed of the photoreceptor surface by the scanning beam is not constant.

In this case, the frequency fK of the pixel clock WCLKL as a clock signal for turning on and off the scanning beam is 1/1, where T is the time allotted for writing one pixel.
It is given by T. When the FE lens is not used, the scanning speed of the scanning beam on the photoreceptor surface is not constant, so if the frequency fl of the pixel clock WCLKL is made constant, the written information will be distorted.

That is, referring to FIG. 13, the angular velocity of the polygon mirror 106 is ω. (constant), the angular velocity of the scanning beam is dθ/dt=2ω. = ω (constant), the scanning speed dh/dt between the distances on the photoreceptor 21 is calculated as follows: β is the distance from the reflection point of the polygon mirror 106 to the photoreceptor 21, and θ is the angle between the distances. When, dh/dt:, 12ω・1/cos”19=βω(1+
h2/β2).

Here, the scanning area width on the photoreceptor 21 is 2H, and H+h=
h', the scanning speed d h/dt over the distance on the photoreceptor 21 is dh/dt=βω(1+(h'-H)"/, 22)
becomes.

Here, assuming that there are 2m pixels within this scanning area width 2H, the scanning speed Vn at the nth pixel counting from the scanning start side on the left side of the scanning area is when the width of one pixel is d. , Vn=j2ω(1+(nd-md)''/u2).Then, the frequency fK of the pixel clock WCLKL is Vn/d in this case from its definition, so fx(n)=( j2 ω/d)・(1+(n d−m
d) 2/, 122).

Therefore, if the frequency fK of the pixel clock WCLK is changed for each pixel according to the above equation, distortion will not occur in writing information even when no fθ lens is used.

Therefore, generation of the pixel clock WCLKL and control of the frequency fK will be explained with reference to FIG. 11A or 11B.

First, the reference clock f of frequency fo from the oscillator 231
4 to 1/N i by the frequency divider 235 to obtain the frequency f
. /N i position control clock fN is generated.

This position control clock fN is given to the PLL circuit 245, and the phase detection circuit 246 of this PLL circuit 245 outputs a voltage signal ○UTD according to the phase difference between the position control clock fN and the clock CLKA from the frequency divider 249. LPF
247 to VC○203, VC○20
Frequency fK according to voltage signal ○UTD input from 3
The internal clock WCLKO is outputted, and this internal clock WCLKO is frequency-divided by a frequency divider 249 and provided to a phase detection circuit 246.

In this case, the internal clock W output from the VCO 203
The frequency fK of CLKO does not change when there is no phase difference between the position control clock fN whose phase is compared in the 1-phase detection circuit 246 and the tally clock CLKA (PLL balanced state).

At this time, the position control clock fN has a frequency f, /Ni
In the equilibrium state, the frequency of the clock CLKA is also f.

/Ni, so in this state, the frequency fK of the internal clock WCLKL output from ■C○203 is fK=f, (1/Ni), where M is the division ratio of the frequency divider 249.・M= f o −M/N
It is i.

Therefore, the frequency division ratio Ni of the frequency divider 235 is set to the frequency division ratio N. By continuously changing the frequency fx-tJfo-M/N of the internal clock WCLKO from
, to f. -M/Np will change continuously and monotonically. In this way, by changing the frequency division ratio Ni of the frequency divider 235, the pixel clock WCLK can be changed to the internal clock WCLK either as it is or with its phase inverted.
The frequency fK of L can also be changed in the same way.

Here, the scanning area is set to blocks BLi (
Based on the predetermined finite number of columns Mi (i=1 to K) during write scanning, the position control clock fN is divided into M units in the first block. The division ratio N1 is switched every time the count is performed.

In other words, the initial value of the division ratio Ni is N. When closed, the frequency of the position control clock fN is f. /No, and in the first block BL1, this position control clock fN is
□When counting, set the division ratio Ni to N. to N1 (
N2=N1+ΔN0).

As a result, the frequency of the position control clock fN becomes fo
/N□. After counting M0 position control clocks fN of this new frequency f, /N, the frequency division ratio Ni is further switched from Ni to N2 (N2=N1+ΔN).

This operation is predetermined n0 for the first block BL process.
After repeating this several times, in the second block BL2, the operation of switching the division ratio Ni is performed n2 times predetermined every time M2 position control clocks fN are counted.

In this way, in the first block BL1, the frequency division ratio Ni is changed to ni every time M1 position control clocks fN are counted.
Switch times.

This process will be explained with reference to FIG. 11A or 11B. The position control clock fN output from the frequency dividers 2 to 5 is divided by the frequency division ratio Mi by the frequency divider 237.

That is, the frequency divider 237 outputs one clock M1 every time Mi position control clocks fN are counted.

At this time, if the enable signal EN from the modulation operation management circuit 244 is output and the frequency modulation up/down counter 241 is in the enabled state, this frequency modulation up/down counter 241 is designated by the up/down switching circuit 242. The clock fM from the frequency divider 237 is counted in the counted mode, and this count value is given to the frequency division ratio setting circuits 23B, 2ES8 and the up/down switching circuit 242.

This frequency division ratio setting circuit 236 changes the frequency division ratio Ni by the amount of change ΔNi every time the count value of the frequency modulation up/down counter 241 changes by "1". Note that although here, the amount of change ΔNi in the frequency division ratio N1 in each block BLi is constant, it may be made different for each block.

Further, the frequency division ratio setting circuit 268 sets the division ratio Mi every time the count value of the frequency modulation up/down counter 241 reaches the switching number ni of the division ratio Ni determined in each block BLi.
is changed by a change amount ΔM1.

Furthermore, the up/down switching circuit 242 provides an up/down switching signal for switching from the up mode to the down mode or from the down mode to the up mode every time the count value of the frequency modulation up/down counter 241 approaches the limit value of the scanning speed. Output U/D.

At the same time, the frequency division ratio setting circuit 236.2'i8 changes the frequency division ratio Ni and the frequency division ratio Mi according to the write mode signal from the write mode setting circuit 253, that is, the pixel density information and the linear velocity information.

An example of the relationship between the number of blocks, the count number of the clock fM (frequency division ratio M i ), the stage of the frequency division ratio Ni, and the position control clock fN at pixel densities of 300 DPI and 240 DPI is shown in FIG. 14 at 0 point. When using a polygon mirror 106 having a radius surface centered at , the length of each surface from the rotation center O is A (the deflection angle 2θ is sinθ=1− with respect to the rotation angle α). A/R-si
(given by nα) is shown in FIGS. 15 and 16 as an example.

In both figures, the right end is the scanning start side, and only the right half of the symmetrical figure is shown.

In other words, at 300 DPI, the scanning area is divided into seven blocks from the first block BL to the seventh block, as shown in FIG.
The first block BL1 (seventh
The same applies to block BL7), the frequency division ratio Ni is switched stepwise to six stages (ni=6) every time five position control clocks fN are counted (M1=5), and the second block BL2 (
The same applies to the sixth block BL), the position control clock f
Every time N is counted 6 times (Mi=6), the division ratio N is changed step by step to 9 levels (ni=9), and the third block BL3
(The same applies to the fifth block BL), the division ratio N1 is switched in three steps (ni=3) every time 10 position control clocks fN are counted (Mi=10), and in the fourth block BL, the position Every time 16 control clocks fN are counted (Mi=16), the division ratio Ni is changed stepwise through five stages (ni=5).

Also, at 240DPI, as shown in Figure 16,
The scanning area is divided into nine first blocks BL1 to ninth blocks B.
Divide into L, 1st block BL E (9th block B
(Same for L), the division ratio Ni is switched stepwise by 10 steps (ni=10) every time two position control clocks fN are counted (Mi=2), and the second block BL2 (the eighth block BL6 is also (same), the position control clock fN is set to 3.
The frequency division ratio N1 is changed step by step to 11 steps (ni=11) every time the frequency division ratio N1 is counted (Mi=3), and the third block BL3
(The same applies to the seventh block BL7). Every time the position control clock fN is counted four times (Mi = 4), the frequency division ratio Ni is switched stepwise in five stages (ni = 5), and the fourth block BL
4 (6th block BL.

is the same), count 7 position control clocks fN (
In the fifth block BL5, the division ratio Ni is changed every time 16 position control clocks fN are counted (Mi = 16). Switching is performed in three steps (ni=3).

By doing this, the ideal pixel clock W
A change in the position control clock fN that approximates the change in CLKL (line a in the figure) is obtained, and even though the frequency of the position control clock fN changes stepwise, the actual pixel clock due to the action of the PLL circuit can be obtained. WCLKL frequency f
K changes continuously so that an ideal pixel clock can be obtained.

As a result, as shown in FIG. 17, for example, the frequency division ratio setting circuits 236 and 238 are initialized at the timing of the synchronization detection signal DETP shown in FIG. After the scanning time T has elapsed, the enable signal EN shown in FIG. Enable signal E from circuit 243
The output of N is stopped, the frequency modulation counter 241 is placed in a disabled state, and the division ratio is fixed at the initial value.

At this time, the division ratio Ni changes as shown in the same figure (c), and the frequency fo/N of the position control clock fN
As x changes as shown in the same figure (d), the frequency fK of the pixel clock WCLK changes as shown in the same figure (e), which corresponds to the change in scanning speed shown in the same figure (b). More will come later.

Next, the frequency fK of the pixel clock WCLKL is
When changing the frequency fK, although this frequency is the reciprocal of the time T allocated to writing one pixel, the time T also changes as the frequency fK changes, and at this time, the scanning light (scanning beam)
If the intensity is constant, the light energy per pixel will be different between a place where the scanning speed is high and the time T is short and a place where the scanning speed is low and the time T is long, resulting in density unevenness in the image. . Therefore, the pixel clock WCLK
The output (emission intensity) of the laser diode 210 is also changed according to the frequency fK of the laser diode 210.

Control of the emission intensity of this laser diode (LD) 210 will be explained.

First, the operation for setting the emission intensity of the laser diode 210 to a reference value will be described with reference to FIGS. 12 and 18.

The laser light emitted rearward from the laser diode 210 is received by the monitoring photodiode 211, and the photodiode 211 outputs a current corresponding to the amount of received laser light, that is, the emission intensity of the laser light, and the output is sent to the amplifier 261. It is amplified and converted into voltage VM, which is input to comparator 262 and compared with reference value VREF.

Then, the comparison result of this comparator 262 is VM<VREF
When , the up/down counter 270 enters the up-count mode, and when VM≧VREF, the up/down counter 270 enters the up-count mode.
The down counter 270 enters the down count mode.

On the other hand, the edge detection circuit 264 detects the frame synchronization signal FSY.
The rising edge of NC is detected, and the AND circuit 266 performs a logical product of this edge detection signal and the frame synchronization signal FSYNC, and the output of the AND circuit 266 sets the flip-flop circuit 268 at the beginning of standby mode. The Q output becomes a high level °H°, and the AND circuit 269 calculates the logical product of this Q output and the non-scanning signal. An enable signal EN is output to up/down counter 270.

Thereby, the up/down counter 270 counts up or down the clock. Then, the reference value data, which is the count value of the up/down counter 270, is D/A converted by the D/A converter 215 to become an analog reference value signal, which is sent to the LD [dynamic circuit 217] via the adder 252. The LD drive circuit 217 supplies the laser diode 210 with a drive current according to the reference value signal.

Therefore, as the count value of up/down counter 270 increases, the emission intensity of laser diode 210 also increases, and as the count value of up/down counter 270 decreases, the emission intensity of laser diode 210 also decreases.

Then, when the magnitude relationship with the reference value VREF is reversed due to a change in the voltage VM according to the output of the photodiode 211 due to a change in the emission intensity of the laser diode 210, the up/down signal from the comparator 262 is also reversed. .

The rising or falling edge of the up/down signal from the comparator 262 is detected by the edge detection circuit 263, and a reset signal is input to the flip-flop circuit 268.
Q output of flip-flop circuit 268 is low level °L
When the output of the comparator 262 is inverted, the output of the enable signal EN to the up/down counter 270 is stopped, and the up/down counter 270 is in a disabled state and holds the count value when the output of the comparator 262 is inverted.

Therefore, the emission intensity of the laser diode 210 is maintained at the reference intensity corresponding to the reference value VREF.

Note that the edge detection circuit 263 may be configured to disable the up/down counter 270 only when the output of the comparator 262 is inverted from the low level °L° to the high level H'. In this case, comparator 2
When the output of the comparator 262 is inverted from the high level "H" to the low level "L", the explanation is similar to that described above, but the output of the comparator 262 changes from the low level "L" to the high level "H".

When inverted, the up/down counter 270 operates as an up counter with the disabled state released, the emission intensity of the laser diode 210 increases, and the output of the comparator 262 changes from a low level (L°) to a high level. When reversed to H°, up/down counter 270
will be disabled and hold its count value.

Further, the up/down counter 270 is configured to operate as an up counter when the output of the comparator 262 is at a low level "L°" and to operate as a down counter when the output is at a high level "H°". The driving current of the laser diode 210 may be inversely proportional to the driving current of the laser diode 210.

When scanning the photoreceptor 21, the non-scanning signal becomes low level (L), the run up/down counter 270 becomes disabled, and the laser diode 2
10 is not driven when scanning is in standby state, and is interrupted if the output setting of the laser diode 210 is not completed.
Output settings are restarted when non-scanning time occurs.

Note that when trying to set the output of the laser diode 210 to the reference value as described above, when the laser diode 210 has deteriorated, the emission intensity does not change no matter how much the drive current is changed, and therefore the up/down counter The count value of 270 is rFFHJ or roO
Even though the count has increased due to HJ, the output of the comparator 262 is no longer inverted, and at this time the up/down counter 270 starts counting again from the initial value, and this count amplifier detects the carry signal or borrow signal. A signal is output and this signal is applied to the light emitting diode 271.

Therefore, the light emitting diode 271 repeatedly blinks when the laser diode 210 deteriorates, so that the deterioration of the laser diode 210 can be easily detected.

In addition, the mode setting signal MD from the flip-flop circuit 268 forcibly sets the intensity modulation correction value from the intensity modulation up/down counter 240 (described later) to "0" so that it does not affect the reference value setting. ing.

Next, a description will be given of correction of the output (emission intensity) of the laser diode 210 in response to a change in the frequency fK of the pixel clock WCLK.

The intensity modulation up/down counter 240 inputs the clock fM from the frequency divider 237, similar to the frequency modulation up/down counter 241 used for frequency switching of the pixel clock WCLK described above, and inputs the clock fM from the frequency divider 237. The up/down switch output from the up/down switching circuit 242 based on the count value of the up/down counter 241
The counting mode is switched in response to the down switching signal U/D, and the operation is further controlled in response to the enable signal EN from the modulation operation management circuit 244.

In other words, here, the intensity modulation up/down counter 2
40 and a frequency modulation up/down counter 241, it is also possible to use one up/down counter in common.

Therefore, this intensity modulation up/down counter 2
The change in the count value obtained by counting the clock fM from the frequency divider 2 to 7 by 40 is the same as the change in the count value of the frequency modulation up/down counter 241, and this count value is sent to the D/A converter as correction data. It is converted into a correction signal outputted to 216.

In other words, the correction data output from the intensity modulation up/down counter 240 changes in stages according to the scanning speed shown in FIG. 17 (b), as shown in FIG. The correction signal from the D/A converter 216 that D/A-converts the data also changes according to the scanning speed.

Therefore, the correction signal from this D/A converter 216 and the reference value signal from the D/A converter 215 mentioned above are added,
This added value is used as a light emission intensity signal for LDg [4 motion circuit 21
7, the dynamic circuit 217 is input to LDll.
The drive current supplied to the laser diode 210 has a current value depending on the scanning speed, and therefore the emission intensity of the laser diode 210 changes depending on the scanning speed.

As a result, even if the frequency fK of the pixel clock WCLKL is changed, the amount of light per pixel can be kept at -, and density unevenness in the image can be suppressed.

Note that the calculation of the correction signal from the D/A converter 216 and the reference value signal from the D/A converter 215 is performed when the correction signal corresponds proportionally to the change in scanning speed (as described above). case), the light emission intensity signal may be obtained by addition or multiplication, and if the correction signal corresponds inversely to the change in scanning speed, the light emission intensity signal may be obtained by subtraction or division.

In addition, when changing the frequency fK of the pixel clock WCLK according to the pixel density and linear velocity as described above, multiple types of delay elements 22 of the modulation circuit 218 are prepared so that they can be switched with a switch, and the pixel density and linear velocity are changed. It is also possible to improve the on/off ratio of the light source within one pixel by switching the delay element 223 according to the speed.

Here, portions of the embodiments described so far that are directly related to the present invention will be explained with reference to FIG. 19 and subsequent figures.

FIG. 19 is a block diagram schematically showing the main parts of the embodiment described above, and shows the relationship between the main control board 75 and video interface 136 on the laser printer LP side and the exchange of signals with the host HT side. .

Inside the main control board 75 are the vC0248 that generates the internal clock WCLKO mentioned above, the phase selection inversion circuit 280, the inverter 281°, and the modulation circuit 2 mentioned above.
18; a corresponding launch circuit 282 and the like are provided.

Then, ■ Internal clock WCLK generated by C0248
Pixel clock XW is obtained by inverting the phase of O using an inverter 281.
CLK to the video interface 136.

The video interface 136 includes a video I/F circuit 191, a video I/F 191a for sending out pixel clocks, and a video I/F circuit for receiving image data from the host, although the connectors in FIG. 7 are not shown. 191b and are shown separately.

The videoni/F 191a is composed of a Schmitt trigger inverter and a line driver, and sends the pixel clock XWCLK from the main control board 75 as it is, and the inverted WCLK as the pixel clock to the host HT.

On the other hand, the video I/F circuit 191b consists of a line receiver and a Schmitt trigger inverter, and
It receives image data WDAT or XWDT from , and sends it to the latch circuit 282 in the main control board 75 as image data XWDAT.

In this main control board 75, as described above, the internal clock WCLKO is passed through the phase selection inversion circuit 280, which selects whether or not to invert the phase according to the specifications of the host side, and outputs the internal clock WCLKO as the pixel clock WCLKL. Supplied to the latch circuit 282 in the modulation circuit 218,
Image data XWDAT transferred from the host HT via the video I/F circuit 191b is latched and used as an actual write signal.

As shown in FIG. 20, this laser printer receives image data XWDA from the host HT with reference to the fall of the pixel clock
The pixel clock XWCLK is configured so that it can be input in synchronization with T, and as mentioned above, this pixel clock XWCLK is frequency-modulated to ensure uniform writing speed since no FE lens is used.

By the way, when connecting to a host with a built-in video interface like this printer, the host side has two configurations: one that transfers image data at the falling edge of the pixel clock XWCLK, and the other that transfers image data at the rising edge of the pixel clock XWCLK. There are two possible configurations to transfer.

Therefore, as mentioned above, the printer uses the pixel clock XW.
When the falling edge of CLK is used as a reference, the transfer of image data XWDAT from the host side is based on the pixel clock XWCL.
If the configuration is such that data is transferred based on the rising edge of the pixel clock XWCLK, the image data XWDA
The transfer of T will be delayed by half a cycle.

Also, the pixel clock XW is sent from the printer side to the host HT side.
CLK is sent, and on the host HT side, the pixel clock
When transferring image data XWDAT to the printer side in synchronization with LK, as shown in FIG. 21, the host HT The same figure reached (b)
The pixel clock XWCLK' shown in is delayed by a time Δt corresponding to the cable length, and this pixel clock x w CLK
′, the host HT side transfers the image data XWDAT to the video I/F circuit 191b, so the video I/F circuit receives the image data XWDAT sent from the host HT.
The image data XWDAT' that has reached the circuit 191b is delayed by a time Δt.

Therefore, the image data XWDAT' is shown in FIG.
As shown in the figure, the pixel clock XWCL shown in FIG.
The phase is delayed with respect to K by a time 2Δt corresponding to twice the cable length.

In other words, the image data XWDAT" is based on the fall of the pixel clock XWCLK' shown in FIG.

On the other hand, the image data VIDEOB obtained by modulating the image data XWDAT by the modulation circuit 218 is latched by the FF circuit 221 (see FIG. 9) at the rising edge of the pixel clock WCLKO as described above, so there is a phase lag as described above. Then, the output of the FF circuit 221 changes from a certain region, but since the pixel clock WCLKO is frequency modulated, there are regions where it changes and regions where it does not change, making the latch of the image data VIDEOB unstable.

Therefore, in this printer, the image data XWDAT is latched by the pixel clock WCLKL obtained by selectively inverting the internal clock WCLKO by the phase selection inversion circuit 280.
By eliminating the phase delay of half a period of the image data XWDAT with reference to the fall of K and using only the phase delay due to the cable length, the image data is prevented from being latched in an unstable region.

Figures 22 and 23 show VIDE for XWCLK.
Each signal WCLKO, XWCLK, VI when OB has a delay of more than half a cycle and when there is a delay of less than half a cycle
3 is a timing chart showing the phase relationship between DEOB and WCLKL.

Note that the video interface 136 can also be incorporated into the main controller 135 by using the main control board 75 and the video interface board 76 as the same board.

In this way, this printer is equipped with means for selecting the phase of the internal clock for latching the image data transferred from the host in synchronization with the transmitted pixel clock. Whether it is a host that transfers image data based on the rising edge of the pixel clock or a host that transfers image data based on the rising edge of the pixel clock,
Image quality is improved because image data can always be latched in a stable area.

In the above embodiment, an example in which the present invention is applied to a laser printer has been described, but it can also be applied to other image forming apparatuses such as copying machines and facsimile machines.

Effects As explained above, according to the present invention, the phase relationship between the pixel clock and the image data can be stabilized, and the image data can always be latched in a stable area, so that the image quality can be improved.

[Brief explanation of the drawing]

FIG. 1 is an external perspective view showing an example of an image forming apparatus embodying the present invention, FIG. 2 is a perspective view showing the unit in an open state, and FIGS. 3 and 4 are the same image forming mechanism. 5 and 6 are a plan view and a perspective view of the laser writing device, FIG. 7 is a block diagram of the control section and source section, and FIG. 8 is a block diagram of the control section and source section. 9 and 10 are block diagrams showing an example of the modulation circuit and timing diagrams for explaining its operation. Write control IC
and a block diagram showing different examples of the internal configuration of the clock generation circuit; FIG. 12 is a block diagram showing the configuration of the reference value setting circuit; FIGS. 16 to 18 are explanatory diagrams explaining the operation of each part; FIG. 19 is a block diagram schematically showing the main part of the embodiment of the present invention, FIGS. 20 and 21 are timing charts that similarly explain the relationship between the pixel clock and image data, and FIGS. 22 and 23. is EO from V for XWCLK
Each signal WCLKO, XWCLK, VID when B has a delay of more than half a cycle and when there is a delay of less than half a cycle
FIG. 3 is a timing chart showing the phase relationship between EOB and WCLKL. 1...Top unit 2-Lower unit 21...
Photoreceptor 24, laser writing device 106, polygon mirror 135, main controller 136, video interface 163, writing control unit 191a, 191b, video I/F circuit 201, writing control IC 203, clock generation circuit 210, laser diode 248, Voltage controlled oscillator (VC○) 280.280' / Phase selection inversion circuit 28 to inverter 282 / Latch circuit LP / Laser printer HT... Hostro 9 Procedural correction band May 2, 1988 Commissioner of the Japan Patent Office Kuni Ogawa Husband 1, Indication of the case Patent application No. 62-334094 2, Name of the invention Image forming device 3, Person making the amendment Relationship to the case Patent applicant 1-3-6 Nakamagome, Ota-ku, Tokyo (674) Ricoh Co., Ltd. - 4, Agent 6, 1-20 Higashiikebukuro, Toshima-ku, Tokyo 170 (Telephone 986-2380) Contents of amendment (1) "Also Form ... at the back of the right side and delete ". (2) Delete the statement ``Also...'' from lines 7 to 13 on page 5 of the same book. (3) Insert the phase-selected (for example, non-inverted) pixel clock WCLKL between the rWCL KO on page 28, line 11 of the same book and the clock terminal CKJ. “Clock generation circuit/
・・・・・・・・・・・・ ・・・Pixel clock WCL
Correct KLJ as follows. ffD-Inverted pixel clock X opposite to FF221
WCLKLJI (5) 1 internal clock WCLKO on line 20 of the same page in the same book
is corrected as "pixel clock WCLKL, il."
Correct "internal clock WCLKOJ" in line 6 to "pixel clock WCLKLJI." (7) Correct "rWCLKLJ" in line 6 on page 39 of the same book to [i'X
Corrected to WCLKLJJ. (8) “Exclusive OR circuit EXO” on page 42, line 3 of the same book
Correct RJ to "inverter INj." (9) Correct "WCLK" on page 48, line 8 of the same book to [i'WC
LKO,! l and rWcLKLJ in the 9th line as li′XW
CLKLj and correct them respectively. (10) "Pixel clock WCLKLJ" in lines 3 to 4 and line 8 on page 54 of the same book is replaced with "internal clock WCLKLJ".
Correct it to LKOJI. (11) “Pixel clock WCLK” on page 55, line 6 of the same book
” and “pixel clock WC” on the 9th line and 17th to 18th lines.
LKLj to the internal clock WCLKo,!
Correct it as l. (12) "Pixel clock WCLKl" in lines 9 and 13 of page 61 of the same book is replaced by "internal clock WCLK1".
o” and correct it. (13) “Pixel clock WCLK” on page 63, line 7 of the same book
"Pixel clock WCLK" in line 20 and LJ are corrected to "internal clock WCLKOJI." (14) "Pixel clock WCLK" in line 9 on page 66 of the same book.
" is corrected as "internal clock WCLKi." (15) Same book, page 68, line 12 (7) rWcLKOJ is corrected as [mWCLKL, Q, and "pixel clock" on line 16 is corrected as "internal clock." (16) Ibid., page 69, lines 1 and 11 (7) rWc
LKLJ, all 1rXWcLKL,! Correct it as l. (17) The drawings "Figure 1, Figure 4, Figure 9, Figure 10, Figure 22, Figure 23" will be corrected as shown in the attached corrected drawings. that's all

Claims (1)

[Claims] 1 It has a built-in video interface, and sends a pixel clock, which is an inverted version of the internal clock, to the host side from the video interface, and uses the internal clock to transfer image data from the host side in synchronization with the fall of this pixel clock. An image forming apparatus that forms an image by latching, the image forming apparatus comprising: a phase selection means for selecting a phase of the internal clock.