JPH04126448A - Picture recorder - Google Patents

Abstract

PURPOSE:To generate each timing signal whose timing change differs from a same main scanning controller by storing a different main scanning data to a RAM in response to the selection designation such as resolution, image forming speed or print area in the main scanning direction. CONSTITUTION:One of plural data groups stored in a ROM 30 is selected and transferred and stored in an area of a RAM 35 based on a state of a dip switch 31, a content of the ROM 30 or a command signal from other block in response to a kind of an optical system of a scanning unit used by a CPU 33 and its resolution (picture density) or a print speed and a print area or the like at initializing at application of power. Thus, a timing change in each timing signal is varied in many ways by revising a main scanning data stored in the RAM 35 in a main scanning controller 51.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image recording device such as a laser printer or a digital copying machine.

[Conventional technology]

In an image recording device such as a laser printer, a laser diode is controlled to blink in response to an image signal (VIDEO) synchronized with a 5-pixel clock signal (WCLK), and the laser beam generated by the laser diode is main-scanned to print on an image forming medium ( Images are formed by irradiating a photoreceptor (generally drum-shaped or belt-shaped).

In this type of optical scanning method using a laser beam, the laser beam from a laser diode is rotated and deflected by a polygon mirror (rotating polygon mirror) to perform main scanning (scanning), and at the same time images are scanned in a direction perpendicular to the main scanning direction. A method of sub-scanning by rotating the forming medium is well known.

In this case, since the polygon mirror deflects the light beam at a constant angular velocity, an fθ lens is generally used to keep the scanning speed on the surface to be scanned constant.

However, this f-theta lens is a special lens, large in size, and expensive, so recently optical scanning methods that do not use it have been proposed and put into practical use (for example, in Japanese Patent Laid-Open No. 62-32
(See Publication No. 768).

According to such an optical scanning method that does not use an fθ lens,
Since the scanning speed of the laser beam on the scanned surface is not constant, if the frequency fk of the pixel clock for image scanning is constant, distortion will occur in the written image.

Therefore, it is necessary to change the frequency fk of the pixel clock according to changes in the scanning speed on the surface to be scanned. That is, where the scanning speed is high, the frequency fk of the pixel clock must be increased accordingly, and where the scanning speed is low, the frequency fk must be decreased accordingly.

Incidentally, since the frequency fk of one pixel clock is the reciprocal of the time T allocated to writing information for one pixel, a change in this frequency fk corresponds to a change in time T.

Therefore, assuming that the amount of laser beam irradiation is constant, there will be a difference in the amount of exposure per pixel where the scanning speed is high (time T is short) and where the scanning speed is low (time T is long). As a result, the image density changes in response to changes in the scanning speed.

Therefore, in order to prevent such density changes from occurring, the drive current of the laser diode, which is the light source, is changed in accordance with the change in the frequency of the pixel clock, thereby changing the amount of light emitted (emission power).

Incidentally, in such an image recording apparatus, a timing signal having the following meaning is required in the main scanning period.

*PCDA...Scanning period of the effective printing area of the photoreceptor CURV...Scanning period of the pixel clock frequency modulation area and laser diode emission power variation area LSYNC...Print data VIDE for processing section
Synchronous timing for sending the O signal LGATE...Scanning period of the print area in the main scanning direction Book opening 5YNCI...Next scanning timing of the polygon mirror *5YNCO...Laser diode emission timing for the synchronizing signal These timing signals To generate this, a circuit as shown in FIG. 27, for example, has conventionally been used.

This circuit uses one counter that counts the reference clock 5CLK generated by the reference clock oscillation circuit 70 by being reset by the input of the beam detect signal DETP, which is a synchronization signal, and the count output is sent to the decoder group 72.
The respective decoders are manually decoded using fixed count values, and each timing signal (PCDE, CURV, LSYNC) as shown in FIG. 28 is generated.

LGATE, 5YNCI, 5YNCO).

[Problem to be solved by the invention]

However, the relationships among the timing signals generated by such a conventional main scanning timing signal generation circuit, that is, the periods T1 to T9 shown in FIG. 28, are constant.

Therefore, when trying to achieve different resolutions and image recording speeds with a single image recording device, or when trying to change the printing area in the main scanning direction on a page-by-page basis, it is necessary to use multiple stages of decoder circuits. Moreover, in some cases, the number of counter stages becomes redundant, resulting in an increase in the scale of one circuit, resulting in high costs.

In addition, in conventional image recording devices that employ such an optical scanning method, both the light amount modulation data for changing the amount of light emitted by the laser diode and the frequency modulation data for changing the frequency of the pixel clock, as described above, are It was also stored as a fixed value, for example, as a pull-up or pull-down at the input end of an IC, or as data in a ROM.

Therefore, when you want to perform light intensity modulation using multiple characteristics (for example, when you want to change one pixel density, when you want to change the light amount characteristics depending on the sensitivity of the sensor or image density, etc.), and when you want to perform frequency modulation using multiple characteristics. When it is desired to change the pixel density (for example, when it is desired to change the pixel density), it is necessary to change the state of the input terminal of the IC or replace the ROM, which is troublesome and leads to an increase in cost.

The present invention has been made in view of the above points, and in the image recording apparatus as described above, the generation timing of each timing signal necessary for main scanning of a laser beam within one main scanning period can be determined using a simple circuit. The first objective is to allow the configuration to be freely set, thereby making it possible to correspond to various resolutions, image forming speeds, or print areas in the main scanning direction.

Furthermore, it is possible to easily change the light amount modulation data or the frequency modulation data, and to arbitrarily control the light amount distribution of the laser diode and the frequency distribution of the pixel clock signal during main scanning of the image forming medium by the laser beam. This is the second purpose.

[Means for Solving the Problems] The present invention controls blinking of a laser diode according to an image signal synchronized with a pixel clock signal, and irradiates an image forming medium by main scanning a laser beam generated by the laser diode. In order to achieve the above object in an image recording apparatus that forms an image by a data register that latches the data read out from the RAM by the laser beam at a predetermined timing before the start of main scanning of the laser beam; a down counter that loads part of the data latched into the data register as an initial value and counts down; The sequencer includes a prescaler that prescales a clock supplied to the down counter using another part of the data latched in the register, and a sequencer that operates using a signal generated when the down counter overcounts as a clock. A main scanning controller is provided which generates each necessary timing signal within the main scanning period at a timing according to the main scanning control data in the RAM.

In the invention according to claim 2, there is provided a RAM for storing light intensity modulation data including a change amount, direction, and interval for changing the light emission amount of the laser diode, an address counter for generating address data of the RAM, and the address data. A data register that latches the light intensity modulation data read from the RAM at a predetermined timing before the start of main scanning of the laser beam, and an interval component of the latched light intensity modulation data is loaded into this data register and downloaded by the main scanning control clock. It consists of a down counter that counts, and an up/down counter that increases or decreases the output according to the direction of change by the value of the change amount component of the light intensity modulation data latched in the data register when the down counter counts over. a light amount modulator; a register that stores an initial value to be set in the up/down counter; a D/A converter that receives the output of the up/down counter as an input; A circuit for controlling a drive current is provided, and the light amount distribution of the laser diode is controlled for each main scan according to the light amount modulation data stored in the RAM.

In the invention according to claim 3, the RAM stores frequency modulation data including a change amount, direction, and interval for changing the frequency of a reference signal for generating a pixel clock signal.
and.

an address counter that generates address data of the RAM; a data register that latches frequency modulation data read out from the RAM according to the address data at a predetermined timing before the start of main scanning of the laser beam;
A down counter that loads the interval component of the frequency modulation data latched into this data register and counts down using the reference signal, and the amount of change in the frequency modulation data latched in the data register when this down counter counts over. a frequency modulator consisting of an up/down counter that increases or decreases the output by the value of the component depending on the direction of change; a register that stores an initial value to be set in the up/down counter; A frequency divider is provided to generate the reference signal at a frequency determined by the frequency, and the frequency distribution of the pixel clock signal is controlled for each main scan according to the frequency modulation data stored in the RAM.

Furthermore, the invention according to claim 4 is the image forming apparatus according to claim 3, further comprising a voltage controlled oscillator.

It has a frequency divider that divides the oscillation output of this voltage controlled oscillator, and a phase comparator that inputs the output signal of this frequency divider and the above-mentioned reference signal, and passes the output of this phase comparator through a low-pass filter to A phase locked loop (PLL) circuit configured to be input to a controlled oscillator is provided, and the oscillation output of the voltage controlled oscillator is used as a pixel clock signal.

[For production]

In the image recording apparatus according to the first aspect, the main scanning controller generates each necessary timing signal from the sequencer within the main scanning period at timings according to main scanning control data stored in the RAM that can be arbitrarily set by the CPU.

Therefore, by storing different main scanning data in the RAM according to the selection designation of the resolution, image forming speed, printing area in the main scanning direction, etc., the same main scanning controller can control the time period TI-1 shown in FIG. It is possible to generate timing signals each having a different T9.

In the image recording apparatus according to claims 2 and 3, each of the CP
Based on the light intensity modulation data or period number modulation data stored in RA, M, which can be set arbitrarily by U.

This is because the light intensity distribution of the laser diode or the frequency distribution of the pixel clock signal within each modulation region can be controlled for each main run of the laser beam.

A plurality of light intensity modulation characteristics can be realized with the same light intensity modulation device, and one frequency modulation characteristic can be easily changed.

Further, the image recording apparatus according to claim 4 is provided with a PLL circuit and uses the oscillation output of the voltage controlled oscillator as a pixel clock signal, so that the frequency distribution is controlled as described above by multiplying the reference signal. Since a distributed pixel clock signal can be obtained, the same pixel clock generation circuit can be used regardless of the pixel density or the type of optical device.

〔Example〕

Embodiments of the present invention will be specifically described below with reference to the drawings.

FIG. 2 is a schematic diagram of the mechanism of a laser printer which is an image recording apparatus to which the present invention is applied, that is, an embodiment of the present invention.

This laser printer 1 has an optional mass paper feed tray 12.
The system is configured by placing it on top.

When the print starts, the drum-shaped photoreceptor 2, which is an image forming medium, is rotated in the direction of the arrow (sub-scanning direction) by a main motor (not shown), and the main charger 3 scans the uniformly negatively charged surface with a laser beam. The unit 4 irradiates and exposes the drum with laser light that is blink-controlled in accordance with an image signal while main scanning in the direction of the drum axis, thereby forming an electrostatic latent image.

Furthermore, a toner image (visible image) is formed on the surface of the photoreceptor 2 by applying toner by the developing device 5 to the area where the negative charge has disappeared or decreased due to the exposure of this electrostatic latent image. The image is transferred to the resist by the transfer/discharge charger 6 onto a copying paper (recording paper) sent at a predetermined timing by the laser pair 7.

The transfer paper is separated from the photoreceptor 2, passed through the fixing device E by heating and applying pressure to fix the toner image, and is then ejected in the direction of arrow A (outside the machine) or transported for ejection. The transfer paper is fed out one by one from either the paper feed tray 11 or the bulk paper feed table 12, and the leading edge is held between the pair of registration rollers 7. After waiting once at the position where the photoreceptor 1 is placed, the pair of registration rollers 7 is driven again at a predetermined timing to send the photoreceptor 1 to a position facing the transfer/discharge charger 6 of the photoreceptor 1, which is the transfer position.

In the upper part of the laser printer 1, boards of a data controller 13 and a device controller 14, which will be described later, are housed to control the entire laser printer.

Laser Scanning Unit FIGS. 3 and 4 are respectively a plan view and a perspective view of the main parts of the laser scanning unit 4 described above. A diode (LD) unit 101 and a first cylindrical lens 102 attached near the center of the bottom surface. First mirror 103. A spherical lens 104, a polygon mirror (rotating polygon*) 106 that is rotated at a constant speed in the direction of the arrow by a polygon motor 105 attached to the rear of the bottom, a second mirror 107 attached to the front, and a second mirror 107 attached to the side of the bottom. A third mirror 110 is provided, and a synchronization detection sensor 111 is a photosensor attached to the side surface.

The LD unit 101 has a laser diode (to be described later) inside, a collimating lens that converts a diverging light beam emitted from the laser diode into a parallel light beam, and a sub-assembly that changes the shape of the light beam of the laser beam that has passed through the collimating lens. It is provided with a printed circuit board 114 in which an aperture member for shaping the laser diode into a short shape in the scanning direction is integrally incorporated and forms a part of an automatic output control (APC) circuit that controls the output of the laser diode.

Note that the laser diode of this LD unit 101 has a monitoring photodiode integrated therein that receives laser light emitted backward from the laser diode.

Further, the first cylindrical lens 102 functions to shape the laser beam emitted from the LD unit 101 in the sub-scanning direction on the photoreceptor 2 shown by the broken line in FIG. 4.

The spherical lens 104 narrows down the laser light reflected by the first mirror 103, forms a laser beam, refracts it obliquely upward by about 5 degrees, and makes it incident on the mirror surface 106a of the polygon mirror 106.

The polygon mirror 106 uses a round polygon mirror formed by curving each mirror surface 106a, and uses a post-object type optical deflector (light beam This is a type of optical deflector in which a deflector is placed after condensing the beam into a condensed beam.

The polygon mirror 106 is rotated at a constant speed by a motor 105 and reflects the irradiated light.

Due to the rotation, the angle of the mirror surface 106a that reflects the irradiation light with respect to the irradiation light gradually increases, and in the illustrated example, the mirror surface 106a facing the irradiation light increases every time it rotates 360°/6.
06a is updated, and the reflected light of the polygon mirror 106 is repeatedly swung.

The second mirror 107 reflects the laser beam (scanning beam) reflected by the polygon mirror 106 toward the photoreceptor 2 .

Further, the third mirror 110 is disposed outside the scanning area on the photoreceptor 2 by the laser beam reflected by the polygon mirror 10, and the third mirror 110 is arranged to pass the incident laser beam to the synchronous detection sensor 1.
Reflect towards 11.

Reference numeral 112 denotes a connection cable for guiding a beam detect signal (DETP) detected by this synchronization detection sensor 111 to a device controller 14, which will be described later.

According to this laser scanning unit 4, the LD unit 10
Laser light from 1 laser diode.

The light is collimated by an internal collimating lens, shaped by an aperture member, and then emitted.

The laser beam passes through the first cylindrical lens 102 and is reflected by the first mirror 103.

The light is condensed by the spherical lens 104 and refracted upward, and is incident on the mirror surface 106a of the polygon mirror 106.

The mirror surface 106a of this polygon mirror 106
The laser beam reflected by the second mirror 107 is further reflected by the second mirror 107 and is irradiated onto the photoreceptor 2 via the second cylindrical lens 108 .

At this time, by rotating the polygon mirror 106 in the direction of the arrow, the laser beam becomes a scanning beam that scans (main scanning or line scanning) the photoreceptor 2 in the direction of the arrow B shown in FIG. Main scanning on the photoreceptor 2 is repeated for each mirror surface 106a of the polygon mirror 106.

At the same time, the photoreceptor 2 rotates in the direction perpendicular to the main scanning direction (sub-scanning direction) as described above, and during this scanning, L
The laser diode of the D unit 101 is turned ON (energized) and 10FF (de-energized) according to the image signal to control blinking.
By selectively neutralizing the negatively charged surface of the photoreceptor 2 in minute dot units, an electrostatic latent image corresponding to the written image is formed on the photoreceptor 2.

In addition, the scanning beam reflected by the polygon mirror 106 (
The laser beam) is incident on the third mirror 110 before scanning the photoreceptor 2 and at a time corresponding to the main scanning break (switching of the mirror surface 106a and switching of the second line), and the reflected beam is reflected by the synchronization detection sensor. 111 and is detected.

As a result, a beam detect signal (DETP) is output from the synchronization detection sensor 111, which is input to a device controller 14, which will be described later, to control the scanning start timing by the laser beam, etc.

FIG. 5 is a block diagram showing an outline of the configuration of the control system of this laser printer.

A control section (controller) of this laser printer 1 is composed of a data controller 13 and a device controller 14.

The data controller 13 processes input information from the operation panel 15 and controls display on a display (not shown) of the operation panel 15.

Also word processors, personal computers, office computers, data processors.

It receives image data from a host computer such as a workstation, image editing processing device, etc., and transfers it to the device controller 14 as necessary.

The device controller 14 includes an LD driver 60, which will be described later.
In addition to the synchronization detection sensor 111 using the photo sensor described above, there are various sensors and switches.

A large number of input/output means such as motors and clutches are connected.

This device controller 14 is a data controller 13
In order to execute the print cycle designated by Control.

Furthermore, an optional sorter 179 duplex unit 18.
If mailboxes 19 and the like are connected, they are also controlled.

(Details of Equipment Controller) FIG. 6 is a block diagram showing the internal configuration of the equipment controller 14.

The main body of this equipment controller 14 is the laser printer 1
LS designed to execute a print cycle in which mechanical elements of the print engine are energized and deenergized at predetermined timings to record an image of a predetermined size and density on transfer paper.
I (large scale integrated circuit) 21.

This LSI 21 includes interface buffers 22 and 23 to which optional units such as a data controller 13 and a mass paper feed tray 12 are connected, and an oscillator 24 that uses a crystal oscillator to generate a clock signal ○SC of a constant frequency. a motor driver 25 that connects each motor;
Clutch driver 2 connected to each clutch, output buffer 27 connected to high voltage power supply, etc., and LD driver 60
A voltage/current conversion circuit 28 is connected to the input buffer 29, and an input buffer 29 is connected to each sensor including the synchronization detection sensor 111, a switch, and the like.

Furthermore, this LSI21 contains RoM30 which stores optical scanning characteristic compensation data and other data to adapt to various laser scanning units, and optical scanning characteristic compensation data and other data corresponding to the attached laser scanning unit. A dip switch 31 for specifying the number of prints and an EEPROM (non-volatile memory) 32 for storing print condition data such as the number of prints instructed by the data controller 13 are connected.

Here, the data stored in the dip switch 31 and the ROM 30 will be specifically explained with reference to FIGS. 7 and 8.

For example, the dip switch 31 is set to 8 as shown in FIG.
A series (eight) of switches is used, and they are divided into two groups of two and one group of four.

The group of switches SWI and SW2 functions as pixel density selection switches, the group of switches SW3 and SW4 functions as optical system selection switches, and the group of switches SW5 to SW8 functions as lateral registration adjustment switches.

1 (ON) 1 for each switch in each of these groups
The following selections can be made by combining 0 (○FF).

<Pixel density selection switch> SWI 5W2 0 0 240DPI 0 1 300DP1 1 0 400DP1 1 1 480DPI (DPI: dots/inch) <Optical system selection switch> SW3 5W4 00 Curved rotating polygonal silver 0 1 Rotating deflector + flattening lens 1 1 carbano mirror 1 1 rotating deflector + fθ lens Here, the rotating deflector is a rotating polygon mirror or a hologram scanner.

<Horizontal registration adjustment> SW5 SW6 5W7 0 0.

W8 0 -64 Dot 1 -56 Dot 0 -48 Dot 1 -40 Dot 0 -32 Dot 1 -24 Dot 0 -16 Dot 1 -8 Dot 0 +/-0 dot (center value) 1 + 8 Dot 1010 + 16 Dot 1 0 1 1+24 dots 1100+3
2 dots 1 1 0 1+401-knit 1110
+48 dots 1 1 1 1 + 56 dots (-) in this horizontal register, the image is written from the left side by a dot distance from the center value with respect to the paper passing direction. For (+), the image is written from the right side by a dot from the center value in the paper feeding direction.

In this embodiment, four types of optical systems and four types of recording pixel densities can be selected for each optical system.

Therefore, the RoM30 in FIG. 6 has a recording pixel density (
Indicates 240DPI, 300DPI, 400DPI, 4
80 DPI (not shown), different optical scanning characteristic compensation data (consisting of main scanning control data, light amount modulation data, and frequency modulation data) are stored.

This optical scanning characteristic compensation data is selected by the switches SW1 to S'W4 of the dip switch 31 described above.

FIG. 9 is a block diagram showing the internal configuration of the LSI 21 in the device controller 14 shown in FIG.

This LSI 21 has a CPU 33. Exposure controller 34
．． RAM35. A/D converter 36゜capo)
(Ilo)37. Address decoder 38, serial interface controller 39.40. Timer 41-4
3. Interwoven controller 44. and a D/A converter group 45.

Note that each of the above parts is connected to an address bus 46 and a data bus 47.
are interconnected by.

Immediately after the power is turned on, the CPU 33 inputs the 8-bit data from the dip switch 31 to the input/output port (Ilo).
37, and the optical scanning characteristic compensation data (main scanning control data, light intensity modulation data,
Frequency modulation data) is read from the ROM 15Q shown in FIG. 6 and written into the RAM 35.

Exposure control o --1y 34 is set by CPU 3';
It operates based on the data read from M30. Therefore, the CPU 3') transfers the data read from the ROM 30 to the internal register 50 (explained after the exposure controller 34).
Figure 1).

The exposure controller 34 then uses its internal register 50.
generates a pixel clock signal WCLK according to the data of
In addition to setting the reference light intensity of the laser diode,
"! Generates a recording start signal in the main scanning direction based on the main scanning control data (count data) read from the i5, and directly outputs the light amount control data based on the light amount modulation data read from the RAM 35 from the image signal VIDEO. The signal is outputted to the LD driver 60 in FIG. 5 via the A converter group 45 and the voltage/current conversion circuit 28 in FIG. 6 to control the light emission timing and light emission power of the laser diode.

Details of exposure controller 1 [@ is a block diagram showing the internal configuration of this exposure controller 34.

In this exposure controller 34, the main scanning controller 51 controls CURV, LSYNC, LGAT based on the main scanning control data read from the RAM 35.
Generates various timing signals such as E.

The signal CURV is a modulation start signal that becomes active during the scanning period of the modulation region of the pixel clock frequency and the modulation region of the light emitting power or light amount of the laser diode,
By outputting this signal, the power controller 67 sends the interrupt signal INT to the interwoven controller 44 in FIG.
2, which is output from the LD driver 60 (described later) to the latch circuit 68 in response to the interrupt signal INT.
The value signals LDCTI and LDCT2 are latched.

The light amount modulator 52 transmits light amount control data to the D/A group 4 in FIG. 9 based on the light amount modulation data read from the RAM 35.
5 to change the amount of light emitted from the laser diode.

Frequency change! In the I unit 53, the CPU 33 uses the internal register 50.
The PLL reference signal CLKA is generated at a frequency set to , and the PLL reference signal CLKA is modulated based on the frequency modulation data read from the RAM 35.

The internal register 50, which is instructed by the decoder 35 that decodes the address when writing data, contains the CPU 3
i5 writes laser diode light amount upper limit data and light amount lower limit data, reference frequency data of PLL reference signal CLKA, test pattern data, etc.

The test pattern generator 56 generates a test pattern based on the data written in the internal register 50 by the CPU 35 .

The video controller 57 includes a test pattern generator 56
test patterns generated by the data controller 13
The image data sent from the main scanning controller 51
and modulate it based on the output of.

Generates image signal VI DEO.

The timing generator 54 generates a timing signal φvT based on the input clock signal O8C from the oscillator 24.
o w Tt t Generate T2 ・Timing signal φ
is a signal that determines the timing at which the exposure controller 34 accesses the RAM 35, and the timing signal To +
TI and T2 are signals that determine the timing for reading main scanning control data, light amount modulation data, and frequency modulation data from the RAM 35.

That is, as shown in FIG. 14, the main scanning control data is transferred to the timing signal T1 at the falling edge of the timing signal To.
The light intensity modulation data is transmitted at the falling edge of the timing signal T2.
Frequency modulation data is read at the falling edge of .

In addition, 'roy'rt? For both T2, φ is 3
These are frequency-divided clock signals, and the phases are shifted from each other by one cycle of φ.

Further, as the clock signal oSC, the reference clock signal CLKo synchronized with the fall of the beam detect signal DETP from the synchronization detection sensor 111 shown in FIG. 5 is selected by the tap selector 64.

Frequency divider 58.59. Phase comparator 61. The voltage controlled oscillator 62 constitutes a phase locked loop (PLL) circuit 65 together with an external low-pass filter 68, and is reset by the beam detection signal DETP.
A pixel clock signal WCLK having a frequency specified by the frequency modulator 53 is multiplied by the PLL reference signal CLKA output from the frequency divider 58.

Frequency divider 63 divides this pixel clock signal WCLK to generate main scanning control clock 5CLK.

Controller A specific configuration example of the main scanning controller 51, its operation, and main scanning control data will be explained with reference to FIG. 10 and FIGS. 15 to 18.

The main scanning control data is a main scanning synchronization signal LSYNC in the main scanning direction (direction B shown in FIG. 4) starting from the beam detect signal DETP from the synchronization detection sensor 111 shown in FIGS. 3 and 4. , main scanning image area designation signal LGA
TE and other timing signals necessary for main scanning (PCDA, CURV, 5YNCI, 5YNCO)
This is the basic data for generating the switching interval of timing signals adjacent in time series, that is, the count when counting the period T1 to T9 between each timing signal shown in FIG. 28 using the main scanning control glock 5CLK. It is expressed as a value (DS1.DS2.DS3,...).

As shown in FIG. 10, the main scanning controller 51 has address counters 511 . Down counter 512, data register 513. Sequencer 514 and prescaler 51
It is composed of 5.

In addition, the ROM 30 is shown in FIG. 6, and the CPU 33 and RAM 3
5 is also shown in FIG. 9, and during initialization when the power is turned on, the dip switch 31 described above is activated.
Based on the state of the ROM 30, the contents of the ROM 30, or instruction signals from other blocks, the CPU 3E5 determines the type of optical system and resolution (pixel density) of the scanning unit to be used, or Depending on printing speed, printing area, etc.

1 out of multiple data groups stored in ROM30
One is selected and transferred to and stored in a certain area on RAM:35.

Then, as shown in FIG. 15, at the timing signal To immediately after the fall of the beam detect signal DETP, R
DSL (the first content of the main scanning control data), which is the content of the main scanning control data read from AM; 5, is taken into the data register 513 and then loaded into the down counter 512.

This main scanning control data consists of one byte, and each bit has a meaning as shown in FIG.

That is, the 6th to 0th bits of this data are loaded into the down counter 512 as the count value data described above,
This is the initial value and is counted down. The seventh bit (MSB) is 1-bit data indicating whether or not to skip, and is latched by the prescaler 515 and sequencer 514 at the same time as the other bits.

This 7th bit latched by prescaler 515 is
If it is 1°, the main scanning control clock 5CLK is prescaled (divided by 128 in this example).

That is, when the seventh bit of the main scanning control data is 0°, the down counter 512 counts down the value indicated by the 6th to 0th bits using the main scanning control clock 5CLK itself to generate the clock CLK1. , if the 7th bit is 1°.

The value indicated by the 6th to 0th bits is used as the main scanning control clock 5C.
A clock CLKI is generated by counting down using a clock obtained by dividing LK by 128.

The seventh bit latched to sequencer 514 is
It has the effect of ignoring the next CLKI input. As a result, even if the change interval of each signal generated by the sequencer 514, which will be described later, is more than 128 clocks of clock 5CLK, if the data with this 7th bit set to 1° is used,
It becomes possible to express it.

The down counter 512 generates a clock CLKI when its down count exceeds, increments the address value of the address counter 511, and updates the address value in the RAM 35.

That is, the DSL data access address of the RAM 35 is incremented by one.

Then, DS2, which is the content of the next address read out from the RAM 35 in synchronization with the timing signal TO, is taken into the data register 513, then loaded into the down counter 512, and counted down using the main scanning control clock 5CLK.

After that, when the down counter 512 counts over again, the clock CLKI is generated, and the address counter 512 generates the clock CLKI.
The address value of 11 is incremented, and the address value to the RAM 35 is updated. That is, RAM:! i5 D
Increment the S2 data access address by 1.

Again, DS3, which is the content of the next address read from the RAM 35 in synchronization with the timing signal TO, is loaded into the data register 513, then loaded into the down counter 512, and counted down with the main scanning control clock 5CLK. is executed to generate the clock CLK1, and the sequencer 515 generates the clock CLKI.
Count the PCDA and CU shown at the bottom of Figure 15.
RV, LSYNC, LGATE.

Each timing signal of 5YNCI and 5YNCO is generated.

Therefore, according to this main scanning controller 51, R
By changing the main scanning data (change timing count data) stored in AM35, the change timing of each timing signal (period T1 to T9 shown in FIG. 28) can be changed.
) can be changed in various ways.

Some of these timing signals, such as the CURV signal, are
It is applied to the light amount modulator 52 and frequency modulator 53 shown in FIG.

Here, even if the change interval of each of the above-mentioned signals generated by the sequencer 514 is longer than 128 clocks of clock 5CLK, it can be generated by using data in which the 7th bit of the main scanning control data is set to 1 degree. A case in which the main scanning control data transferred by the CPU 35 to addresses 1000 and beyond in the RAM 35 is as shown in FIG. 17 will be specifically explained with reference to FIG. 18 as an example.

First, since the 7th bit of the data at address 1000 is O°, the PCDE signal rises two clocks of 5CLK from the synchronization input (rising edge of DETP) according to the values of the 6th to O bits.

Similarly, since the 7th bit of the data at address 1001 is also 0°, the CURV signal rises one 5CLK clock after the rise of the signal PCDA according to the values of the 6th to 0th bits.

Next, since the 7th bit of the data at address 1002 is 1°, only the address counter 511 is incremented 128×1 clocks after 5CLK from the rising edge of the CURV signal, depending on the value of the 6th to 0th bits, and the LSYN
The C signal does not change. Then, according to the data at address 1003, after 3 clocks of 5CLK, the LSYNC signal rises after 128Xl+3=131 clocks from the rise of the CURV signal.

11. A specific configuration example of the light amount modulator 52, its operation, and light amount modulation data will be described with reference to FIG. 11, FIG. 19, and FIG. 20.

The light intensity modulation data is data for changing the light emission amount of the laser diode based on the laser diode light intensity upper limit data written in the internal register 50 of the exposure controller 34 (see FIG. 1) by the CPU 3E5 in FIG. 9. .

As shown in FIG. 19, it is composed of one byte, and includes the amount of change (5th and 6th bits) DPnV for changing the light emission amount of the laser diode, the direction of change (7th bit) U/D, Interval of change (0th to 4th bit)
This data includes components of DPnI.

As shown in FIG. 11, the light amount modulator 52 has an address counter 521 . Down counter 522. data register 5
23 and an up/down counter 524.

Then, as shown in FIG.
The DPI (the first DPI of the light intensity modulation data), which is the content of the light intensity modulation data read from the RAM 35 in the figure, is
After taking in the data register 523, the interval component DPII is loaded into the down counter 522.

While the CURV signal generated by the main scanning controller 51 is at a high level, the laser diode light amount upper limit data PREF written by the CPU 33 in the internal register 50 of the exposure controller 34 is transferred from the up/down counter 524 to the D/A converter group 45. + CU is output to the D/A converter 454, which will be explained with reference to FIG.
When the RV signal becomes low level, the down counter 522 generates the clock CLK2, and the data DP indicating the amount of change in the light amount included in the DPI, which is the content of the light amount modulation data.
The up/down counter 524 changes its output by IV according to the up/down instruction data U/D, and now U/
If D is a down instruction, then PREF-DPIV
Output.

Also, the address counter 521 is activated by the clock CLK2.
The address value of the RAM 35 is updated. That is, the DPE and data access address of the RAM 35 are incremented by one.

Then, after taking into the data register 523 DP2, which is the content of the next address read from the RAM 35 in synchronization with the timing signal T1, the interval component D
P2I is loaded into the down counter 522 and counted down using the main scanning control clock 5CLK.

When the down counter 522 counts over, it generates a clock CLK2, and the up/down counter 524 changes its output to up/down instruction data U/D by the amount of data DP2V that indicates the amount of change in the amount of light included in the data DP2.
Assume that U/D is also a down instruction.

Output PRFE-DPIV-DP2V.

At the same time, the address value of the address counter 521 is incremented, and the address value to the RAM 35 is updated. That is, the DP2 data access address of the RAM 35 is incremented by one.

After DP3, which is the content of the next address read from the RAM 35 in synchronization with the timing signal T1, is taken into the data register 523, it is loaded into the down counter 522 and down-counted with the main scanning control clock 5CLK.

Thereafter, the process is executed in the same manner, and the output from the up/down counter 524 is changed every time the clock CLK2 is generated, thereby controlling the amount of light emitted by the laser diode by the LD driver 60, which will be described later.

LD driver and related circuits FIG. 12 shows an LD driver 60, a D/A converter group 45 for controlling the amount of light, and a voltage/current conversion circuit 28.
A specific circuit example is shown below.

Although the D/A converter group 45 is also shown in FIG. 9, it is located in the LSI 21 in FIG. 6 and includes four D/A converters 45.
1 to 454, and an operational amplifier 435 used as an impedance converter.

The D/A converters 451 to 435 are all 8-bit converters, and are connected to the data bus of the CPU 33 shown in FIG. 9, so that the CPU 33 directly controls them.

The D/A converter 454 is connected to the 8-power terminal of the operational amplifier 435 and the output terminal of the up/down counter 524 shown in FIG. 11 of the light amount modulator 52 in the exposure controller 34 of FIG. 10.

Each output of the D/A converter 451, 452, 454 is
Each operational amplifier 281 to 283 of the voltage/current conversion circuit 28
to each transistor 284-286.

The digital values input to the D/A converters 451 to 453 are converted into corresponding analog output voltages, which are further converted into currents Ipa, Iρb, and Ipd by the voltage/current conversion circuit 28, respectively.

Note that the D/A converter 453 converts the digital value set by the CPU 33 into an analog voltage and outputs the analog voltage.
The impedance is converted by the operational amplifier 435 and the D/
Reference input voltage V ref of A converter 454
It is given as follows.

From this voltage/current conversion circuit 28, a current ■ρa is generated.

When the added value IPT of Ipb and Ipd is supplied to the LD driver 60, the LD driver 60 inputs it to the operational amplifier 6.
01, and the power transistor 602 causes a drive current ILD corresponding to the current IPT to flow through the laser diode LD, thereby controlling the amount of light emitted from the laser diode LD.

This current Ipτ and drive current ILD form a linear function with a negative slope, as shown in FIG. Therefore, by changing the digital input values of the D/A converters 451 to 454, it becomes possible to control the drive current ILD.

Note that the on (lighting)/off (lighting out) of the laser diode LD is controlled via the inversion circuit 603 by the image signal VIDEO input from the video controller in FIG.

That is, when the one-image signal VIDEO is at a high level indicating non-recording, the output of the inverting circuit 603 is at a low level, so that the anode side of the laser diode LD is grounded via the diode D1, and the laser diode LD is turned off.

When the image signal VIDEO is at a low level indicating recording, the output of the inverting circuit 603 is at a high level, so that a drive current ILD from the power transistor 602 flows through the laser diode LD, turning it on.

The amount of light emitted by the laser diode LD is detected by a monitoring photodiode PD, and the detection voltage adjusted by the variable resistor VR is compared with comparison voltages Va and Vb by comparators 604 and 605, and the comparison result is
It is output to the exposure controller 34 as value signals LDCTI and LDCT2.

The comparison voltages Va and Vb are determined by the resistance values of the resistors R1yR2vR3, and as shown in FIG.
The resistance values of the resistors R1, R2, and R3 are set so that the DCT2 is inverted corresponding to the minimum light amount P@in.

The exposure controller 34 has an APC interrupt function,
Exposure controller 34 shown in FIG.
An APC interrupt is generated by setting register 50 in the .

At this time, the 1-image signal VIDEO (in this case, the laser diode movement command signal) becomes active.

Laser diode LD starts emitting light.

Thereafter, the exposure controller 34 generates an interrupt signal INT to the CPtJ33, and at the same time generates a binary signal LDCTI.
, LDCT2 are latched by the latch circuit 66 and stored in the register 50.

The CPU 33 executes its LDCTI in the interrupt processing routine.
The amount of light emitted from the laser diode LD is controlled by reading the value of LDCT2 and changing the digital input values of the D/A converters 451 to 453 based on the result.

The D/A converter 451 performs rough control of the amount of light, and
/A converter 452 uses resistor Ra of voltage/current conversion circuit 28 to perform fine control.

By selecting the value of Rb, the amount of change in the current value IPT per ILSB is changed.

For example, by setting the resistors Ra and Rh so that ILSB of the D/A converter 451 is equal to 235LSH of the D/A converter 452, the same control as an A/D converter corresponding to maximum 16 bits can be performed.

Furthermore, the light amount modulation data from the up/down counter 524 in the light amount modulator 52 shown in FIG. 11 is input to the D/A converter 454 to modulate the light amount of the laser diode LD.

That is, if the image signal VIDEO records all dots in one line (low level), the drive current ILD of the laser diode LD is changed by the output of the up/down counter 524 in the light amount modulator 52 shown in FIG.
roughly represents a current level distribution in the main scanning direction as shown in FIG.

The light amount reference data PREF is an energization level controlled by the light amount upper limit data Pmax of the laser diode LD.

In Fig. 25, ±DPnV (n=1.2°3, ・
...) is the data that changes the light amount included in DPn, which is the content of the light amount modulation data, and its +
specifies an increase in the DPnV step of the energization level, - specifies a decrease in the DPnV step of the energization level, and the interval component DPnI of DPn (n=1.2, 3...
・) specifies the amount of main scanning progress.

For example, in DPnI, main scanning control clock 5CLK is
This means that the current level is increased or decreased by a DPnV step when the current level advances by a PnI pulse.

l1m Next, referring to Fig. 13, Fig. 21, Fig. 22, etc.,
Frequency modulator 53 and frequency modulation data and PL in FIG.
The L circuit 65 and the like will be specifically explained.

The frequency modulation data is stored in the PLLJ input into the internal register 50 of the exposure controller 34 by the CPU 33 in FIG.
Based on the reference frequency data FINT of f$ signal CLKA L:
, is data for changing the frequency of the PLL reference signal CLKA.

As shown in FIG. 21, it consists of one byte, and includes the amount of change (5th and 6th bits) DFmV for changing the frequency of the PLL reference signal CLKA, and the direction of change (7th bit) U/D. , the interval of change (0th to 4th bits) is data including a component of DFmI.

As shown in FIG. 13, the frequency modulator 53 includes address counters 531 . The down counter 532 is composed of a data register 353 and an up/down counter 534.

This frequency modulator 53 supplies data specifying the frequency of the PLL reference signal CLKA to the frequency divider 58 in FIG.
It functions to cause the frequency divider 58 to generate the PLL reference signal CLKA of the designated frequency.

First, to explain this frequency divider 58, this frequency divider 58 is a down counter, and the reference clock signal CLKo is equal to the number of frequency data provided by the 1-frequency converter ti4.
When counted, a pulse with a length of 10 clocks of the reference clock signal CLKO is output. This is repeated and output as the PLL reference signal CLKA.6 If the frequency data provided by the frequency modulator 53 does not change,
The PLL reference signal CLKA is output as a pulse with a constant length and a constant cycle, but when the frequency modulator 53 changes the frequency data, the pulse width remains the same but the cycle changes.PLLJ! A quasi-signal CLKA is output.

Therefore, as shown in FIG. 22, this frequency modulator 53 uses the contents of the frequency modulation data DFl (the first part of the frequency modulation data) read out from the RAM 35 at the timing signal T2 immediately after the fall of the beam detect signal DETP. DPI) into the data register 533, and then its interval component DFII is transferred to the down counter 53.
Let's talk about 2.

While the CURV signal generated by the main scanning controller 51 is at a high level, the up/down counter 534 outputs the reference frequency data FINT of the PLL reference signal CLKA, which the CPU 33 has written to the internal register 50 of the exposure controller 34, to the frequency divider 58. However, when the CURV signal becomes low level, the down counter 532
LK3 is generated, and the up/down counter 534 changes its output according to the up/down instruction data U/D by the amount of frequency change data DFIV included in the DPI, which is the content of the frequency modulation data.

If it is assumed that U/D is a down instruction, F I NT-DFIV is output to the frequency divider 58 .

Also, the address counter 531 is activated by the clock CLK3.
The address value of is incremented, and the address value of the RAM 35 is updated. That is, the DFI data access address of the RAM 35 is incremented by one.

Then, after taking in data DF2, which is the content of the next address read from the RAM 35 in synchronization with the timing signal T2, into the data register 533, the interval component DF21 is loaded into the down counter 532, and P
Downcount is performed using the LL reference signal CLKA.

When the down counter 532 reaches a count over, it generates a clock CLK3, and changes the output from the up/down counter 534 to up/down instruction data U/D by the amount of frequency change data DFZV included in the data DF2.
Now, if U/D is a down instruction, FINT-DFIV-DF2V is sent to the frequency divider 58.
Output.

At the same time, the address value of the address counter 531 is incremented, and the address value stored in the RAM 35 is updated. That is, the DF2 data access address of the RAM 35 is incremented by one.

After data DF3, which is the content of the next address read from the RAM 35 in synchronization with the timing signal T2, is taken into the data register 533, the interval component DF31 is loaded into the down counter 532, and the P
Downcount is performed using the LL reference signal CLKA.

Thereafter, similar operations are performed to generate the clock CLK3, change the output from the 7-up down counter 534 to the frequency divider 58, and modulate the PLL reference signal CLKA.

Since the frequency modulator 53 changes the count value given to the frequency divider 58 in this way, the frequency of the PLL reference signal CLKA generated by the frequency divider 58 changes corresponding to 29.

Due to the operations of the frequency modulator 53 and the frequency divider 58, the PLL reference signal CLKA is stored in advance in the ROM'50 in FIG. 6, roughly as shown in FIG.
This shows the frequency modulation distribution in the main scanning direction defined by the frequency modulation data written in the RAM 35 by U33; and the reference frequency data FINT of the PLL reference signal CLKA.

In Fig. 26, ±DFmv (m=1,2°3,...
...) is data on the amount of change that changes the frequency included in DFm, which is the content of frequency modulation data, where + indicates an increase in DFmV step of the frequency, and - indicates a decrease in DFmV step of the frequency. Specify each,
Interval component DFmI of DFm (m=1, 2, 3.
...) specifies the amount of main scanning progress.

For example, in DFmI, the main scan is the PLL reference signal CLKA.
This means that when the PLL reference signal CLKA advances by DFmI pulses, the frequency of the PLL reference signal CLKA is stepped down by DFmV.

In FIG. 1, a PLL reference signal CLKA generated by a frequency divider 58 is input to a phase comparator 61.

This phase comparator 61, together with a frequency divider 59 for pixel clock signal WCLK, an external low-pass filter 68, and a voltage controlled oscillator 62, constitutes a PLL circuit 65 that generates pixel clock signal WCLK at a frequency specified by one frequency modulator 53. are doing.

Then, by providing a pixel clock signal WCLK synchronized with the PLL reference signal CLKA from the voltage controlled oscillator 62 of this PLL circuit 65 to the video controller 57 and the frequency divider 63, the image data from the data controller 13 is transferred to the video controller 57. is the pixel clock signal W
It is serially read out in synchronization with CLK, and after signal processing is performed, it is output as an image signal VIDEO and is applied to the LD driver 60 shown in FIG.

The operations of the light amount modulator 52, frequency modulator 53, etc. explained above, and
The laser diode LD in the LD unit 101 shown in FIG. 3 and FIG.
In this case, energization is performed with a current level distribution as shown in FIG.

Furthermore, the frequency of the one-pixel clock signal WCLK is such that the PLL reference signal C exhibits a frequency modulation distribution as shown in FIG.
The frequency distribution is multiplied by LKA, and one main scanning line of dot recording is performed in synchronization with this pixel clock signal WCLK.

Note that the current level distribution as shown in FIG. 25 and the current level distribution as shown in FIG.
For the frequency distribution shown in the figure, arbitrary distribution characteristics can be obtained by setting (changing) the light amount modulation data and the frequency modulation data.

Therefore, in this embodiment, four groups of data shown in FIGS. It can be arbitrarily selected and set.

Since scanning areas may shift between different types of laser scanning units, the timing signal that determines the main scanning image area is also determined for each type of laser scanning unit, and the main scanning control data is also adapted to each of the four types of laser scanning units. Four groups of data are stored in the ROM 30.

Each group has four sets of data corresponding to four sets of recording pixel densities.

[Effects of the Invention] As described below, according to the invention set forth in claim 1, each of the necessary operations within the main scanning period is performed at the timing according to the main scanning control data stored in the RAM, which can be set arbitrarily by the CPU. Since a timing signal is generated, by storing different main scanning data in RAM according to the resolution, image forming speed, printing area in the main scanning direction, etc. of the image recording device, changing timing can be generated from the same main scanning controller. Different timing signals can be generated. Furthermore, the configuration of the main scanning controller for this purpose is relatively simple.

Therefore, it is possible to support different resolutions, printing speeds, printing areas, etc. at low cost.

Further, according to each of the inventions described in claims 2 to 4, based on the light intensity modulation data or period number modulation data stored in the RAM that can be arbitrarily set by the CPU, each modulation region is Since it is possible to control the light intensity distribution of the laser diode or the frequency distribution of the pixel clock signal, the same light intensity modulation device can realize the light intensity modulation characteristics of the antinodal number, and it is also easy to change the single frequency modulation characteristics. .

Therefore, in an optical scanning image recording apparatus that does not use an fθ lens, it is possible to easily deal with changes in pixel density, photoreceptor sensitivity, image density, etc., and it is possible to always obtain images without distortion or density unevenness.

Furthermore, by providing a PLL circuit and using the oscillation output of the voltage controlled oscillator as the pixel clock signal, it is possible to obtain a pixel clock signal whose frequency distribution is multiplied by the reference signal whose frequency distribution is controlled for each main scan. Therefore, the same pixel clock generation circuit can be used regardless of the pixel density or the type of optical device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the internal configuration of the exposure controller 34 in FIG. 9. FIG. 2 is a schematic configuration diagram of the mechanism of a laser printer according to an embodiment of the present invention, FIGS. 3 and 4 are a plan view and a perspective view of the main parts of the laser scanning unit 4 in FIG. 2, and FIG. 5 is a block diagram showing an overview of the configuration of the control system of the laser printer shown in FIG. 2, FIG. 6 is a block diagram showing the internal configuration of the device controller 14 in FIG. 5, and FIG. FIG. 3 is a schematic diagram showing a configuration example of a switch 31. FIGS. 8(a) to 8(d) are explanatory diagrams of the storage state of different optical scanning characteristic compensation data for each optical system in the ROM 50 in FIG. 6. 9 is a block diagram showing an internal configuration of the LSI 21 in FIG. 6, FIG. 10 is a block diagram showing an example of the configuration of the main scanning controller 52 in FIG. 1, and FIG. 11 is a block diagram showing an example of the configuration of the main scanning controller 52 in FIG. 12 is a circuit diagram showing an example of the structure of the LD driver 60 and its related circuits in FIG. 5; FIG. 13 is a block diagram showing an example of the structure of the frequency modulator 53 in FIG. 10; Figure 14 shows the RAM shown in Figure 9! 15 is a time chart showing the timing of reading main scanning control data, light amount modulation data, and frequency modulation data from +5. FIG. 15 is a time chart for explaining the operation of the main scanning controller 52 shown in FIG. 11. 16 to 18 also show the main scanning controller 51.
FIG. 19 is an explanatory diagram for explaining the operation of the RAM! of FIG. 11. 15 is an explanatory diagram of light amount modulation data stored in 15. FIG. FIG. 20 shows the operation of the light amount modulator 52 shown in FIG.
21 is a time chart for explaining the 13th
22 is a time chart for explaining the operation of the frequency modulator 53 shown in FIG. 13, and FIG. 23 is an LD driver shown in FIG. 12. 60 is a diagram showing the relationship between the control current rpr and the drive current ILD of the laser diode in 60. FIG. FIG. 24 is a diagram showing changes in the light amount in the light amount modulation region of the laser diode LD, FIG. 25 is a diagram showing an overview of the current level distribution in the main scanning direction of the drive current ILFI of the laser diode, and FIG. PLL generated by frequency divider 58 in the figure
FIG. 3 is a diagram showing the frequency distribution of the reference signal CLKA in the main scanning direction. FIG. 27 is a block diagram showing an example of a circuit that generates each timing signal necessary for the main scanning period of a laser beam in a conventional image recording device, and FIG. 28 is a timing chart showing the relationship between each timing signal. . 1...Laser printer 2...Photoconductor 3...Main charger 4...Laser scanning unit 5...Developing device 6...Transfer/electrostatic charger 7...
Registration roller pair 8... Fixing device 9... Paper ejection conveyance path 10... Paper ejection tray 11... Paper feed tray
12...Mass paper feed No. 115...Data controller 14...Equipment controller 15...Scanning panel 21...LSI24...
Oscillator 28...Voltage/current conversion circuit 30...
・ROM 31...date switch 33・
...CPU 34...Exposure controller 35
...RAM 45...D/A converter group 50...Internal register 51 of exposure controller...
Main scanning controller 52... Light amount modulator 53... Frequency change! l11
54... Timing generator 56... Test pattern generator 57... Video controller 58, 59, 6E5... Frequency divider 60... LD driver 61... Phase comparator 6
2... Voltage controlled oscillator 64... Tap selector 65... PLL circuit 101... Laser diode (LD) unit 10B
... Polygon mirror 111 ... Synchronization detection sensor 511, 521, 53m ... Address counter 512
,522,532...down counter 513.523
, 533...Data register 514...Sequencer 515...Prescaler 524.534...Up/down counter; Self 5 Figure 3 (A) Curved polygon mirror (B) Rotating deflector + flattening lens (H) ) Galvano mirror (d) Rotating deflector + fθ lens 119 Figure 16 MSB SB Figure 17 m 18 Figure ■ FT" 1 Straw 23s Figure 24 Hold down Figure 25 Main scanning direction - m - Figure 27 Figure 1128

Claims (1)

[Claims] 1. A laser diode is controlled to blink in accordance with an image signal (VIDEO) synchronized with a pixel clock signal (WCLK), and a laser beam generated by the laser diode is main-scanned to irradiate an image forming medium. A RAM (35) for storing main scanning control data for main scanning the laser beam in an image recording apparatus that forms an image.
an address counter (511) that generates address data for accessing the R;
A data register (513) that latches the data read from AM at a predetermined timing before the start of main scanning, and a down counter (513) that loads part of the data latched into this data register as an initial value and counts down.
12) and another part of the data latched in the data register (513).
2), and a sequencer (514) that operates using a signal generated when the down counter overcounts as a clock, and from this sequencer to the RAM (35). 1. An image recording apparatus comprising a main scanning controller that generates each necessary timing signal within a main scanning period at timings according to main scanning control data. 2. A laser diode is controlled to blink in accordance with an image signal (VIDEO) synchronized with a pixel clock signal (WCLK), and the laser beam generated by the laser diode is scanned in the main direction to irradiate the image forming medium to create an image. In the image recording apparatus for forming an image, a RAM (35) stores light amount modulation data including a change amount, direction, and interval for changing the amount of light emitted from a laser diode, and an address counter (521) that generates address data for the RAM. According to the address data, the RA
A data register (523) that latches the light intensity modulation data read from M at a predetermined timing before the start of main scanning of the laser beam, and a main scanning control clock by loading the interval component of the latched light intensity modulation data into this data register. A down counter (522) counts down with (SCLK), and when this down counter counts over, only the value of the change amount component of the light intensity modulation data latched in the data register (523) is output according to the direction of change. A light amount modulator (5) consisting of an up/down counter (524) that raises or lowers the
2), a register (50) that stores an initial value to be set in the up/down counter (524), a D/A converter (454) that receives the output of the up/down counter (524), and this D/A converter (454). A circuit (2) that controls the drive current of the laser diode according to the output of the A converter.
8, 60), and the light amount distribution of the laser diode is controlled for each main scan according to the light amount modulation data stored in the RAM (35). 3. A laser diode is controlled to blink in response to an image signal (VIDEO) synchronized with a pixel clock signal (WCLK), and the laser beam generated by the laser diode is scanned in the main direction to irradiate the image forming medium to create an image. In the image recording apparatus for forming images, the pixel clock signal (W
A RAM (35) that stores frequency modulation data including the amount of change, direction, and interval for changing the frequency of a reference signal (CLKA) for generating CLK), and an address counter (531) that generates address data for the RAM. and the RA according to the address data.
A data register (533) that latches the frequency modulation data read from M at a predetermined timing before the start of the main scanning of the laser beam, and an interval component of the latched frequency modulation data is loaded into this data register to generate the reference signal (533). A down counter (532) that counts down with CLKA), and when this down counter overcounts, outputs only the value of the change amount component of the frequency modulation data latched in the data register (533) according to the direction of change. A frequency modulator (consisting of an up/down counter (534) that goes up or down)
53), a register (50) that stores an initial value to be set in the up/down counter (534), and a frequency divider that generates the reference signal (CLKA) at a frequency corresponding to the output of the up/down counter (534). Vessel (5
8), and according to the frequency modulation data stored in the RAM (35), the pixel clock signal (WCLK) is applied for each main scan.
An image recording device characterized in that the frequency distribution of the image is controlled. 4. The image recording apparatus according to claim 3, further comprising a voltage controlled oscillator (62), a frequency divider (59) that divides the oscillation output of this voltage controlled oscillator, and an output signal of this frequency divider and the reference signal ( CLKA) and a phase comparator (61) that inputs the phase comparator (CLKA), and the output of this phase comparator is passed through a low-pass filter (61).
8), a phase locked loop circuit configured to be input to the voltage controlled oscillator (62) through the pixel clock signal (WCLK) is provided, and the oscillation output of the voltage controlled oscillator (62) is used as the pixel clock signal (WCLK). Features of the image recording device.