JPH01176193A - Simultaneous broadcast trunk - Google Patents

Abstract

PURPOSE:To attain excellent function and economy even in a small sized system by retarding a received signal in a reception circuit by a prescribed time in a short distance and then sending the result to an extension communication circuit or the like. CONSTITUTION:When a transmission line is a long distance (e.g., within 400m), there is no delay in the reception circuit and a signal is sent to an extension speech circuit, a trunk line speech circuit or a conference speech circuit. In case of a short distance (e.g., within 200m), after the reception signal is delayed by a prescribed time (transmission time equivalent to 200m of transmission line) in the reception circuit, the signal is sent to an extension speech circuit 200, trunk line speech circuits 250A, 250B or a conference speech circuit 350. Thus, it is possible to connect a transmission line of a short or long distance to a terminal equipment and an output signal from a simultaneous broadcast circuit is sent simultaneously to each terminal equipment to be commanded. Thus, the signal is subjected to pulse code modulation (PCM) regardeless of a small sized key telephone set and the system copes with a long range transmission line.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a broadcast trunk for a key telephone device used for PC-1 (pulse code modulation) communications. Specifically, it aims to provide a simultaneous broadcast trunk using a new PCM that can arbitrarily connect terminal devices including telephones, data devices, etc. between central office lines and terminal devices, and perform simultaneous broadcasts. It is.

[Prior Art] When transmitting and exchanging many communication signals and data signals, there are generally two types of cases: time division and space division.

In the case of time division, as is well known, a call signal or the like is encoded into Oto or "1", and a large number of call signals are transmitted as a digital signal on one transmission line. Here, digital signal rate conversion and time division multiplexing are performed. In this time division multiplex transmission, the code arrangement and timing are determined in advance, and the receiving side separates the multiplexed call signals, rearranges the data order, etc., and then performs D/A conversion. You can now make calls.

In a space-division communication path, for example, the number of input and output lines corresponding to each terminal is exchanged by closing them with a cross point switch, and in this case, A/D conversion and D/D conversion are generally performed. No A conversion is performed and the signal is transmitted as an analog signal.

[Problems to be solved by the invention] In time division, PCM is used, and by increasing the bit rate, it is possible to multiplex as many communication channels as desired. , the cost per channel will decrease. However, in order to perform transmission using digital codes, an A/D converter,
D/A converter.

loader. Since a decoder and a speed converter are required, this often poses a problem of high cost in small-scale systems. For this reason, it has been difficult to add the function of a broadcast trunk at a low cost.

However, in space-division communication channels, A/D converters, D/A converters, and loaders are required for PCM transmission and exchange in order to transmit analog signals as they are. Although decoders and speed converters are not required, as the number of lines increases, the number of cross point switches in the exchange increases in proportion to the square of the number of lines, resulting in high costs. Ta.

Furthermore, it has been difficult to handle digitally encoded signals in space-division communication channels. Because there is a delay time (5 to 6 ns/m) in the transmission line and the phase between the transmission timing and the reception timing is shifted, it has not been possible to transmit and receive signals efficiently with a simple device. Therefore, it has been difficult to realize the simultaneous broadcasting function at low cost even in the space-division communication path.

[Means for Solving the Problems] The cost per line of the conventional time-division communication path and space-division communication path based on PCM intersect when the number of lines is about OO. That is, in systems with 100 lines or less of terminals, it is cheap to use the spatial type, and in systems with 100 lines or more, it is cheap and effective to use the time division type with PGM.

However, with recent advances in LSIC large-scale integrated circuit (LSIC) technology, time-division communication channels using PCM have become smaller and more economical. dominance has increased.

The present invention has been developed in view of these circumstances, and it is an object of the present invention to provide a small-scale system with excellent functionality and economy.

For this purpose, PCM using digital codes that are resistant to noise and easy to process is used, and a main control device including a broadcast circuit that characterizes the present invention controls each of a plurality of terminal devices, and a main control device that controls each terminal device. A transmission line for connecting to the terminal by two-wire ping-pong transmission, and a transmission line for sending signals to the transmission line and receiving signals from the transmission line between both ends of the transmission line and the terminal equipment and the main control equipment, respectively. A transmitter/receiver is provided, and the receiving circuit included in this main device is compatible with two-wire ping-pong transmission, and is compatible with transmission line lengths within a certain range (for example, within 20Qm) and transmission lines over long distances (for example, within 400 m). , roughly 600m or more).

This main control device includes a broadcast circuit, a receiving circuit,
In order to enhance the overall functionality of this system, a central office line communication circuit, an extension communication circuit, a conference communication circuit, a CPU interface circuit that interfaces with a CPU (central control unit) for controlling these circuits, and A timing circuit was provided to generate timing signals necessary for each circuit included in the main device.

Here, the broadcast circuit includes an OR gate for ORing signals from the station line and terminal equipment that are the sound source of the broadcast,
An AND gate is provided as a sending means for receiving the output of this OR gate and sending it to each terminal device that is to receive simultaneous broadcasting according to an instruction from the CPU.

[If the working transmission line is long distance (for example, within 400 m),
There is no delay in the receiving circuit, and the signal is sent to the extension telephone circuit, central office telephone circuit, or conference telephone circuit, and in the case of a short distance (for example, within 200 m), the signal is sent within the receiving circuit for a predetermined time (
After delaying the received signal (transmission time for 200 m of transmission line), the received signal is transmitted to the extension line communication circuit, office line communication circuit, or conference communication circuit.

Therefore, it has become possible to connect terminal devices using short-distance and long-distance transmission lines, and it has become possible to simultaneously send output signals from the broadcast circuit to each designated terminal device.

In this way, although it is a small-scale button telephone device, it has become possible to create a device that is PCM-based and has many functions that can be used with long-distance transmission lines.

[Example] The principle of a button telephone device having a broadcast trunk function according to the present invention is shown in FIG. 1A, and the waveforms at each part thereof are shown in the timing diagrams of FIGS. 1B, 1C, 1D, and 1E. This will be explained using a chart.

In FIG. 1A, 10 is a main controller including a broadcast trunk of the present invention, and this main controller 10 synchronizes with a clock 51 from a clock generator 50 to
<Central control unit> Signals 21, 22, 23, and 20
808 and address bus signals 25. Data bus signal 3
It operates according to 5. The main controller 10 has a signal 61A.
(61B.

61C), signal 108A (108B, 108C) and signal 1o9A (109B, 109C)
0A (60B, 60C) and transmission line 63A (63B,
63C) and transceiver 60D (60E.

60F> and signal 61D (61E, 61F> and signal 7
1A (718, 710) and signal 72A (72B.

72C), the terminal device 70A (70B, 70C)
) are connected. Roughly speaking, in this main control device 10, the office line 12A (12B>) is connected to the office line interface 11A.
(11B> via signal 14A (14B> and signal 15A
(Connected by 15B>. Signal 16A(1
6B>, the arrival at the station is detected by the CPU 20, or
It provides information for sending dial signals from the office line interface 11A (11B>).

With such a configuration, the terminal devices 70A, 70B, 70
Between C or each terminal device 70A (70B, 70C)
This makes it possible to communicate in any combination between the station and the central office line 12A (12B).

FIGS. 1B (a) and (b) show a signal 108A between the main controller 10 and the transmitter/receiver tJ60A.

109A and the signal 61A are shown, and (C) shows the signal on the transmission line 63A. Signals 108A and 109A in (a) are output from the main controller 10 in the first half of one frame (125 m>), and then from the transmitter/receiver 160A side (b)
The signal 61A is output in the latter half of one frame. The signals on the transmission line 63A in (C) are (a) and (b)
This shows how the signal shown in Figure 1 is transmitted.

FIGS. 1C (a) and (b) show the contents of signals 108A, 109A and signal 61A shown in FIG. 1B. Here, ST is the start bit, F is information for frame synchronization (hereinafter referred to as F bit), 87 to 80 are audio information (data information), and D is control information for connecting to the destination. (hereinafter referred to as D information), P
represents parity information (hereinafter referred to as P information) for maintaining DC balance in the transmission line 63A.

In FIG. 1D, uplink and downlink information of the transmission line 63A and their timing signals are explained, and (a> shows the signal 10
8A, 109A are shown, the signal 61A is shown at (d>), and the main controller 1 is shown at (b,), (c) and (e).
Signals 1268.1269.0 generated inside 0. and 13
77 is shown.

Here, the signal 1268 represents the transmission period of the audio information 87 to BO, the signal 1269 in (C) represents the transmission timing of the audio information 87 to 80 shown in (a), and the signal 1269 in (e) represents the transmission timing of the audio information 87 to 80 shown in (a). Signal 1377 is signal 6 shown in (d)
1A represents the reception timing signal of audio information 87 to BO.

(a) Signals 108A, 109A and (d) (7) Signal 6
1A, a guard time T1 is provided. This is a combination of the two signals 108A and 109A of type (a), which are convenient for transmitting 100% AMI signals from the main controller 10 side, through the transmitter/receiver 160A, and transmits the 100% AMI signals through the transmission line. 63A and enters the terminal device 70A as a signal 61D via the transceiver 60D, and from the terminal device 70A receiving this, audio information 87 to BO excluding the start bit ST and frame bit F, Control information and parity information P are sent to the transceiver 60D and the transmission line 63 by signals 71A and 72A.
A, the signal 6 of FIG. 1D (d) via the transceiver 60A
This is the time provided to prevent the trailing edges of the signals 108A and 109A shown in (a) from colliding with the leading edge of the signal 61A shown in (d) when received by the main controller 10 as 1A. .

FIG. 1E explains the influence of the length of the transmission path 63A on uplink and downlink information, and corresponds to FIG. 1D. In FIG. 1E, the signal of Ca> 1.08A, 109
As a result of sending A in the first half of the n-th frame, the terminal device 7
The signal 61A of (d> returned from the 0A side is delayed by the transmission path 63A and received in the nth frame, and in addition to the guard time T1, the trailing edge of this signal 61A and the (d>) a) signal 108A.

This point requires a guard time T2 provided to prevent collision with the leading edge of 109A. An addition time T3 of 2 bits is provided when a conference call is required in between. In this way, even on a short-distance or long-distance transmission line 63A, the terminal device 76A can be connected to the main control device 10.
the upstream signal in the direction and the terminal device 7 from the main control device 10 side.
Downlink signals in the 0A direction do not collide.

FIG. 1F shows a waveform diagram for explaining the reason why the length of the transmission line 63A is limited, and (a) shows
(b) shows the case where the length of the transmission line 63A is 2 meters, and (C) shows the case where the length is zero meters.
), audio information 87 to 80 constituting the signal 61A of (b)
A signal 1376 is shown having a period equal to the period of each bit of . With respect to the signal 61A of (b), the signal 61A of (a> causes a delay time Td of 2Xe meters in the transmission line 63A, but this delay time Td is 1
Must be within bits. Otherwise, it would be impossible to distinguish it from the next bit. In the present invention, the delay time Td (0 to 7/8 bits) is set with a margin of 1/8 bit, for example. If the bit rate is, for example, 256 bps! is approximately 200 meters.

FIG. 1G shows the principle when a key telephone device is connected to a central office line.

The terminal devices 70A, 70B, and 70C are telephones and other data devices, and these terminal devices are connected to the central office line communication circuit 25.
It is connected to the office line 12A via OA and office line interface IIA. This office line communication circuit 250A includes the office line 1
The signal 15A is sent to the S/S register 26 from the 2A side via the office line interface 11A in the latter half of one frame.
The signal 268A is taken in by the OA, and in the first half of the next frame, the signal 251A is sent from the demultiplexer 27OA to one of the terminal devices 70A to 70C.
, 252A, or 253A.

From the terminal devices 70A to 70C side, for example, the terminal device 7
The signal 162A from 0A is selected by the multiplexer 28OA, is taken into the S/S register 260B that performs serial input and serial output in the second half of one frame, and is input to the S/S register 260B in the first half of the next frame.
A signal 268B is output from 0B, and sent to the office line 12A via the office line interface 11A. In this way, communication between the office line 12A and the terminal devices 70A to 70C is performed.

FIG. 1H shows a principle diagram of an extension call trunk that allows communication between terminal devices within a key telephone device without going through a central office line.

The signal 162A transmitted from the terminal device 70A is applied to the multiplexers 21OA and 210B, but is selected by the multiplexer 21OA by a control signal not shown here, and the selected signal 21
8A is S/S register 2 for serial input and serial output.
2OA in the second half of one frame and outputs it as a signal 225A in the first half of the next frame, which is applied to a demultiplexer 227A and is output as a signal 23 by a control signal not shown here.
6A and applied to the terminal device 70B.

The transmission signal 162B from the terminal device 70B is selected by the multiplexer 21081 using a control signal (not shown), outputs the signal 218B, and sends the signal 218B to the S/S register 220B.
is captured in the second half of one frame and output as signal 225B in the first half of the next frame, which is applied to demultiplexer 227B and selected by a control signal (not shown) to produce signal 2.

358 and is applied to the terminal device 70A.

FIG. 11 shows a principle diagram of a conference call trunk that allows simultaneous communication between two or more terminal devices.

Here, a conference call between terminal devices 70A, 70B, and 70C is illustrated, and a signal 61A (B, C) output from the terminal device 70A (B, C) is connected to a conference call circuit that enables the conference call. Multiplex circuit 360 within 350
There, in the latter half of one frame, the respective signals are accumulated, and are sent to the adder 430 as a bus signal 420 from the multiplex circuit 360 in a time-sharing manner during the guard time T2 explained in FIG. 1E. Apply.

This adder 430 adds the signals from each terminal device 70A (B, C) sent by the bus signal 420, outputs the addition result as a bus signal 652, and applies it to the demultiplex circuit 660. There is.

In the demultiplex circuit 660, the terminal device 7OA (
For B and C), the signal 693 (694, 695) is output in the first half of the frame immediately after the guard time T2. Here, the signal 693 is transmitted to the terminal device 708,
The contents of signals 61B and 61C output from 700 are added. Similarly, signal 694 is
Signal 695 represents the addition result of the contents of signals 1A and 61C, and signal 695 requires the addition result of signals 61A and 61B.

In this way, a conference call is possible.

FIG. 1J shows the principle of the broadcast trunk of the present invention for simultaneously transmitting the same information to all or a designated part of a large number of terminal devices connected to a key telephone device. A diagram is shown.

Here, each signal 239 is transmitted from the terminal devices 70D, 70E or the office line via the office line interface 11A.
One of A, 239B, and 257A is broadcast circuit 7
Applied to the OR gate 701 contained in 00, the signal @7
11, AND gates 702, 703, 704 are activated by simultaneously applying control signals 871, 872t and 873.
via signals 712, 713, 714 . It is output to the terminal devices 70A, 70B and 70C as follows. In this way, simultaneous broadcasting becomes possible. Here, or gate 7
Signals 239A, 239B and 25 which are input to 01
7A outputs one signal to OR gate 70 by CPU (central control unit) 20, not shown here.
When input to 1, input of other signals is prohibited.

FIG. 2A shows the main side which includes various circuits for realizing the broadcast trunk and various functions related to the present invention explained in FIGS. 18 to 1J. 1 shows a conceptual diagram of the configuration of the device 10, and here, connection relationships within the main control device 10 are omitted.

100A to 100D are extension interface circuits;
The signals 108A, 109A to 108D, 109D can be sent directly to the terminal device 70 or via the transmission line 6 to the transceiver 60.
3 (see FIG. 1A).

150A to 150D are receiving circuits, which receive signals 61A to 61D from the terminal device 70 side.

170 is a D information transmitting/receiving circuit for transmitting and receiving dial information and information for controlling the terminal; Information is exchanged.

Reference numeral 200 denotes an extension call circuit, which performs the function of the extension call explained with reference to FIG. 1H.

Reference numerals 25OA and 250B are office line communication circuits, which perform the office line communication function explained with reference to FIG. 1G.

Reference numeral 350 denotes a conference call circuit, which performs the conference call function described with reference to FIG. 1I.

Reference numeral 700 denotes a broadcast circuit which forms the main part of the broadcast trunk of the present invention, and performs the broadcast function described in FIG. 1J.

Reference numeral 720 denotes a sound source circuit, which receives various signals 66 to 69 applied from outside the main control device 10, and selectively transmits these signals to extension line interface circuits] 00A to 1.
00D to the terminal device 70, and these various signals 66 to 69 include background music (BGM), hold music, doorbell chime sound, etc. .

800 is a CPU interface circuit, which transmits and receives address bus signals 25 .
Data bus signal 35. Reset signal 21. Read signal 22. A write signal @23 and a signal 80B for interrupting the CPU 20 are interfaced.

A timing circuit 1000 generates various timing signals required inside the main control device 10 from a clock 51 applied from the outside and applies them to various circuits inside the main control device 10.

Reference numeral 358 denotes a μ/A switching signal applied from the outside, which is used to select the μ law or A law used for addition processing within the conference call circuit 350.

Signals 14A, 15A (14B, 15B> is the central line 12A
(See Figure 1A), signal 15A is a communication signal between
(15B> is directly input to the office line communication circuit 25OA (250B>), and the transmission signal of the office line communication circuit 250A (250B> or the conference call circuit 350 is input to the OR circuit 13A (250B>).
13B) to the central office line as a signal 14A (14B>).

In the case of an extension call, signals 61A to 61D sent from the terminal device 70 are sent to the receiving circuits 150A to 150D, the extension call circuit 200, and the extension interface circuits 100A to 100A.
Signals 108A, 109A to 108D via 100D,
109D to other terminal devices 70.

In the case of a local line call, the signals 61A to 61D sent from the terminal device 70 are sent to the local line side via the receiving circuits 150A to 150D, the local line communication circuit 25OA, and the OR circuits 13A and 13B. The signals 15A and 15B are
Signals 108A, 109 are sent via the office line communication circuits 25OA, 250B and extension line interface circuits 100A to 100D.
It is sent to the terminal device 70 as A to 108D and 109D.

In the case of a conference call, signals 61A to 61D sent from the terminal device 70 are sent to the receiving circuits 150A to 150D, the conference call circuit 350, and the OR circuit 13A.

13B to the office line side, and further from the conference call circuit 350 to the extension interface circuits 100A to 100D.
Signals 108A, 109A-108D, 109D via
It is sent to other terminal devices 70 as a. Further, the signal 15A from the office line side is transmitted to the signals 108A, 108A, and 108A through the conference call circuit 350 and extension interface circuits 100A to 100D.
It is sent to each terminal device 70 as 109A to 108D and 109D.

In the case of simultaneous broadcasting, the signal sent from the simultaneous broadcasting circuit 700 is sent to the extension interface circuits 10OA to 100D.
via signals 108A, 109A-108D, 109
D, and is sent to each terminal device 70. The signals to be sent from the broadcast circuit 700 are the signals 61A to 61D output from the terminal device 70 to the receiving circuits 150A to 150D.
A case where the signal is applied to the broadcast circuit 700 via the extension line communication circuit 200, and a case where it is applied from the office line side as signals 15A and 15B via the office line communication circuits 25OA and 250B are considered.

When dial information indicating a destination is output from the terminal device 70, the receiving circuits 150A to 150A receive signals 61A to 61D.
150D, and is transmitted to the D information transmitting/receiving circuit (information transmitting/receiving means) 170. This dial information is
D information is read from the transmitter/receiver circuit 170 by the CPU 20 via the data bus signal 35. When the same arrival from the central office line is detected, the central office line interfaces 11A and 11B (first
The CPU 20 reads this station arrival from signals 16A and 16B from Fig. A). The destination is data bus signal 35.
The D information is transmitted to the D information transmitting/receiving circuit 170, and from there the extension interface 1 connected to the destination terminal device 70
The incoming call is notified to one or more of 00A to 100D.

FIG. 2B shows a terminal device 7 connected to the main control device 10.
0 is shown, and FIG. 2B (a) shows an example of the telephone 10
A codec 103 converts the transmission and reception of 5 to a PCM signal, and a codec 103 that converts the transmission and reception of 5 to a PCM signal, and a signal 1
08A and 109A are applied, and a signal 61A is output from the PCM output connected to the pull-up resistor 104.

In FIG. 2B (b) a circuit is shown in which the NOR gate 102 is replaced by a circuit including a transistor 106, the function of which is the same as that shown in (a).

FIG. 3A shows an extension interface circuit, e.g.
A, and FIG. 3B shows a timing chart of the waveforms of each part thereof.

The inputs of the OR gate 101 include a signal 712 from the broadcast circuit 700, a signal 736 from the sound source circuit 720, and a signal 179A (Fig. 3B) which is D information from the D information transmitting/receiving circuit 170 (Fig. 1C). (d)), the signal 693 from the conference call circuit 350, the signals 235A and 235B from the extension call circuit 200, and the office line call circuit 25OA.
, 251A from 250B (Figure 3B (C) > , 25
1B and timing signals 1231.1317 from the timing circuit 1000 (FIG. 3B(a)).

(b)) is applied, and outputs a signal 107 shown in (e) of FIG. 3B. In this FIG. 3B, CPt
Signal 25 from the office line communication circuit 250A under the control of J20
The case of a central office line call receiving 1A at OR gate 101 is shown.

Signal 1231 in FIG. 3B(a) is the start bit ST.
(Fig. 1C), the signal 1317 in (b) represents the F bit (Fig. 1C), and the signal 2 in (C)
51A represents call signals from the office line, and by ORing these signals and the D information in (d), a signal 107 shown in (e) is obtained.

This signal 107 is applied to the code separation circuit 1'IOA. The code separation circuit 110A is applied with the signal 1304 which is the P information in FIG. 3B(f) and the signal 1098 shown in FIG.
A signal 108A representing the output signal 108A and a signal @ 109A representing the even-numbered "1" are separated and output.

Signals 108A and 109A in (h) and (i) are
This shows the contents of the signal 107 in (e) and the signal 1304 in (f). In the signal 107 shown in (e), 1" that first appears after the start of one frame is
Signal 108 of (h) delayed by 1 bit in 98
When the second "1" of the signal 107 of (e) appears, the signal 109A of (i) is similarly set to 1°', and the same goes for (e). For the odd-numbered "'1 pa of signal 107, signal 1 of (h)
08A to “1”, and for even numbered “1”, (i
) signal 109A as 1p, signal 108A of (h)
When the sum of the numbers of “1”s in the signal 109A of (i) and (i) becomes an odd number, “1” of the signal 1304, which is P information (parity information) of As a result, (h) in one frame.

The numbers of "1" appearing in each of the signals 108A and 109A in (i) are equal, and the subsequent transmission line 63A
A good DC balance can be obtained in this case.

FIG. 3C is a detailed circuit diagram of the code separation circuit 110A, and the waveforms of each part thereof are shown in the timing chart of FIG. 3D.

The signal 107 shown in FIG. A signal 133 of the output shown in (e) is applied to one input terminal and is applied to the data terminal of the D flip-flop 111.
A signal 1098 having an equally divided period (a>) is applied.

The signal 139 in (f) indicating the output Q of the D flip-flop 111 is “Ott” in the initial stage, and when “1” in the signal 107 in (b) is applied, the signal 139 in the odd numbered state becomes “1”. , a signal 139 indicating "O"(f>) is outputted at the even number.

Here, the signal 1304 shown in (C) is parity information that is set to "1" when (11ft) indicates an odd number in one frame of the signal 107 indicating the timing of the downlink signal in (b). applied to the other input of NOR gate 117.

Further, the signal 139 (f) is applied to the other terminal of the exclusive OR gate 120.

Signal 1304 (C), which is parity information, is applied to one input terminal of NAND gate 115, signal 139 (f) is applied to the other terminal, and signal 134 (g) is output. This signal 134 (g) indicates 440'' when the signal 1304 (C) which is parity information indicates "1", and indicates "1" at other times.

In response to the signal 131 and the signal 134 (g), the NAND gate 116 outputs the signal 135 (h), which is applied to the data terminal of the D flip-flop 1]2. The clock terminal of this D flip-flop 112 has (a
) signal 109B is applied. The signal 136 of (i) is obtained at the not-Q output. Here, (i)
The signal 136 of (b) is the signal 107 of (c)
304 is added, and the signal 1098 in (a) is delayed by a half cycle valve, and its inverted output is shown.

(D flip-flop 11 inverting the signal 139 of f>
1 output knot Q signal 140 and (i) signal 136
The NOR gate 118 to which is applied outputs a signal 137 shown in (j>. The signal 137 of (j), which is the output of the NOR gate 118,
When there is an odd number of 1's, it indicates 1pa. This (j＞
A signal 137 is applied to the data terminal of the D flip-flop 113. The signal 108A shown in (te) is obtained at the output Q of the D flip-flop 113 to which the signal 1098 of (a>) is applied to the clock terminal via the inverter 122. shows "1" when an odd number of "1"s are added.

The NOR gate 119 to which the signal 139 of (f) and the signal @136 of (i) are applied outputs the signal 138 of (k),
This is applied to the data terminal of the D flip-flop 114. Here, the signal 138 in (k) is obtained by adding "1" of the signal 1304 in (c) to the signal 1Q7 in (b), and indicates "1" when the number of 1pas is even.

The clock terminal of this flip-flop 114 has (a
A signal 1098 of It shows "1" when water is added.

The case where the total number of "1"s of the signal 107 shown in (b) is an odd number is illustrated in FIG. 3D, but if the total number of "1"s is an even number, the parity information (C) signal 1
304 indicates an opening.

FIG. 4A shows a specific circuit of, for example, 150A among the receiving circuits 150A to 150D, and FIG. 4B shows the waveforms of each part as a tie and mink chart. .

The signal 61A shown in FIG. 4B (a) or (b) from the terminal device 70 is received via the inverter 155 to the data terminal of the D flip-flop 151, and its clock terminal is connected to a clock terminal for receiving the upstream signal. A signal 1376 (C) having a period obtained by equally dividing the frame into 32 is applied, and a signal 161 shown in (d>) is obtained at its output Q.

The AND gate 152 indicates "Ott" when the transmission distance from the signal 161 (d) and the receiving circuit 15OA to the terminal device 70 is, for example, up to 200 meters; In this case, a signal 861 indicating "1" is applied.AND gate 153
A signal 861 and a signal 61A are applied through the inverter 155. Both and gate 152.15
3 is applied to OR gate 154 to output signal 16
It is outputting 2A.

FIG. 4B (a) shows the case where the transmission distance is, for example, 0 meters, (b) shows the case when ff1=200 meters, (e) shows the case when e2=150 meters, and (f)
shows the signal 61A when ε3=350 meters.

When the transmission path length is zero meters, as shown in (a>), the beginning of data information 87 to BO is at time t1.
It is applied to the receiving circuit 150A.

When the transmission path length is e1=200 meters, the beginning of data information 87 to BO is applied to the receiving circuit 150A at time t3, as shown in (b). Similarly, Z2=
In the case of 150 meters, (e) t,: As shown, at time t2, in the case of f3 = 350 meters, (f
> indicates that the signal is applied to the receiving circuit 150A at time t5.

In cases (a) and (b), the signal 861 is “Ott
Then, at the signal 1376 in (C), the timing is changed from t4 to t7. , sample the signal 61A and apply the D flip 70 knob 1.
51, and the output signal 161 (d) is sent to AND gate 152 and OR gate 1.
54 as a signal 162A.

In the cases of (e) and (f), the signal 861 is "1", and the signal 1377 of (g), which is not shown in FIG. 4A for convenience of explanation, is at time t6. At t8,
The signal 61A sampled by another circuit is connected to the inverter 15.
5. It is output as a signal 162A via an AND gate 153 and an OR gate 154.

The outputs in cases (e) and (f) are delayed by a half period of the signal 1376 in (C) than in cases (a) and (b). In this way, various transmission lengths can be accommodated.

FIG. 5A shows the circuit configuration of the D information transmitting/receiving circuit 170, and FIG. 5B shows a timing chart showing waveforms of each part thereof.

The D information transmitting/receiving circuit 170 is a circuit for transmitting/receiving dial information and information for controlling the terminal device 70, and FIG. 5A shows four sets of D information transmitting/receiving circuits 170A.
~170D are exemplified, among which, for example, 170A
includes a D information transmitting circuit 171 and a D information receiving circuit 180.

The D information transmitting circuit 171 is applied with a signal 1318 that determines the timing of transmitting the D information in FIG. 5B(a), and
Upon receiving the write signal 822 for capturing the data bus signal 35 from the PU 20, the captured signal (
Timing of signal 131B in a), signal 179 in (b)
A is sent to the extension interface circuit 100A.

The D information receiving circuit 180 is applied with the signal 1379 (d) that determines the timing of receiving the D information in FIG. 5B.
The signal 162A (C) is taken in from the receiving circuit 150A and output to the data bus signal 35 to the CPU 20 at the timing of the signal 817.

FIG. 5C shows a specific circuit diagram of the D information transmitting circuit 171.

172 is a P/S register, and the signal 822 applied to the shift/load terminal S/L takes in the signals 36 to 43 applied in parallel to the input terminals A to H at "Ott", and at "1", Inverter 17 is connected to that clock terminal.
4, the signals 43, 42 . . . 36 as a serial signal, and through the AND gate 173 to which the signal 1318 is applied, the signal 179A (
It is output as FIG. 5B (b>).

FIG. 5D shows a specific circuit diagram of the D information receiving circuit 180.

The signal 162A from the receiving circuit 150A is applied to the A terminal of the 8-bit shift register 181, and each time the signal 1379 for taking in data is applied to the clock terminal, the data of the signal 162A is taken in and sequentially shifted. and outputs them in parallel to outputs QA-QH. These parallel outputs QA-QH are 3-state buffers 18
Parallel input to input terminals A-H of 2, control terminal G
1. When the signal 817, which is the read signal from the CPU 20 applied to G2, indicates "O+t", the input terminal A-
The signals applied to H are output to the CPU 20 as signals 36 to 43 forming the data bus signal 35 to output terminals YA to YH, respectively.

FIG. 6A shows a circuit configuration diagram of the extension call circuit 200, in which signals 16 from the receiving circuits 150A to 150D are shown.
2A to 162D, signals 66 to 69 indicating sound source information,
These signals 162A to 162D and 66 to 69 are selected by bus signal 885, and multiplexer 21OA outputs signal 218A to S/S register 22OA.

The S/S register 22OA receives signal 2, which is a serial signal.
18A, received at the timing of signal 1377,
It is sent as a signal 225A at the timing of the signal 1269, and this sending continues while the signal @ 1268 is "1".

A signal 225A and a bus signal 92 for instructing the destination.
3, the demultiplexer 227A receives the signal 23
5A to 238A, respectively, as extension interface circuit 1.
Broadcasting signal 239A to 00A to 100D from broadcast circuit 70
Send to 0.

The multiplexer 210B, the S/S register 220B, and the demultiplexer 227B are connected to the multiplexer 21, respectively.
OA, S/S register 22OA.

It corresponds to the demultiplexer 227A and operates in the same way.

FIG. 6B shows a specific circuit diagram of the multiplexer 21OA. 211 is an 8-bit multiplexer, 2
12 is a 4-bit multiplexer, and the signal 16 applied to data terminals D1 to D7 of 211 and Do of 212 is
2A-162D, 66-69, selection signals 886-
889 is the select terminal A of the 8-bit multiplexer.
,B.

C, strobe terminal S, and 4-bit multiplexer 2
12 select terminals A, B, and strobe terminal S are applied via an inverter 214, and each selected output signal is obtained at their Y terminals, and is sent via an OR gate 213 as a signal 218A to the S/S. It is output to register 22OA. The selection signals 886 to 889 are all “Oto”.
At this time, the grounded data terminal Do of the 8-bit multiplexer 211 is selected, and a silent signal is output from the Y terminal via the OR gate 213 as the signal 218A. Data terminals D1-D3 of 4-bit multiplexer 212 are never selected.

FIG. 6C shows a specific circuit diagram of the S/S register 22OA, and FIG. 6D shows timing diagrams showing waveforms of each part.
A chart is shown.

Here, FIG. 6D (a) from multiplexer 21OA
The 8-bit shift register 221 to which the signal 218A shown in FIG. 22
3, and when receiving it, the signal 218A is serially input and latched, and is sequentially output at the timing of the signal 1269 in (g), and during the period of "1" of the signal 1268 in (f). , and outputs a signal 225A (h) via an AND gate 222. Here, the 8-bit shift
Each output terminal QA, QB of the register 221 ---Q
To explain H using examples (c), (d), and (el), QA and QB are shifted one bit at a time,
The output QH in (e) shows that data information 87 to O (B is omitted in the drawing) are sequentially output.

The signals 1377.1268.1269 shown in Fig. 6D (b), (f>, (C1>) are shown in Fig. 1E (e).
, (b) and (c), and as is clear from these figures, the frame in FIG. 6D is displayed with a delay of half a frame.

A circuit diagram of demultiplexer 227A is shown in FIG. 6E. Select signals 936 to 93B to select terminal A
-C, the 3-power 8-output decoder 228 receives the signal 225 at the enable terminal G△, and its output terminal YO-Y
7, signals 235A to 239A are obtained from Y1 to Y5 via inverters 229 to 233. Here, when all of the selection signals 936 to 938 indicate "Oee", no output is made in order to select the output terminal YO.

FIG. 6F is a circuit configuration diagram showing another embodiment of the extension call circuit 200, and the difference from that shown in FIG. 6A is that transmission control circuits 24OA and 240B are added, and other The same is true for

Rather than applying the signal 225A from the S/S register 22OA directly to the demultiplexer 227, the signal 225A is applied by the control signal 964 in the transmission control circuit 24OA.
It is either allowed to pass through or prohibited from passing through. By doing this, by separating the selection of the destination by the demultiplexer 227AI and the sending of the signal, the CP
There is an advantage that the hierarchical structure design of the software in U20 becomes easy.

A specific circuit of this output control circuit 24OA is shown in FIG. 6G, in which a control signal 964 is applied via the inverter 242 and a signal 225A is directly applied to the AND gate 241, so that the signal 964 becomes "0". Signal 2 which is output when
I am getting 48A. The operation of the sending control circuit 240B is also 24
The operation is similar to that of OA.

FIG. 7A shows the circuit configuration of two sets of office line communication circuits 25OA and 250B, and shows a case where an incoming call from the office line is transferred again to another office line.

Signal 15A from the central office line side is received by S/S register 260A and outputs signal 268A, which is applied to demultiplexer 27OA, which outputs signal 256A.
The signal 288B is applied to the multiplexer 280B of the central office line communication circuit 250B, and the signal 288B is outputted through it.
Signal 268D is output to the central office line via register 260D.

Similarly, the signal 15B from the other office line side is received by the S/S register 260C, outputting the signal 268C, which is applied to the demultiplexer 270B, and the signal 256B
is output and applied to multiplexer 28OA of office line communication circuit 25OA, through which signal 288A is output, and signal 268B is output to the office line side via S/S register 260B.

Here, the signal 1377 is the S/S register 260A to 2
This is a reception timing signal applied to 60D, and the signal 1269 is also a transmission timing signal, and the signal 1268 is also "1".

This is a timing signal indicating the transmission period. The bus signal 926 (925) is a bus signal for instructing the destination, and is a bus signal 251A to 254A (251B to 254).
B> sends data information (87 to BO) to the extension interface circuits 100A to 100D to each destination.

The signal 257A (257B>) sends data information (audio information) to the broadcast circuit 700.

Signal 255A (255B> is multiplexer 28OA
(280B>) 162A to 162D are signals from the receiving circuits 150A to 150D, and the signal 66
~69 indicates sound source information, and these signals 16
Bus signal 880 for selecting 2A-D, 66-69
(875), signal 288A (288
B> is output to the S/S register 260B (260D).

FIG. 7B shows a specific circuit diagram of the multiplexer 28OA. 281 is an 8-bit multiplexer,
282 is a 4-bit multiplexer, and signals 162A to 162D, 66 to 69.255A, 25 applied to data terminals D1 to D7 of 281 and DO to D3 of 282
6B, selection signals 881 to 884, select terminals A, B, and C of the 8-bit multiplexer, strobe terminal S, and select terminal A of the 4-bit multiplexer.
B and strobe terminal S through the inverter 284 to obtain each selected output signal to their Y@ terminal,
S/S as signal 288A via OR gate 283
It is output to register 260B. Selection signal 881
~884 are all “O”, the grounded data terminal Do of the 8-bit multiplexer is selected, and Y
A silent signal is output from the terminal via the OR gate 283@ as a signal 288A. Data terminal D3 of 4-bit multiplexer 282 is never selected.

FIG. 7C shows a circuit diagram of demultiplexer 27OA. Selection signal 931 included in bus signal 926
~933 to select terminal A-C, enable terminal GA
The decoder 271, which has three outputs and has 8 outputs and receives the signal 268, outputs signals 251A to 257 from Y1 to Y7 of the output terminals Y○ to Y7 via inverters 272 to 278.
I got an A. Here, when all of the selection signals 931 to 933 indicate Oto, no output is made in order to select the output terminal YO.

FIG. 7D shows another embodiment of the office line communication circuit 25OA or 250B, and the difference from the office line communication circuit 25OA shown in FIG. 7A is that a transmission switching circuit 290 is added. , a multiplexer 310 that is different from multiplexer 280 is used, so this difference will be explained.

This circuit is suitable for transfer over the central office line explained in FIG. 7A. The S/S register 26OA (260B) receives its input signal, the signal 15A (328), as shown in (d) in Figure 1E.
), it is captured in the second half of one frame, and in the first half of the next frame, it is sent out as shown in (a> in Figure 1E).However, in transfer over the central office line, the signal 255
A is immediately applied to the multiplexer 310, and its output signal 328 is applied to the S/S register 260B, but at this time, the signals 1268 and 1269 in FIG. is being applied, the signal 328 cannot be taken into the S/S register 260B, so the signal 328 is passed through the output switching circuit 290 by bypassing the S/S register, and is sent as the signal 29B through the OR circuits 13A and 13B. and sent to the central office line.

Bypass the S/S register 260B and send the signal @328,
Whether or not to output the signal 298 from the transmission switching circuit 290 is determined by the signal 329 from the multiplexer 310.

FIG. 7E shows a specific circuit diagram of multiplexer 310. 311 is an 8-bit multiplexer, 3
12 is a 4-bit multiplexer, and signals 162A to 162D, 66 to 69, 255A, 256 are applied to data terminals D1 to D7 of 311 and Do to D2 of 312.
B, selection signals 881 to 884 are connected to the select terminals A, B, C, and strobe terminal S of the 8-bit multiplexer, and inverters are connected to the select terminals A, B, and strobe terminal S of the 4-bit multiplexer 312. 317, each selected output signal is applied to their Y terminals, and outputted as a signal 328 via the OR gate 315 to the S/S register 260B and the output switching circuit 290.

When the selection signals 881 to 884 are all 44 ON, the grounded data terminal Do of the 8-bit multiplexer 311 is selected, and the data terminal is connected from the Y terminal to the OR gate 3.
A silent signal is outputted as a signal 32B via the signal line 15. Data terminal D3 of 4-bit multiplexer 312 is never selected. Selection signals 881 to 884
is applied to AND gates 313 and 314 via inverters 318 to 321 or directly, and their outputs are ORed by OR gate 316 to output signal 329. Here, when the selection signals 881 to 884 select the signal 255A or 256B, both the signals 329 are set to "1".

At other times, “Ot?”

FIG. 7F(a) shows a specific circuit of the transmission switching circuit 290 of FIG. 7D.

A signal 268B which is the output of the S/S register 260B,
A control signal 329 is applied to AND gate 291 via inverter 294, and its output is applied to OR gate 2
93 is applied. AND gate 29 applied with signal 328 and signal 329 from multiplexer 310
The output of 2 is applied to an OR circuit 293, and a signal 298 is output. The relationship between this signal 329 and signal 298 is
As shown in FIG. 7F (b), the signal 329
When signal 329 is "1", signal 328 is output as signal 298, and when signal 329 is "OQ", signal 268B is output as signal@298.

FIG. 7G is a circuit configuration diagram showing another embodiment of the office line communication circuit 25OA of FIG. 7D, and the difference from that shown in FIG. 7D is a transmission control circuit 24OA.

240B is added, and the rest is the same.

Rather than applying the signal 268A from the S/S register 26OA directly to the demultiplexer 27OA, the signal 248A is applied by the control signal 960 in the transmission control circuit 24OA.
It is either allowed to pass through A or prohibited from passing through. By doing so, there is an advantage that the hierarchical structure design of the software in the CPU 20 is facilitated by separating the selection of the destination in the demultiplexer 27OA and the sending of the signal.

The specific circuit configuration of this output control circuit 24OA (240B>) is the same as that already shown in FIG. 6G.

FIG. 8A shows the circuit configuration of the conference call circuit 350. 360 is a multiplex circuit, which converts serially input signals 15A and 15B from the office line side and signals 162A to 162D applied from the terminal device 70 via receiving circuits 150A to 150D to bus signals 920,
Select according to the instructions of 921.922, multiplex,
It is converted into parallel data at the timing of signal 1377, and outputted in parallel as bus signal 420 at the timing of bus signal 1430.

430 is an adder which receives a bus signal 927 for setting the amount of attenuation for each of the plurality of signals of the bus signal 420 from the multiplex circuit 360, a bus signal 1430 which is a timing signal for setting the attenuation, and an initial value. Upon receiving the signal 1480 which is a clear signal for setting to zero and the signal 1482 for latching the addition data, it outputs a signal 545 representing the polarity of the signal and a bus signal 652 for outputting the addition result in parallel. are doing.

660 is a demultiplexing circuit, which latches the input signal 545 and the bus signal 652 which is a parallel signal at the timing of the bus signal 1475 and according to the instruction of the bus signal 1470, and in the period indicated by the signal 1268, the bus signal 9 is latched.
The signals 20, 921, and 922 are sent to the destinations indicated by the signals 691 to 696 connected to the respective destinations at the timing of the signal 1269.

FIG. 8B shows a more specific circuit configuration of the multiplex circuit 360.

361A to 361C are multiplexers which receive signals 15A and 15B from the office line side and a signal 162A applied from the terminal device 70 via receiving circuits 150A to 150D.
- 162D, respectively, and output signals 362A-362C multiplexed by bus signals 920-922 instructing each destination.

(gM3) of each output of multiplexers 361A to 361C
62A to 362C are S/P registers 364, each of which is a register for converting serial input into parallel output.
It is applied to A to 364C, taken in at the timing of signal 1377, and parallel bus signals 365A to 365C.
and applied to multiplexer 380.

At multiplexer 380, applied bus signal 365
A to 365C are time-divided at the timing of signal 1430 and output as bus signal 420.

FIG. 8C shows multiplexer 361A (361B).

361C is the same), and the multiplexer 361A is connected to the receiving circuit 1
Signals 162A-1 applied via 50A-150D
62D, signals 15A and '15B from the office line side, and signals 939 to 941 forming the bus signal 920 for selecting each destination are connected to data terminals D1 to D6 and select terminals A to C. A multiplexed serial signal 362A is output to the output terminal Y.

FIG. 8D shows S/P registers 364A (364B, 36
4C) is shown, in which a signal 362A from a multiplexer 361A is received at input terminal A,
Receive the signal 1377 for reception timing at the clock terminal, take in the signal 362A, and output the signal 3 in parallel.
66A to 373A (bus signal 365A> to output terminal QA
~QHk: Obtained.

FIG. 8E shows a specific circuit diagram of the multiplexer 380, which includes a set of AND gates 381 to 388 and an OR gate 406, a set of AND gates 389 to 396 and an OR gate 407, and an AND gate. 397-404
and an or gate 408, each set having the same configuration.

Therefore, to explain the first set, the signals 366A to 373A making up the bus signal 365A are
Signals 1431 and 1436 in the bus signal 1430, which are applied to one terminal of each of the AND gates 381 to 388 and indicate the timing for time-division transmission, are applied to the other terminal of each of the AND gates 381 to 388 via the OR gate 406. The signals 421 to 428 (bus signal 4
20) is output. AND gates 389-396 and 397-404 each input signal 42 at different times.
1 to 428, time-division multiplexed signals 421 to 428 are obtained. Here resistance 41
Reference numerals 1 to 418 indicate open drain pull-up resistors used to wire-OR these three sets of AND gates.

FIG. 9A shows a more specific circuit configuration of adder 430.

440 is a nonlinear/linear converter which receives the bus signal 420, which is a nonlinear signal from the multiplex circuit 360, and determines whether this nonlinear signal is based on the μ law or not.
μ/A switching signal 3 indicating whether it is based on the law
58 is applied thereto, which is converted into a linear signal and output as a linear bus signal 445.

460 is an attenuation instruction circuit which outputs a signal 469 at the timing of the bus signal 1430 for distinguishing the amount of attenuation instructed by the bus signal 927 between callers.

470 is an attenuation circuit that attenuates the linear bus signal 445 according to the instruction of the signal 469, and outputs the bus signal 475 that has undergone the specified attenuation to the caller side.

This bus signal 475 is applied to a full adder 500, and a signal 4 in the bus signal indicating the polarity of data in the bus signal 420 is applied to the full adder 500.
28, a signal 1480 that is a clear signal for setting the initial value to zero, and a signal 148 for latching the addition data.
2, the full adder 500 outputs a bus signal 585 indicating the addition result and a signal 545 indicating its polarity.

650 is a linear/nonlinear converter, which outputs the applied bus signal 585 as a bus signal 652, which is a linear signal according to the μ law, and which is a nonlinear signal, according to the μ/A switching signal 358. are doing.

FIG. 9B shows a circuit diagram of nonlinear/linear converter 440.

441 and 442 are read-only memories (ROM).
), signals 421 to 427 of the signals constituting the bus signal 420 are applied to the respective input terminals AO to 80, and the μ/A switching signal 358 is applied to the input terminal A7 to write. Store the linear data in the ROM442
The signals 446 to 453 are output from the output terminals DO to D7 of the RO
Signals 454 to 458 from output terminal Do-D4 of M441
are output respectively. These signals 446-45
8 constitutes a bus signal 445.

FIG. 9C shows a circuit diagram of the attenuation instruction circuit 460, in which three OR gates 461-463 have signals 1434, 1435, 1431, .
1436, 1432, and 1433 are applied to the three AND gates 464 to 466, and signals 942 to 944 constituting a bus signal 927 indicating the amount of attenuation, respectively.
The outputs of OR gates 461-463 are applied, and the outputs of each AND gate 464-466 are applied to OR gate 467.
is applied to output a signal 469.

FIG. 9D shows attenuation circuit 470, which is comprised of 2-bit multiplexers 471-474.

Linear signals 446-449, 450-453 and 454
~457 is a 2-bit multiplexer 47
1,472.473 respective input terminals A4. A3.
A2. The linear signal 458 applied to A1 is a 2-bit signal.
Applied to the input terminal A4 of the multiplexer 474, the rough signals 447°448.449,450 and 451,4
52,453.454 and 455,456,457.45
8 is a 2-bit multiplexer 471°4
72.473 input terminal 84. B3. B2. A signal 469 for selecting input terminal A or B is applied to each select terminal S, and a signal 469 for selecting input terminal A or B is applied to each select terminal S.
Output terminal Y4 of bit multiplexers 471 to 473
Signals 476 to 487 are output from ~Y1, and signal 488 is output from Y4 of 474, and these signals 476 to 488 constitute a bus signal 475.

FIG. 9E shows a more specific circuit configuration of full adder 500. The first adder 510 receives a linearized and attenuated bus signal 475, a signal 428 indicating whether the polarity of the bus signal 475 is positive or negative, and a bus signal 620 indicating the previous addition result. is applied, and when the addition result is negative, the bus signal 530 is expressed as a two's complement number, and the bus signal 530 is
A signal 545 indicating the polarity of the data of the bus signal 530 is output.

550 is a second adder, in which when the bus signal 530 is expressed as a two's complement number, by applying a signal 545 indicating the polarity of the signal @530, it further takes the two's complement number and outputs the bus signal. 585 is output.

610 is a temporary storage circuit which, after being cleared with a signal 1480, latches the bus signal 530, which is the output of the first adder 510, with a signal 1482, and outputs a bus signal @620. When the data on the bus signal 475 indicates a negative value, the signal 545 indicates a negative value. In this case, the bus signal 530 is expressed as a two's complement number, and its stored output, the bus signal 620, indicates a negative value. , is conveniently added to the bus signal 475 in the first adder 510.

FIG. 9F shows a circuit diagram of the first adder 510, which is composed of adders 511-514 and exclusive-OR gates 516-528.

Signals 476 to 488 forming the bus signal 475 from the attenuation circuit 470 are sent to the exclusive OR gate 5.
A signal 428 indicating the polarity of signals 476 to 488 is applied to one terminal (73 terminal) of 16 to 528, and a signal 428 indicating the polarity of signals 476 to 488 is applied to the other terminal. A signal 428 applied to terminals A1-A4 and A1 of 514 and further indicating polarity.
is applied to the input terminal CO of the adder 511 and the input terminals A2 and 3 of the adder 514, and the signal 621 constituting the bus signal 620 from the - hour storage circuit 610
~635 are input terminals 81~B of adders 511~513
81 to B3 of adders 512 to 514, and input terminals CO of adders 512 to 514 respectively.
A carry signal from terminal C4 that outputs a carry signal of 513 is applied, and signals 476 to 488 and signals 621 to 63
The addition result with 5 is the output terminal 8 of adders 511 to 513.
1 to S4 and 81 to S3 of 514, signals 531 to 5
It is output as 45.

FIG. 9G shows a circuit diagram of the temporary storage circuit 610,
It is composed of latches 611 to 614 and an inverter 616.

Input terminals D1 to D4 of the latches 611 to 613 and D1 to D3 of the latches 614 are supplied with signals 531 to 531 of the output of the first adder 510.
A clear signal 1480 is applied to each clear terminal CL of the latches 11 to 614 via an inverter 616, a latch signal 1482 is applied to each clock terminal, and a signal 531 is applied to each clock terminal. ~54
5 is latched and signals 621 to 635 are output.

FIG. 9H shows a circuit diagram of the second adder 550,
It consists of adders 551-554, exclusive or gates 556-569, and or gates 571-583.

Bus signal 5-3 which is the addition result from the first adder 510
Signals 531 to 544 constituting 0 are applied to one input terminal of exclusive OR gates 556 to 569, respectively, and are applied to the other input terminal and adder 551.
A signal 545 indicating the polarity is applied to the input terminal CO of the adders 552 to 554, and a signal indicating a carry from the output terminal C4 of the adders 551 to 553 is applied to the input terminals CO of the adders 552 to 554, respectively. Input terminal 81~B
4 and 81 and 82 of 554 are grounded to input zero. Output terminals 81 to S4 of adders 551 to 553
and 81 of 554 are or gates 571 to 5, respectively.
83, and a signal representing an overflow from the output terminal S2 of the adder 554 is applied to the other terminal, so that each of the OR gates 571-583
, respectively, output signals @586 to 598.

These signals 586-598 constitute bus signal 585.

A circuit diagram of a linear/nonlinear converter 650, which is a read-only memory, is shown in FIG.
Signals 586 to 598 forming bus signal 585, which is a linear signal output from
and the nonlinearized signals 653 to 65 are output to the output terminal Do according to the μ law or the A law instructed by the μ/A switching signal 358 applied to the input terminal A13.
~ I got it on D6. These signals 653 to 659 constitute a bus signal 652.

1st. The OA diagram shows the demultiplexer circuit 660 (8th A
The diagram shows a more specific circuit configuration of P/S registers 661A to 661C and a demultiplexer 670.
It is composed of A to 670G and OR gates 685 to 690.

In the P/S register 661A (661B, 661C) for serially outputting parallel signals, the adder 43
A bus signal 652 indicating the result of addition from 0 and a signal 545 indicating the polarity of data are used as a latch clock signal 14.
71 (1472, 1473) and latch timing signal 1476 (1477, 1478>),
During the period indicated by the signals 126 and 8, the serial signal 668A (6688, 6
68C> is output.

Demultiplexer 670A (670B, 670C) receiving signal 668A (668B, 668C) sends signals 679A to 684A (679
B~684B, 679C~684C> are respectively output, and the outputs of each demultiplexer 670A~670C are ORed by OR gates 685~690, respectively.
The signals are output as signals 691-696. Of these signals, 691 and 692 are output to the office line side as signals 14A and 14B via OR circuits 13A and 13B, respectively (see FIG. 2A). Moreover, the signals 693 to 696 are
Via the extension interface circuits 100A to 100D,
Each is sent to the terminal device 70.

FIG. 10B shows the P/S register 661A (661B,
661C is the same).

Adder 4 is connected to input terminals A to G of shift register 662.
Signals 653~ constituting the bus signal 652 from 30
659 are respectively applied, a signal 545 representing the polarity is applied to the input terminal H, and the shift/load terminal S/
A latch timing signal 1476 is applied to L via an inverter 665, and a latch timing signal 1476 is applied to the clock terminal via an OR gate 663.
71 and a signal 1269 for sending timing are applied,
During the period when the signal 1476 is “Htt”, the signal 1471 is
Signals 653 to 659 and 545 are captured every time the signal 1269 rises, and are outputted as a signal 668A from the output terminal SO at the timing of the signal 1269 through the AND gate 664 during the period of the signal 1268.

FIG. 10C shows demultiplexer 670A (6708,
670C also shows the same). In the decoder 671, signals 939 to 941 constituting the bus signal 920 instructing the destination are sent to select terminals A to C, respectively, and
A signal 668A from the S register is applied to the enable terminal GA, and output as signals 679A to 684A from output terminals Y1 to Y6 via inverters 672 to 677, respectively.

10D and 10E are timing charts representing the main operations of conference call circuit 350. FIG.

Figures 10D (a>, (b), and (C) show signals 362A, 362B, and 362C, which are the outputs of multiplexers 361A, 361B, and 361C (Figure 8B), respectively, and the signal 1377 shown in (d). is S/P register 36
4A, 3648.364C, respectively signal 362A,
362B, 362C, (e
).

(f>, (q)) respectively show signals 365A, 365B, and 365C that are captured and output in this way.

In (h> of FIG. 10D, P/S registers 661A to 6
Signal 1 representing the period of transmission from 61C (Figure 10A)
268 is shown, and (i) shows the signal 1 for sending timing.
269 is shown (j).

(k) and (ri) each have a P/S register 661A.
The signal 668A, which is the output of ~661C, 6688.66
8G is shown.

In Figure 10D, each signal (a) to (g) and (h)
A guard time T2 described in FIG. 1E and an addition time T3 for two hits are provided between each signal of (e) to prevent the two signals from overlapping during this period. It also allows conference calls to be held if necessary. During the 2-bit period of addition time T3 following this guard time T2, the first
The addition work shown in the timing chart in Figure 0E is being performed.

Here, in FIGS. 1E, 10D, and 10E, addition time T3 is provided immediately after guard time T2 for convenience of explanation;
2, or it may be provided so as to end immediately before B7, which is the first bit of the data information.

FIGS. 10E (a) to (C) show the multiplexer 38
Signals 1431 to 1436 forming the bus signal 1430 (FIG. 8B) applied to the bus signal 1430 are shown in FIG.
The contents of 0 are "A" corresponding to S/P registers 364A, B, and C.

The bus signal 475 shown in (e) is a signal obtained by converting the nonlinear bus signal shown in (d>) into a linear signal and passing it through the attenuation circuit 470. (
The signal 1480 shown in q) causes the temporary storage circuit 61Q (9th E
10E, the linear signal 445 of (e) is latched and temporarily stored in the temporary storage circuit 610, and (Cl
) is output as shown in bus signal 620.

(h) shows a bus signal 58 which is the output of the second adder 550.
5 is shown, and this bus signal 585 shows the addition result of the bus signal 475 of (e) and the bus signal 620 of (CI>).

(i) shows a bus signal 652 obtained by converting the linear bus signal 585 in (h) into a nonlinear one.

From the bus signal 652 shown in (i), (m>, (
n>, signals 1476 to 1478 shown in (p), respectively.
Signal 1 shown in (j), (k), and (e) at the timing of
Data is taken into the S/P registers 661A to 661G (FIG. 10A) at the rising edge of 471 to 1473.

FIG. 11 shows a circuit diagram of a broadcast circuit 700 that constitutes the main part of the broadcast trunk according to the present invention.
Signals 257A from office line communication circuits 25OA and 250B,
257B (FIG. 7A), the signals 239A and 239B (FIG. 6A) from the extension communication circuit 200 are sent to the OR gate 70.
A signal 711 is obtained by ORing with 1, and this signal 711 is applied to one input terminal of AND gates 702 to 705, which are sending means to the destination.

Signals 871 to 874 indicating the destination are applied to the other input terminals of each of the AND gates 702 to 705, and signals 712 to 715 are obtained as outputs from each of the AND gates 702 to 705. Signal 712-7
15 are extension interface circuits 100A to 1, respectively.
It is sent to each terminal device 70 via 00B.

FIG. 12A shows a specific circuit configuration of the sound source circuit 720, in which multiplexer 721 receives signals 66 to 69 from various sound sources and sends signals 916 to 99 to select a destination.
A signal 722 selected by 18 is obtained and applied to a serial input/serial output S/S register 725. Therefore, the signal 728 is taken in at the signal 1377 and sent out at the timing of the signal 1269 during the period of the signal 1268.

This signal 728 is applied to one input terminal of AND gates 731 to 734, and signals 866 to 869 indicating the destination are applied to the other input terminals of each of AND gates 731 to 734. The output of
Signals 736 to 739 are obtained, and these signals 73
6 to 739 are extension interface circuits 100, respectively.
It is sent to each terminal device 70 via A to 100D. −
FIG. 12B shows a circuit diagram of an 8-bit multiplexer 721, to which input terminals D1 to D4 are applied signals 66 to 69 from various sound sources, respectively, and select terminals A, B, and C. Signals @916 to 918 are applied to select the destination, respectively, and the signal 7 is applied to the output terminal Y.
I got 22.

The circuit of the S/S register 725 shown in FIG.
In the circuit shown in Figure C, signal 218A is connected to signal 722.
This is the same as signal 225A replaced by signal 728.

FIG. 13A shows the internal configuration of CPU interface circuit 800.

801 is an interrupt circuit which receives an interrupt timing signal 1316, a reset signal 21 for initialization when power is turned on, and a signal @848 applied for resetting when work is completed, and interrupts the interrupt period. A signal 808 indicating medium "1" is output.

Reference numeral 810 denotes an address decoding circuit, which receives a reset signal 21 for initialization when the power is turned on and an address bus signal 25, and outputs a bus signal 816 indicating timing and address for reading according to the read signal 22. , and bus signals 821 and 82 indicating the write timing and address by the write signal 23.
A signal 848 for outputting 6,834.844 and resetting the interrupt circuit 801 when a series of operations is completed.
Output.

850 is a 4-bit latch circuit, which is reset by the reset signal 21 for initialization when the power is turned on, and outputs a bus signal 826 indicating write timing and address.
and bus signals 860, 865, and 870 that are applied with signals 36 to 39 included in data bus signal 35 and send three data signals 36 to 39 to the designated address at the timing of bus signal 826. ,875,880,8
It is outputting 85.890.

900 is a 3-bit latch circuit, which is reset by the reset signal 21 for initialization when the power is turned on, and outputs a bus signal 834 indicating write timing and address.
and bus signals 915, 920 to 927 which are applied with signals 36 to 38 included in data bus signal 35 and send data of signals 36 to 38 to the designated address at the timing of bus signal 834. is outputting.

950 is a 2-bit latch circuit, which is reset by the reset signal 21 for initialization when the power is turned on, and outputs a bus signal 844 indicating write timing and address.
, signals 36.37 included in the data bus signal 35 are applied, and at the timing of the bus signal 844, signals 960 to 965 are outputted to send the data of the signal 36.37 to the specified address. ing.

FIG. 13B shows a circuit diagram of the interrupt circuit 801, and FIG. 13C shows a timing chart showing waveforms of each part thereof.

In FIG. 138, 802 is a D flip-flop, and "1" is always applied to its data terminal, and the first
The reset signal 21 at power-on in Figure 3C (b) and (d)
) is received by the clear terminal CL through the inverter 804 and the NOR gate 803, and an interrupt is generated every time the interrupt timing signal 1316 shown in (a) is applied. The CPU sends the signal 808 (C) which indicates “1” that it is in the period.
20 (Figure 1A).

FIG. 13D shows a circuit diagram of the address decoding circuit 810, and FIG. 13E shows a timing diagram showing the waveforms of each part.
Showing a chart.

A decoder 811 sends signals 29 to 33 of the upper five bits included in the address bus 25 to a terminal A.

B, C, G2A, G2B to select the decoder, the signals are applied to terminals YO, Y1 . It is output to Y2.

812 is a decoder which sends the read signal 22 to terminal G1.
, the signal from the terminal YO of the decoder 811 is transferred to the terminal G2A.
The reset signal 21 for initialization when the power is turned on is connected to terminal G.
2B, signals 26 to 28 of the lower three bits of the address bus signal 25 are received at terminals A to C, and the signal 8 included in the bus signal 816 indicating the timing and address for reading is received at the terminals A to C.
17 to 820 are obtained at terminals YO-Y3.

813 is a decoder, which sends the write signal 23 to terminal G1.
, the signal from the terminal YO of the decoder 811 is transferred to the terminal G2A.
The reset signal 21 for initialization when the power is turned on is connected to terminal G.
2B, the signal of the lower 3 bits of address bus signal 25 @
26 to 28 are received at the terminals A to C, and the signal 8 included in the bus signal 821 indicating the write timing and address.
22 to 825 and some signals 8 included in the bus signal 826
27 to 830 are obtained at terminals YO-Y7.

814 is a decoder, which sends the write signal @23 to terminal G1.
, the signal from terminal Y1 of decoder 811 is transferred to terminal G2A.
The reset signal 21 for initialization when the power is turned on is connected to terminal 0.
2B receives signals 26 to 28 of the lower 3 bits of the address bus signal 25 at terminals A to C, and connects some signals 831 to 833 included in the bus signal 826 indicating the write timing and address to the bus signal 2B. Some signals 835 to 839 included in signal 834 are obtained at terminals YO-Y7.

815 is a decoder, which sends the write signal 23 to terminal G1.
, the signal from terminal Y2 of decoder 811 is transferred to terminal G2A.
The reset signal 21 for initialization when the power is turned on is connected to terminal G.
2B receives signals 26 to 28 of the lower 3 bits of the address bus signal 25 at terminals A to C, and connects some signals 840 to 843 included in the bus signal 834 indicating the write timing and address to the bus signal 2B. Some signals 845 to 847 and a signal 848 included in signal 844 are obtained at terminals YO to Y7.

In the circuit shown in FIG. 13D, an address bus signal 25 including signals 26 to 33 is applied as shown in FIG. 13E (a), and a write signal @23 is applied at the timing shown in FIG. 13E (b). At the timing of the write signal 23 in (b), at the address bus signal 25 in (a>), (d
) is output. When the readout signal 22 shown in (C) is applied, at that timing (
The bus signal 816 shown in (e) instructed by the address bus signal 25 in (a) is output.

FIG. 14A shows a circuit diagram of the 4-bit latch circuit 850, and FIG. 148 shows a timing chart showing waveforms at various parts thereof.

851 to 857 are D flip-flops, and the reset signal 21 is inverted to their clear terminal CL via an inverter 858, and the signal 859 in FIG. 148(b) is output.
is applied to those data terminals D1 to D4,
Some signals 36 to 39 of the data bus signal 25 shown in FIG. 148(a) are applied, and signals 827 to 83 indicating write timing and address are applied to each clock terminal.
3 is applied as partially shown in (C) to (e), and the signals 36 to 36 in (a) are applied at the timing of each signal 827 to 833.
Bus signal 860 (Figure 14B (
f>), 865 (q), 870 (h), 875,8
It outputs 80,885,890.

FIG. 14C shows a circuit diagram of the 3-bit latch circuit 900, and FIG. 14D shows a timing chart showing waveforms at various parts thereof.

901 to 909 are D flip-flops, and the reset signal 21 is inverted to their clear terminal CL via an inverter 910, and the signal 914 in FIG. 14D(b) is output.
is applied to those data terminals D1 to D3,
Some signals 36 to 38 of the data bus signal 25 shown in FIG. 14D (a) are applied, and signals 835 to 84 indicating write timing and address are applied to each clock terminal.
3 is applied as partially shown in (C) to (e), and at the timing of each signal 835 to 843, the signals 36 to 36 of (a>
Bus signal 915 (Figure 14D (
f >>, 920 (g), 921 (h), 922-9
27 is output.

FIG. 14E shows a circuit diagram of the 2-bit latch circuit 950, and FIG. 14F shows a timing chart showing waveforms at various parts thereof.

951 to 956 are D flip-flops, and the reset signal 21 is inverted to their clear terminal CL via an inverter 957, and the signal 958 in FIG. 14F(b) is output.
and the 14th F is applied to those data terminals.
Some signals 36 of the data bus signal 25 shown in FIG.
．． 37 is applied, and signals 845 to 847 indicating write timing and address are applied to each clock terminal (C
) to (e), and each signal 845 to 84
Signals 960 and 961 (FIG. 14F (f)), 96 which send data of signal 36 and 37 of (a) at timing 7
2 and 963 (C1), 964 and 965 (h) are output.

FIG. 15A shows the internal configuration of the timing circuit 1000, and FIGS. 15B and 15C show timing charts showing waveforms of each part thereof.

The 1090 receives the reset signal 21 when the power is turned on, and, for example, divides the clock 51 with a frequency of 2.048 MH2 by 2 to generate the signal @1096, and divides the frequency by 4 to generate the signal 1097 by 8.
The frequency is divided and a signal 1098 having a frequency of 256 KHz is output.

1100 is a frame pulse circuit, which is reset in response to the reset signal 21, and is reset in response to the signal 1098;
A signal 1128 output for each frame and a bus signal 1120 shown in FIG. 15B (a) indicating the frame number are output.

1150 is a multi-frame pulse circuit, which is reset by the reset signal 21 and receives the signal 1128 output for each frame, and performs the multi-frame pulse circuit in FIGS. 15C (b) and (C
) signals 1177 and 1176 are output. here(
Signal 1177 in b) indicates the frame period during which D information can be sent. That is, frame numbers O to 7
This shows the period during which the data will be sent.

A signal 1176 in FIG. 15C (C) indicates the period of frame number 8, which is a frame that transmits the F bit (see FIG. 1C), which is information for obtaining the frame period.

1200 is a first to fourth transmission timing circuit;
For example, 25
Signal 1098 with a frequency of 6KH2 and FIG. 15C(b)
, signals 1177 and 1176 shown in (C) and the 15th B
The bus signal 1120 shown in FIG.
A signal 1231 indicating the timing for transmitting the start bit in FIG. 15B (d), a signal 1268 indicating the timing for transmitting data information B (7) in FIG. A signal 1304 indicating the timing of transmitting information and a signal 108A shown in FIG.

109A (see Figures 1A to 1E) - a signal 1269 indicating the timing of each bit during the period;
It outputs a signal 1316 for interrupt timing for U20, a signal 1317 indicating the timing of sending out the F bit, and a signal 1318 indicating the sending period of data information B.

1350 is a reception timing circuit, which receives reset signal 2
1, the signal 1098, the clock 51, the signal 1177 (FIG. 15C (b)), and the signal 1120 indicating the frame number (FIG. 15B (a)) are received, and the signal shown in FIG. Up signal 61A (1st B) shown in
For example, the signal 1376 shown in FIG. 158(q) having a frequency of 256KH2 (see FIGS.
(see Figure (C)) and the signal 13 shown in (h) of Figure 15B.
77 (Fig. 1D, Fig. 1E, Fig. 1F.

(see Figure 4B) and the signal 13 shown in (i) of Figure 15B.
79 (see Figure 5B).

1400 indicates the first and second conference timing circuits, and signals 1096 to 1098 from the frequency divider circuit 1090
and the clock 51, the conference signals 1431~
A bus signal 1430 consisting of 1436 (see Figure 10E)
, a bus signal 1470 consisting of latching signals 1471 to 1473 (see FIG. 10E), a bus signal 1475 consisting of signals 1476 to 1478 (see FIG. 10E) indicating a latch period, and a - time storage circuit 610 is reset. a signal 1480 for latching (see FIG. 10E) and a latch signal 1482 (10th
See figure E).

Here, bus signals 1430.1470.1475 and signals 1480.1482 are output during the conference call addition time T3 (between O and 1 bit in one frame) shown in FIG. 15B (b). .

Similarly, in the transmission timing period (between 0 and 12 bits in one frame) shown in FIG. 158(C),
Signals 1231, 1268, 1269.1304, 131
6 to 1318 are sent out.

Similarly, the reception timing period (1
Between bits 21 and 29 of the frame), signals 1376.1377.1379 are sent out.

FIG. 15D is a timing chart showing the circuit of the frequency dividing circuit 1090, and FIG. 15E is a timing chart showing the waveforms of each part thereof.

1090 is a frequency divider circuit, which is cleared by receiving the reset signal 21 at power-on via the inverter 1091 to the clear terminal CL, and receives the clock 51 shown in FIG. 15E (a) to the clock terminal; After dividing the frequency, the signal 1096 of (b) is sent to the output terminal QA, and after dividing the frequency by 4, the signal 1097 of (C) is sent to the output terminal QB, and after dividing the frequency by 8, the signal 1 of (d>
098 is obtained at the output terminal QC.

FIG. 15F shows the frame pulse circuit 110Q, and FIG. 15G shows a timing chart of the waveforms of each part thereof.

1110 and 1111 are hexadecimal counters, and both have a reset signal 2 at their clear terminal CL when the power is turned on.
1 is applied via the inverter 1117, and the clock terminal is applied via the inverter 111B, as shown in FIG. 15G(a).
A signal 1098 shown in is applied. The outputs QA, QB, QC, and QD of the hexadecimal counter 1110 include the 15th G
As shown in Figures (b), (c), (d>, (e)) (a)
A signal 1121 is obtained by dividing the signal 1098 by 2, a signal 1122 is obtained by dividing the signal by 4, a signal 1123 is obtained by dividing the signal 1098 by 8, and a signal 1124 is obtained by dividing the signal 1098 by 16. When the hexadecimal counter 1110 reaches a full count state, an output is provided from the carry-out terminal CO, which is applied to the enable terminals P and T of the hexadecimal counter 1111, and the output terminal Q is applied to the enable terminals P and T of the hexadecimal counter 1111.
From A, a signal 1125 is obtained by frequency-dividing the signal 1098 in (a) by 32, as shown in FIG. 15G (f).

Each of the frequency-divided signals 1121 to 1125 is passed through an AND gate 1114 to a signal 1126 shown in FIG. 15G (Q).
is applied to the data terminal of the D flip-flop 1112. The signal 1098 in FIG. 15G (a>) is applied to the clock terminal of this D flip-flop 1112 via two inverters 1118 and 1119, and the signal 1127 in (h) is obtained at its Q output. The signal 1127 is applied to the data terminal of the D flip-flop 1113, and the signal 1098 shown in (a) is applied to its tally terminal via the inverter 1118, and the Q output shown in (1) is applied to the data terminal of the D flip-flop 1113. A signal 1128 is obtained.

FIG. 15H shows multiframe pulse circuit 1150.
FIG. 15I shows a timing chart showing the waveforms of each part of the circuit.

1151 and 1152 are hexadecimal counters, and both have a reset signal 21 at their clear terminal CL when the power is turned on.
is applied via an inverter 1160, and a signal 1128 shown in FIG. 15I (a) is applied to the clock terminal. Output QA, QB, Q of hexadecimal counter 1151
C, QD include Figure 15I (b), (C), (d), (
As shown in e), a signal 1171 obtained by dividing the signal 1128 of (a> by 2), a signal 1172 obtained by dividing the frequency by 4, 1172. a signal obtained by dividing the frequency by 8, 1173, and a signal 1174 obtained by dividing the frequency by 16 are obtained.1
When the hexadecimal counter 1151 reaches the full count state, an output is output from the carry-out terminal GO, and it becomes 1.
Applied to enable terminals P and T of hexadecimal counter 1152, from its output terminal QA, as shown in FIG.
As shown in FIG. 3, a signal 1175 is obtained by frequency-dividing the signal 1128 in (a) by 32.

The frequency-divided signal 1174 of (e) is directly applied to the AND gate 1153, and each of the frequency-divided signals 1171 to 1173.1175 is applied to the AND gate 1153 via inverters 1155 to 1157. Figure 15I (
The signal 1176 shown in h) is obtained. Also, the inverter 115
AND gate 1154 applied with signal 1174 through 8 and signal 1175 through inverter 1159.
outputs a signal 1177 shown in FIG. 15I (q).

FIG. 16A shows the first to fourth transmission timing circuits 120.
The circuit diagram of the first transmission timing circuit included in
FIG. 68 shows a timing chart of the waveforms of each part.

Signals 1 of (b) to (f) constituting the bus signal 1120 whose bit numbers are expressed numerically in FIG. 168 (a)
121 to 1125 are inverters 1221 to 1, respectively.
225 to AND gate 1212;
A signal 1231 shown in (h) is output from there.

The flip-flop 1 receives the reset signal 21 when the power is turned on and is applied to the clear terminal CL via the inverter 1226.
The clock terminal of 211 receives the signal 1098 shown in (g).
is applied, and the signal 12 of (h) is applied to the data terminal.
31 is applied, and the signal 1 shown in (i) is applied to its Q output.
232 is obtained.

Each output of inverters 1221, 1223 to 1225 and signal 1122 are applied to AND gate 1213, and (
It outputs a signal 1233 shown in j).

FIG. 16C shows the first to fourth transmission timing circuits 120.
The timing chart showing the waveforms of each part of the second transmission timing circuit included in 0 is shown in FIG. 16E (a).
~(k>).

Signals 1121 to 1125 constituting the bus signal 1120 whose bit numbers are expressed numerically in FIG. 16E (a)
Of these, signals 1121 to 1123 are directly connected to signal 112.
4 and 1125 are inverters 1251 and 1252
is applied to NAND gate 1244 via (C)
A signal 1261 shown in is output, and the AND gate 12
45, and the outputs of inverters 1251 and 1252 are also applied to AND gate 1245, the output of which becomes signal 1262 shown in (d), which is applied to terminals A and B of 8-bit shift register 1241.

Clear terminal CL of 8-bit shift register 1241
In this case, the reset signal 21 at power-on is sent to the inverter 12.
The signal 1098 shown in (b) is applied to its clock terminal, and the signal 1098 shown in (b) is applied from its third and fourth outputs QC' and QD, respectively. and signal 1263 shown in (f)
and 1264 are output.

Clears the output of inverter 1253 when power is turned on.Terminal C
D flip-flop 12 reset by applying to L
The signal 1098 (b) is applied to the clock terminals of 42 and 1243 via the inverter 1254, and the signal 1263 (e) is applied to the data terminal of the D flip-flop 1242, causing the Q output to be ( It is obtained as a signal 1265 shown in g).

The signal 1265 is applied to the data terminal of the D flip-flop 1243 to obtain the signal 1266 shown in FIG. A signal 1268 shown in i) is obtained.

The AND gate 1246 to which the output of the inverter 1254 and the signal 1264 are applied outputs the signal 1267 shown in (j>
This signal 1267 is applied to the AND gate 1247 together with the signal 1266, and the signal 1269 shown in (k) is output.

FIG. 16D shows the first to fourth transmission timing circuits 120.
A circuit diagram of the third transmission timing circuit included in the third transmission timing circuit is shown, and the timing and fv-t of the waveform of each part are shown in (a), (b), (e) to (p) of Fig. 16E. There is.

Signals 1121 to 11 constituting the bus signal 1120 in which the bit numbers shown in FIG. 16E (a> are expressed numerically)
Signals 1121, 1123.1125 of 25 are connected to inverters 1291 to 1293, and signals 1122.
1124 is directly applied to the NAND gate 1283 to output the signal 1301 shown in (2), which is applied to the data terminal of the D flip-flop 1281.

A reset signal 21 at power-on is applied to the clear terminal CL of this D flip-flop through the inverter 1294, and the D flip-flop has already been reset. A signal 1098 shown in (b) is applied to the clock terminal of the D flip-flop 1281, and a signal 1302 shown in (m>) is obtained at the not-Q output.

This signal 1302 is applied to a D flip-flop 1282. The clear terminal CL of this D flip-flop 1282 is the clear terminal C of the D flip-flop 1282.
It is connected to L and is reset when the power is turned on. D
The clock terminal of flip-flop 1282 receives signal 1.
098 is applied via the inverter 1295, and the signal 1303 shown in (n> is output to the Q output thereof.

The inputs of AND gate 1284 include signal 1121.1
122.1125 are each inverter 1291.1
via 296.1293 and also signal 1123.112
4 is directly applied, and a signal 1304 shown in (p) is obtained at its output.

FIG. 16F shows the first to fourth transmission timing circuits 120.
The fourth transmission timing circuit included in the 16th . FIG. G shows a timing chart showing the waveforms of each part.

In FIG. 16G (a), a bus signal 1170 representing a frame number numerically is shown to explain the timing relationship with one other signal.

The AND gate 1311 has a signal 123 shown in (f).
2 and a signal 1176 shown in (C) are applied, and a signal 1316 shown in (h) is output.

The AND gate 1312 has a signal 123 shown in (g).
3 and a signal 1176 shown in (C) are applied, and a signal 1317 shown in (i) is output. and gate 131
3 is applied with a signal 1303 shown in (d) and a signal 1177 shown in (b), and outputs a signal 1318 shown in (e). Since each signal shown in FIG. 16G is drawn based on the bus signal 1170 representing the frame number shown in (a), the signal 1177 in FIG. 15I (g) is the same (
h) signal 1176, signal 1303 in Fig. 16E(n)
．． Signals 1232.12 in Figures 16B (i) and (j)
33, it is displayed significantly shorter in time.

FIG. 17A shows a circuit diagram of the reception timing circuit 1350, and FIGS. 17B, 17C, and 17D show timing charts of waveforms of each part thereof.

1351 is an 8-bit shift register, and its input terminals A and B receive the signal 10 shown in FIG. 170(b).
98 is applied to the clock terminal of the inverter 1.
The clock 51 shown in FIG. 17C (a) is applied through the 361, and from the third output terminal QC, the clock 51 shown in FIG.
A signal 1371 shown in C) is output. This output is D
applied to the data terminal of flip-flop 1352;
The clock terminal of this D flip-flop 1352 has
The clock 51 in FIG. 17C (a>) is applied, the signal 1376 in FIG. 17(d) is applied to the Q output, and the signal 1376 in FIG.
You will get the inverse of that.

In FIG. 17B (a), among the signals 1121 to 1125 (b) to (f) forming the bus signal 1120 in which the bit numbers are expressed numerically, the signal 1125 is directly transmitted, and the signal 1124 is transmitted by the inverter. 1362 to an AND gate 1356, the output of which is a signal 1372 shown in (i).

This signal 1372 is applied to the D flip-flop 1353, and the (d> signal 1123 is applied to the clock terminal of the D flip-flop 1353, and the (j> signal 1373 is obtained at its Q output. b) Signal 11
21 applied to the clock terminal of D flip-flop 1
A signal 1373 of (j>) is applied to the data terminal of 354, and a signal 1374 shown in (k) is obtained at its Q output.

AND gate 1357 has signals 1374 and (h)
The inverted signal 1376 of the signal 1376 is applied to the output, and the signal 1377 of (e>
The relationship between the clock 51 and the signal 1376 in FIGS. 17G and 137H is the same as that shown and explained in an enlarged manner in FIGS. 17C (a) and (b). Therefore, the rising and falling edges of signal 1377 correspond to clock 51 of FIG.
It is synchronized with the rise of

The AND gate 1355 receives the signals 1121 . (d) Signal 1123. (e) Signal 112
4. The signal 1125 in (f) is directly connected to the signal 11 in (C).
22 is applied via the inverter 1363, and a signal 1375 of (m> is output. This signal 1375 and (h
) and the inverted signal 1376 of the AND gate 1358 outputs a signal 1378 of (n).

The AND gate 1359 has a signal 1378 commonly shown in FIG. 178(n) and FIG. 17D(C), and a period of frame numbers O to 7 as shown in FIG. 15C(b). In response to the signal 1177 shown in FIG. 17D, the signal 1379 shown in FIG. 17D (d) is output. FIG. 17D (a) shows a bus signal 1120 representing a bit number within one frame.
and (b) shows the bus signal @1170 representing the frame number.
and signals 1378 in (C) and (d).
．． 1379.

Figure 18A shows 1. Second conference timing circuit 1400
The circuit diagram of the first conference timing circuit included in the 18th
FIG. 8 shows a timing chart of the waveforms of each part.

FIG. 188(C) shows the bus signals 1120 (d) to (h
) among the signals 1121 to 1125, the signals 1122 to 1
125 is applied to the NOR gate 1413 and (p)
A signal 1437 is output.

A signal 1121 (d) is applied to the NAND gate 1414 via an inverter 1421, and a signal 1437 (D) is directly applied to the NAND gate 1414, and a signal 1438 (Q) is obtained at its output.

The input terminals A and B of the decoder 1411 are supplied with the signal 1097 shown in FIG. 188(a) (see FIG. 15E(C)).
) and (b) signal 1098 (see FIG. 15E(d)
) is applied, the signal 1438 of (a) is applied to the enable terminal G, and the output terminals YO-Y3 output the signals via inverters 1422 to 1425, respectively.
Signals 1431 to 1434 shown in (i) to (1) are output.

The NAND gate 1415 has a signal 1121 of (+j>
and (p) signal 1437 are applied, and (r) signal 1
439 is output. Input terminal A of decoder 1412
and B are applied with the signal @ 1097 of (a> and the signal 1098 of (b), respectively), and the signal 1439 of (r) is applied to the enable terminal G, and its output terminal YO.

Yl outputs signals 1435 and 1436 of (m>, (n)) via inverters 1426 and 1427, respectively.

FIG. 18C shows the first. Second conference timing circuit 140
The circuit diagram of the second conference timing circuit included in
Figure 8D shows a timing chart of the waveforms of each part.

1451 and 1452 are D flip 70 knobs,
Each of the data terminals D1 to D3 has a terminal as shown in FIG.
>, (I, (n>) signals 1432.1434.
1436 is applied.

The signal 1096 shown in FIG. 18D (b) is applied to the clear terminal CL of the D flip-flop 1451, and the clock 51 shown in FIG. Each (j) ~
Signals 1471 to 1473 shown in (e) are output.

The D flip-flop 1452 has a signal 1097 obtained by dividing the frequency of the signal 1096 (b) by 2 to its clear terminal CL, and a signal 1096 (b) to its clock terminal, and outputs 01 to Q3 respectively. Signals 1476 to 1478 of (q) to (i) are output.

The signal 1096 in (b) is input to the NOR gate 1455 by 2.
The frequency-divided signal 1097 and the signal 1096 (b) are applied, and the output is the signal 1479 (C).
It is applied to the data terminal of flip-flop 1453. The signal 1096 in (b) is applied to the clear terminal CL of this D flip-flop 1453 via the inverter 1458, and the clock 51 in (a) is applied to its clock terminal.
is applied via an inverter 1459, and a signal 1480ffi (d) is obtained at its Q output.

The signal 1096 in (b) is input to the NOR gate 1456 by 2.
The frequency-divided signal 1097 and the signal 1096 of (b>) are applied via the inverter 1458, and the signal 14 of (e)
81 is output. D to which this signal 1481 is applied
The clear terminal CL of the flip-flop 1454 has (b
> signal 1096 is applied to this clock terminal (
The clock 51 in a) is applied via an inverter 1459, and a signal 1482 shown in (f) is obtained at its Q output.

19-1 to 19-22 are flowcharts showing the flow of operations of the main device 10 and CPU 20 shown in FIGS. 1A and 2A.

The CPtJ20 checks at regular intervals whether or not the D information representing control information is output from the terminal device 70 (S20
01, Figure 19-1), if the D information is not detected (3
2001N>, check whether the signal from the office line interface 11, so-called 8@, is being output (32002>
, if it is not output from the central office line interface 11, the process returns to step 32001 (32002N>).

In step 32002, the signal from the office line interface,
When the CPU 20 detects a so-called station arrival (S2002Y
), detects an incoming call from the office line 12, puts it on the D information, and sends the D information transmitting/receiving circuit 170 to the extension line interface 1.
00 to the terminal device 70 52021, the first
9-4), the process returns to step 32001.

In step 52001, if there is D information, the CPU 20
When it is determined (S200'1Y), the content of the information is deciphered to check whether or not a call is being requested from the terminal device 70 to the central office line 12 (32003, Fig. 19-1). If (32003Y), the process moves to the station line origination subroutine, and if there is no request, (32003Y)
N), the terminal device 70 is connected to another terminal device 7 in the same system.
It is checked whether the call is a so-called extension call made to 0 (S2004>).

If the CPU 20 confirms that the call is an extension call, it moves to the extension call subroutine (52004Y), and if it is not an extension call (32004N>), it checks whether or not a simultaneous broadcast is requested (S2005>).

When it confirms that a simultaneous broadcast is requested, it moves to the simultaneous broadcast subroutine (52005Y), but when it finds out that it has not requested it (32005N>), it requests the broadcast of background music (hereinafter abbreviated as BGM). It is confirmed whether or not there is one (S2006>).

If it is confirmed that a BGM broadcast is requested, the process moves to the BGM broadcast subroutine (52006Y), and if it cannot be confirmed (32006N>), it is checked whether or not a conference call is requested (S2007, 19-2 figure).

If it is confirmed that a conference call is requested, the process moves to the conference call subroutine (52007Y), and if it cannot be confirmed (32007N>, the terminal device 7 that received the notification of the call arrival to the terminal device 70 in step 52002Y)
It is checked whether the response is a so-called local response, which is a response from 0 (32008).

If it is confirmed that it is a station arrival response, the process moves to the station arrival response subroutine (52008Y), and if it cannot be confirmed (32008N>, another terminal in response to calling another terminal device 70 in the same system in step 52004Y). It is checked whether the response signal from the device 70 is a so-called fixed response (32009>).

If it is confirmed that it is a stuck response, the process moves to the stuck response subroutine (52009Y), and if it cannot be confirmed (32009N>, a so-called so-called check is performed to determine whether or not the call with the central office line 12, which was executed as a result of step 52008Y, has ended. Check the end of the local line (S2010>, and if the end of the local line is confirmed, proceed to the subroutine for ending the local line. 52010Y
), if it cannot be confirmed (3201ON>), it is checked whether the call between the terminal devices 70 that was executed as a result of step 52009Y has been terminated, that is, a so-called extension termination is requested (32001>).

If it is confirmed that the request is to end the extension call, the process moves to the subroutine for ending the extension call (52011Y), and if it cannot be confirmed (32011N), the conference call that was executed as a result of 32007Y is ended, a so-called conference end request is made. Check to see if it has been done (32012>).

If the request to end the conference is confirmed, the process will proceed to the conference end subroutine (32012Y), and if the request cannot be confirmed (32012Y).
32012N>, 52005Y, it is checked whether or not the executed simultaneous broadcast has ended, that is, a so-called simultaneous broadcast end is requested (S2013, FIG. 19-3).

If the request for ending all broadcasts is confirmed, the process moves to the subroutine for ending all broadcasts (32013Y), and if it cannot be confirmed (32013N>, the BGM broadcast that was executed as a result of step 52006Y ends, so-called BGM ending is requested. Check to see if it has been done (32014>).

If the request for ending the BGM call is confirmed, the process moves to the BGM ending subroutine (32014Y), and if the request cannot be confirmed (32014N>), an incoming call response is made in step 52008Y, and then the call between the central office line 12 and the terminal device 70 is terminated. It is checked whether or not the request is for temporary hold, so-called station line hold (S2015).

If it is confirmed that the station line hold is requested, the process moves to the station line hold subroutine (82015Y), and if it cannot be confirmed (32015N>, the station line hold is canceled in step 32015Y, so-called station line hold). It is checked whether cancellation is requested (S2016>).

If it is confirmed that the station line hold release is requested, the process moves to the station line hold release subroutine (82016Y), and if it cannot be confirmed (32016N>, step 5200).
Check whether the fixed response of 9Y requests temporary hold of the extension call, so-called extension hold (
32017>.

If it is confirmed that the extension has been requested, the process moves to a subroutine for releasing the extension from hold (32017Y), and if it cannot be confirmed (32017N>, step 32017Y).
It is checked whether this is a so-called extension hold release request (32018).

If you confirm that you are requesting to release your extension from hold,
52018Y) to move to subroutine for releasing extension hold.
, if it cannot be confirmed (32018N>, the process returns to step 52001).

In step 32003 (Figure 19-1), when the call to the central office line is confirmed in CPtJ20, the central office line 12
The office line interface 119 and the office line communication circuit 250. Connects to terminal device 70 via extension interface circuit 100 to transmit dial tone from central office line 12 to terminal device 70.
The upstream signal is sent to the receiving circuit 1502 and the central office line communication circuit 2.
50. The OR circuit 132 is connected to the office line 12 via the office line interface 11 (S2031, FIG. 19-5).

Distinguish whether the central office line 12 is for dial pulse (DP>) or button button (PB) (82032>, and in either case (S2032P)
B, DP>, D It is determined whether dial information is included in the information 32033.2034>, and if dial information is not included (S2033N, 52034
N>, return to step 32001, and if included (S2033Y, 2034Y), the central office line communication circuit 25
The transmission control circuit 240 in 52036.0 prohibits the dial signal from returning to the terminal device 70 as a sidetone.
32041, Figure 19-6.

(Fig. 19-7), the dial signal from the terminal device 70 is
The PU 20 reads the information, and in the case of DP, the CPU 20 instructs the office line interface 11 to send only a dial signal to the office line, and in the case of PB, the office line communication circuit 250. OR circuit 1
A transmission line is formed to send only the dial signal to the office line via 32037.32042>, and the dial number is sent out (32038.52043>).

Here, dial pulse (DP>
When transmitting a dial number, the central office line interface 11 generates a dial pulse signal and sends it to the central office line, and when transmitting a dial number using the button button (PB), the button dial The signal 66, which is the sound source of the signal, is transmitted to the central telephone communication circuit 250. OR circuit 131
It is sent to the office line 12 via the office line interface 11.

When the dial signal is sent out, the sending control circuit 240
The sidetone prohibition is canceled, a downward communication path from the terminal device 70 to the central office line is formed (S2039.32044), and an upward communication path from the central office line to the terminal device 70 is also formed (S2039.32044).
2040, 52045).

This process continues until there is no more dialing information (S
2033, 2034, Figure 19-5).

In step 52004 (FIG. 19-1), if the terminal device 7Q is an extension calling a separate terminal device 70 (S2004Y), the dial tone signal 67 is sent to the extension communication circuit 200° and the extension interface circuit 100. 32 to connect to the originating terminal device 70 via the originating terminal device 70 and sending a dial tone to the originating terminal device 70
051, FIG. 19-8), the CPU 20 receives the dial information from the caller via the D information transmitting/receiving circuit 170, deciphers the destination, and notifies the destination terminal device 70 of the incoming call (3
2052>. After that, the process returns to step 52001.

In step 32005 (Figure 19-1), if it is determined that the request is for simultaneous broadcasting (S2005Y)
, to form a transmission path from the requesting terminal device 70 to the extension call circuit 200 via the receiving circuit 150 52061
, FIG. 19-9), and furthermore, a transmission path is formed from the extension call circuit 200 to the broadcasting circuit 700 (52062>), and in the opposite route, from the broadcasting circuit 700 to other terminals via the extension interface circuit 100. Form a transmission path to the device 70 and broadcast 52063>, step 5200
Return to 1.

When a request for BGM broadcast from one terminal device 700 is confirmed in step 2006 (Figure 19-1) (S200
6Y), connect the signal 68 which is a BGM sound source to the sound source circuit 720 52071, Figures 19-'10), the sound source circuit 7
20 to the extension interface circuit 100, and sends the signal 68, which is a BGM sound source, to the terminal device 70 that requested the BGM broadcast (82072>. Then, the process returns to step 32001.

In step 32007 (Fig. 19-2), when it is confirmed that the conference call request is from a terminal device 70 other than the terminal device 70 that is currently talking to the central office line 12 (S2007Y
), from the office line 12 via the office 5 line interface 11 to the office line communication circuit 250 . Extension interface circuit 100
82081 (FIGS. 19-11)), from the terminal device 70 to the receiving circuit 1509 and the central office line communication circuit 250. The route connected to the office line 12 via the OR circuit 139 office line interface 11 is disconnected (32082).

Therefore, from the office line 12 to the office line interface 11° conference call circuit 350. Form a down route to the terminal device 70 via the extension interface circuit 100 (32083)
, from the terminal device 70 to the receiving circuit 150 and the conference call circuit 35
0. OR circuit 132 Connects to the office line 12 via the office line interface 11 □ forms a route (320
84). Other terminal devices 70 that have offered to participate in the conference call
Also, both routes formed in steps 32083 and 32084 are formed, and audio information is converted between each terminal device 70 and the office line 12 to enable a conference call (3208
5. In step 32008 (Figure 19-2), when it is confirmed that it is a response to the call in step 32021 (Figure 19-4) (32008Y), the station line 1
32091, No. 19-
12), and from the receiving circuit 150 to the central office line communication circuit 250.
A transmission path to the OR circuit 13 is formed via (3209
2>, a call is made between the office line 12 and the terminal device 70,
Return to step 32001.

In step 32009 (Fig. 19-2), when an incoming call from another terminal device 70 is confirmed via the D information transmitting/receiving circuit 170 in step 52052 (Fig. 19-8) (S2009Y), an extension call is received. circuit 200
52101 (FIGS. 19-13)) and the receiving circuit 150.
to the extension call circuit 200 (321
02>, form a transmission path to one terminal device 70, and similarly form transmission paths to other terminal devices (S2103
．． 52104>, a call is made between both terminal devices 70, and the process returns to step 32001.

In step 32010 (Figure 19-2), the 19th
- When it is confirmed that the call between the office line and the terminal 70 in Figure 12 has ended (S201Y), the transmission path from the office line communication circuit 250 to the extension interface circuit 100 and the reception circuit 150 are confirmed.
The transmission line from the office line communication circuit 250 to the OR circuit 13 is cut off (S2'110, 3211L No. 19-1
4), the connection between the office line 12 and the terminal device 70 is terminated and the process returns to step 52001.

In step 52011 (Figure 19-2), the 19th
- When it is confirmed that the call between the terminal devices 70 in FIG.
50 to the extension call circuit 200, and
32121. S
2122゜Figures 19-15), and similarly disconnect the other terminal device 70 (32123, 521).
24>, return to step 2001.

In step 2012<Figure 19-2), Step 19-
After confirming that the conference call in Figure 11 has ended (S20
12Y), the route from the office line 12 formed in step 2083 (FIGS. 19-11) to the extension interface circuit 100 via the conference call circuit 350 is clearly established 321.
31, FIGS. 19-16), the route from the reception circuit 150 formed in step 32084 to the OR circuit 13 via the conference call circuit 350 is determined 32132>, and at the same time, the participants in the conference call formed in step 32085 are (52133). Also, the two routes cut off in steps 32081 and 32082 are re-formed (2134, 2135).
, the conference call is terminated, the process returns to step 32001, and in order to resume the call between the office line 12 and one terminal device 70 before the conference call, the call is returned to the subroutine for calling response shown in FIGS. 19-12. enter.

In step 32013 (Figure 19-3), the 19th
-9 When it is confirmed that the subroutine for broadcasting shown in Figure 9 has ended (32013Y), the transmission line is transmitted from each terminal device 70 to the extension call circuit 200 via the reception circuit 150, and from the extension call circuit 200 to the broadcast circuit 700. 52141.2142, Figures 19-17), and also cut off the transmission paths from the broadcast circuit 700 to each terminal device 70 formed via each extension interface circuit 100 (32143 ), return to step 2001.

In step 52014 (Figure 19-3), the 19th
- After confirming that the 80M broadcast in Figure 10 has ended (3
2014Y), the sound source circuit 720 makes sure that the transmission route of the signal 68 which is BGM is 52151, No. 19-18.
), from the sound source circuit 720 to the extension interface circuit 10
0 (32152>, step 20
Return to 01.

In step 32015 (Figure 19-3), the 19th
- In a call between the central office line and the terminal device 70 in Figure 12,
When the request for station line hold from the terminal device 70 is confirmed (S2
015Y), from the receiving circuit 150 to the central office line communication circuit 250
(S2161, Figure 19-19)
, the hold tone signal 69 is sent to the central office line communication circuit 250 . 32162>, the process returns to step 2001.

In step 32016 (Figure 19-3), the 19th
- When it is confirmed that the terminal device 70 requests cancellation of the station line hold shown in Figure 9 (S2016Y), the transmission path of the signal 69 which is the hold tone is cut off and the transmission of the hold tone is terminated.52
171, Figures 19-20), a transmission path is formed from the receiving circuit 150 to the central office line communication circuit 250 to resume communication.52
172>, return to step 32001.

In step 32017 (Figure 19-3), the 19th
- 13 When there is a request from any terminal device 70 to hold the extension call during a call between the terminal devices 70 in the extension shown in FIG. No. 19-21
), the transmission line connecting the signal 69 to the extension call circuit 200 is turned on, and the hold tone that is the signal 69 is transmitted to the extension call circuit 200.
32182>, the process returns to step 52001.

In step 82018 (Figure 19-3), the 19th
- When the request to release the hold of the extension call shown in Figure 21 is confirmed (S2018Y), the extension call circuit 100 changes the hold tone transmission route 52191 (Figures 19-22), and the receiving circuit 150 makes the extension call. A transmission path to the circuit 200 is formed to resume the call between the terminal devices 70 (32192), and when the call ends, the process returns to step 32001.

[Effect of the invention] As is clear from the above explanation, according to the present invention,
It is possible to simultaneously broadcast to many terminal devices from a sound source such as a central office line or terminal device, and it is also possible to broadcast not only over short distances but also over long distances from the main control device to the terminal devices.
It becomes possible to connect a terminal device without changing the circuit, and moreover, it becomes possible to provide many functions.

In addition, despite the PCM conversion, it has become possible to realize an economical system even in a small scale. Therefore, the effects of the present invention are extremely large.

[Brief explanation of the drawing]

1A is a conceptual configuration diagram for explaining the principle of a key telephone device that enables the function of a broadcast trunk related to the present invention; FIGS. 1B, 1C, 1D, and 1E are 1A
Figure 1F is a timing chart showing waveforms for each part of the figure. Figure 1F is a timing chart showing waveforms to explain why the length of the transmission line is limited. Figure 1G is a timing chart showing the waveforms of each part of the figure. Figure 1G is a timing chart showing the waveforms of each part of the figure. Fig. 1H is a principle block diagram of an extension call trunk that enables communication between terminal devices in a key telephone device; Fig. 1J is a principle block diagram of a broadcast trunk according to the present invention for simultaneously transmitting the same information to a large number of terminal devices connected to a key telephone device. , FIG. 2A is a conceptual configuration diagram showing an embodiment of the main control device 10 including various circuits for realizing various functions shown in FIGS. 18 to 1J, and FIG. 2B is a diagram of FIG. 2A. FIG. 3A is a circuit configuration diagram showing an example of a terminal device connected to the main control device 10 shown in FIG. Interface circuit 1
A timing chart showing the waveforms of each part of 00, Figure 3C is the extension interface circuit 1 shown in Figure 3A.
3D is a timing chart showing waveforms of each part of the code conversion circuit 110 shown in FIG. 3C, and FIG. 4A is a circuit diagram showing an embodiment of the code conversion circuit 110 included in A circuit diagram showing one embodiment; FIG. 4B is a timing chart showing waveforms of each part of the receiving circuit 150 shown in FIG. 4A; FIG. 5A is a circuit configuration diagram showing one embodiment of the D information transmitting/receiving circuit 170; FIG. 5B is a timing chart showing the waveforms of each part of the D information transmitting/receiving circuit 170 shown in FIG. 5A, and FIG.
FIG. 5D is a circuit diagram showing an embodiment of the information transmitting circuit 171; FIG. 5D is a circuit diagram showing an embodiment of the D information receiving circuit 180; FIG. 6B is a circuit diagram showing an embodiment of the multiplexer 210, FIG. 6C is a circuit diagram showing an embodiment of the S/S register 220, and FIG. 6D is a timing chart showing waveforms of various parts of the S/S register 220. , FIG. 6E is a circuit diagram showing one embodiment of the demultiplexer 227A, FIG. 6F is a circuit configuration diagram showing another embodiment of the extension communication circuit 200, and FIG. 6G is a circuit diagram showing one embodiment of the sending control circuit 240. Circuit diagram: FIG. 7A is a circuit configuration diagram showing an embodiment in which the office line communication circuit 250 is connected for communication between office lines; FIG. 7B is a circuit diagram showing an embodiment of the multiplexer 280; FIG. 7C is a circuit diagram showing an embodiment of the multiplexer 280; is a circuit diagram showing one embodiment of the demultiplexer 27OA, FIG. 7D is a circuit configuration diagram showing another embodiment of the central office line communication circuit 250, FIG. 7E is a circuit diagram showing one embodiment of the multiplexer 310, and FIG. The figure shows a circuit diagram of one embodiment of the transmission switching circuit 290 and a table showing the relationship between the switching signal and the output signal, FIG. 7G is a circuit configuration diagram showing another embodiment of the central office line communication circuit 250, and FIG. 8B is a circuit diagram showing an embodiment of the conference call circuit 350; FIG. 8B is a circuit diagram showing an embodiment of the multiplexer 360; FIG. 8C is a circuit diagram showing an embodiment of the multiplexer 361; 8D is a circuit diagram showing one embodiment of the S/P register 364A, FIG. 8E is a circuit diagram showing one embodiment of the multiplexer 380, FIG. 9A is a circuit diagram showing one embodiment of the adder 430, and FIG. 9B is a circuit diagram showing one embodiment of the multiplexer 380. 9C is a circuit diagram showing an example of the attenuation instruction circuit 460; FIG. 9D is a circuit diagram showing an example of the attenuation circuit 470; 9E is a circuit diagram showing an embodiment of the full adder 500; FIG. 9F is a circuit diagram showing an embodiment of the first adder 510; FIG. 9G is a circuit diagram showing an embodiment of the temporary storage circuit 610. 9H is a circuit diagram showing one embodiment of the second adder 550, FIG. 91 is a circuit diagram showing one embodiment of the linear/nonlinear converter 650, and FIG. 10B is a circuit diagram showing one embodiment of the P/S register 661; FIG. 10C is a circuit diagram showing one embodiment of the demultiplexer 670; FIGS. 10D and 10E. 11 is a timing chart showing the main operations of the conference call circuit 350, FIG. 11 is a circuit diagram showing an embodiment of the broadcast circuit 700 which is the main part of the broadcast trunk according to the present invention, and FIG. 12A is the sound source circuit 720. FIG. 128 is a circuit diagram showing an embodiment of the multiplexer 721; FIG. 13A is a circuit diagram showing an embodiment of the CPU interface circuit 800; FIG. 13B is an interrupt circuit. 13C is a timing chart showing waveforms of each part of the interrupt circuit 801, FIG. 13D is a circuit diagram showing an example of the address decoding circuit 810, and FIG. 13E is a circuit diagram showing an example of the address decoding circuit 810. 14A is a circuit diagram showing an embodiment of the 4-bit latch circuit 850. FIG. 148 is a timing chart showing the waveforms of each part of the 4-bit latch circuit 850. The timing chart, Figure 14C, shows the 3-bit timing chart.
A circuit diagram showing one embodiment of the latch circuit 900, FIG. 14D is a timing chart showing waveforms of various parts of the 3-bit latch circuit 900, and FIG. 14E is a 2-bit latch circuit 900.
14F is a timing chart showing waveforms of various parts of the 2-bit latch circuit 950; FIG. 15A is a circuit configuration diagram showing an embodiment of the timing circuit 1000; FIG. 15B and 15C show timing circuit 1000.
15D is a circuit diagram showing an embodiment of the frequency dividing circuit 1090, FIG. 15E is a timing chart showing the waveforms of each part of the frequency dividing circuit 1090, and FIG. 15F is a frame・A circuit diagram showing an embodiment of the pulse circuit 1100, FIG. 15G is a timing chart showing waveforms of each part of the frame pulse circuit 1100, and FIG. 15H is a circuit diagram showing an embodiment of the multi-frame pulse circuit 1150. , FIG. 15I is a timing chart showing waveforms of each part of the multi-frame pulse circuit 1150, and FIG. 16A is a circuit showing an embodiment of the first transmission timing circuit included in the first to fourth transmission timing circuits 1200. 16B is a timing chart showing waveforms of each part of the first transmission timing circuit, and FIG. 16C is a circuit showing an embodiment of the second transmission timing circuit included in the first to fourth transmission timing circuits 1200. Figure 16D is a circuit diagram showing an embodiment of the third transmission timing circuit included in the first to fourth transmission timing circuits 1200, and Figure 16E is a circuit diagram showing waveforms of each part of the first to third transmission timing circuits. FIG. 16F is a circuit diagram showing an embodiment of the fourth transmission timing circuit included in the first to fourth transmission timing circuits 1200, and FIG. 16G shows waveforms of each part of the fourth transmission timing circuit. FIG. 17A is a circuit diagram showing an embodiment of the reception timing circuit 1350; FIGS. 17B, 17C, and 17D are timing charts showing waveforms of each part of the reception timing circuit 1350; Figure 1. 18B is a circuit diagram of the first conference timing circuit included in the second conference timing circuit 1400. FIG. 18B is a timing chart showing waveforms of each part of the first conference timing circuit. FIG. A circuit diagram of the second conference timing circuit included in the second conference timing circuit 1400, FIG. 18D is a timing chart showing waveforms of each part of the second conference timing circuit, and FIGS. 19-1 to 19-22 are Main device 10 and CP
It is a flowchart showing the flow of operation of U20. 10... Main controller 11A, 11B... Office line interface 12A, 12
B... Office lines 13A, 13B... OR circuits 14A, 14B, 15A, 15B. 16A, 16B...Signal 20...CPU 21...Reset signal 22...Read signal 2
3... Write signal 25... Address bus signal (including signals 26 to 33) 35... Data bus signal (including signals @36 to 43)
50... Clock generator 51... Clock 60A-60F... Transmitter/receiver 61A-61F... Signals 63A-63C... Transmission lines 66-69... Signals 70, 70A-70E... Terminal devices 71A to 71G, 72A to 72G...Signal 100A to
100D... Extension interface 10'1... OR gate 102... NOAH gate 103... Codec 104... Resistor 105... Telephone 106
...Transistors 107, 108A, B, C, D to 109A, B. C, D... Signal 110... Code separation circuits 111 to 114... D flip-flop 115.11
6... Nando Gate 117-119... Noah Gate 120... Exclusive or Gate 121.
122... Inverters 131-140... Signals 150A-150D... Receiving circuit 151... D flip-flop 152.153... AND gate 154-... OR gate 155.156... Inverter 161.162A-D...Signals 170A-170D...D information transmitting/receiving circuit 172...
・P/S register 173...AND gate 174...Inverter 177, 178, 179A to 179D...Signal 180
...D information receiving circuit 181...8-bit shift register 182...
3-state buffer 1 200... Extension call circuit 21OA, 210B... Multiplexer 211...
8-bit multiplexer 212... 4-bit multiplexer 213... OR gate 214... Inverters 218A, 218B... Signals 22OA, 220B... S/S register 221...
8-bit shift register 222...AND gate 223...OR gate 225A, 225B...signal 227A, 227B...-Demultiplexer 228...
...Decoders 229-233...Inverters 235A, B-239A, B...Signals 24OA, 24
0B... Sending control circuit 241... AND gate 242... Inverter 248A, 248B... Signal 25OA, 250B... Office line communication circuit' 251A
, B~257A, B...signal 260A~260D...
・S/S registers 268A to 268D...Signals 27OA, 270B...Demultiplexer 271...
・Decoders 272 to 278...Inverters 28OA, 280B...Multiplexer 281...
8-bit multiplexer 282... 4-bit multiplexer 283... OR gate 284... Inverter 288A, B... Signal 290... Output switching circuit 291, 292... AND gate 293...・OR gate 294...Inverter 298...Signal 310・
...Multiplexer 311...8-bit multiplexer 312...4
Bit multiplexer 313.314...AND gate 315.316...OR gate 317-321...Inverter 328.329...Signal 350...Conference call circuit 358...μ/ A switching signal 360...Multiplex circuit 361A, B, C...Multiplexer 362A, B
, C... Signals 364A, B, C... S/P registers 365'A, B
, C... bus signal 366A, B, C to 373A, B, C... signal 380
...Multiplexers 381-404...AND gates 406-408...OR gates 411-418...Resistor 420...Bus signals (including signals 421-428) 4
30...Adder 440...Nonlinear/linear converter 441.442...ROM 445...Bus signal (including signals 446 to 458) 4
60...Attenuation instruction circuit 461-463.467...OR gate 464-4
66...AND gate 469...Signal 470...Attenuation circuit 47
1 to 474...2-bit multiplexer 475...
・Bus signal (including signals 476 to 48B) 500...
Full adder 510...First adder 511-514...Adder 516-528...Exclusive OR gate 530...Bus signal (including signals 531-544) 5
45...Signal 550...Second adder 55
1 to 554... Adder 556 to 569... Exclusive OR gate 571 to 583... OR gate 585... Bus signal (including signals 586 to 598) 6
10...-Hour storage circuits 611-614...Latch 616...Inverter 620...Bus signal (including signals 621-635) 6
50... Linear/nonlinear converter 652... Bus signal (including signals 653 to 659) 6
60... Demultiplex circuits 661A to 661C... P/S register 662...
Shift register 663...OR gate 664...AND gate 665...Inverters 668A to 668C...Signals 670A, 670B, 670C...Demultiplexer 671...Decoders 672 to 677... Inverter 679A, B, C ~ 684A, B, C... Signal 685
~690...OR gates 691-696...Signal 700...Broadcast circuit 701...OR gates 702-705...AND gates 711-715...Signal 720...Sound source Circuit 721... Multiplexer 722... Signal 725... S/S register 728... Signals 731-734... AND gates 736-739... Signal 800... CPU interface circuit 801... - Interrupt circuit 802...D flip-flop 803...NOR gate 804...Inverter 808...Signal 810
... Address decoding circuits 811 to 815 ... Decoder 816 ... Bus signals (including signals 817 to 820) 8
21... Bus signal (including signals 822 to 825) 82
6... Bus signal (including signals 827 to 833) 834
... Bus signal @ (including signals 835 to 843) 844.
...Bus signal (including signals 845 to 847) 848...
・Signal 850...4-bit latch circuit 851-857...D flip-flop 858...
Inverter 859... Signal 860... Bus signal (including signals 861 to 864) 865... Bus signal (
Including signals 866 to 869> 870... Bus signal (including signals 871 to 873) 875... Bus signal 880... Bus signal (including signals 881 to 884) 8
85... Bus signal (including signals 886 to 889) 89
0...Bus signal 900...3-bit latch circuits 901-909...D flip-flop 910...
Inverter 914...signal 915...bus signal (including signals 916-918) 920-922, 924
゜925.927... Bus signal 923... Bus signal (including signals 936 to 938) 9
26... Bus signal (including signals 931 to 933) 95
0...2-bit latch circuits 951-956...D flip-flop 957...
Inverter 958...signal 960-965...
Signal 920...bus signal (including signals 939 to 941) 9
27... Bus signal (including signals 942 to 944) 10
00... Timing circuit 1090... Frequency divider circuit 1091... Inverter 1096-1098... Signal 1100... Frame pulse circuit 1110.1111... Hexadecimal counter 1112.1
113...D flip-flop 1114...AND gates 1117-1119...Inverter 1120...Bus signal (including signals 1121-1124) 1125-1128...Signal 1150...Multi-frame pulse Circuit 1151.
1152... Hexadecimal counter 1153.1154...
- AND gates 1155 to 1160... Inverter 1170... Bus signal (including signals 1171 to 1175) 1176.1177... Signal 1200... 1st to 4th transmission timing circuit 1211.
...D flip-flop 1212.1213...AND gate 1221-1
226... Inverters 1231-1233... Signals 1241... 8-bit shift register 1242.
1243...D flip-flop 1244.1245
...NAND gate 1246-1247...AND gate 1248...OR gate 1251-1254...Inverter 1261-1269...Signal 1281.1282...D flip-flop 1283
．． 1284... Nando Gate 1291-1296.
...Inverters 1301-1304...Signals 1311-1313...AND gates 1316-1
318... Signal 1350... Reception timing circuit 1351... 8-bit shift register 1352~
1354...D flip-flop 1355-1359
...AND gates 1361-1363...Inverters 1371-1379...Signal 1400...First and second conference timing circuits 1411.
1412--Decoder 1413--NOR gate 1414.1415--NAND gate 1421-1
427...Inverter 1430...Bus signal (including signals 1431-1436) 1437-1439...Signals 1451-1454...D flip-flop 1455
．． 1456...Noah Gate 1458.1459...
- Inverter 1470... Bus signal (including signals 1471 to 1473) 1475... Bus signal @ (including signals 1476 to 1478) 1479 to 1482... Signal 87 to BO... Data information D... D information P...P information.

Claims (3)

[Claims] (1) A central office line communication means for connecting to at least one central office line, an extension interface means for sending signals to each terminal device, and a receiving means for receiving signals from each of the terminal devices. , an extension communication means for enabling communication between the respective terminal devices; an information transmitting/receiving means for transmitting and receiving control information for connecting to a destination; and a means for ORing signals from a signal source for simultaneous broadcasting. broadcasting means for receiving the output of the OR means and transmitting the output of the OR means to each designated terminal device to receive the broadcasting via the extension interface means; each frame of a plurality of frames included in the plurality of frames includes a start bit, a bit representing data information, and a bit representing parity information, and controlling at least one frame among the plurality of frames to connect to the destination. 1 above, including bits representing information.
including frame synchronization information for obtaining frame synchronization in at least one frame in one multiframe,
Downlink information from the extension interface means to each terminal device, including at least bits representing data information, bits representing parity information, and bits representing control information for connecting to the destination, is received from each terminal device. The first half of each frame contains one of the downlink information and the uplink information, and the second half contains the other information, so that the mutual downlink information and uplink information included in each frame are A guard time, which is a time longer than the sum of the propagation time of the signal from the extension interface means to the terminal device and the propagation time of the signal from the terminal device to the receiving means, is provided between the downlinks. The timing of transmitting information from the extension interface means to each of the terminal devices, the timing of receiving the upstream information from the terminal device to the receiving means, and the timing of transmitting data information from and to the central office line to the central office line. a timing for transmitting and receiving data by the telephone communication means; a timing for transmitting data information included in uplink information received by the reception means to the extension telephone communication means; and one of the central telephone communication means and the extension telephone communication means. a timing for outputting data information to be broadcast all at once to the simultaneous broadcasting means; and a timing for indicating to the information transmitting/receiving means the position of a bit representing control information for connecting to the destination included in the uplink and downlink information. a timing creation means for creating a timing information; and monitoring control information for connecting to the destination included in the uplink and downlink information to control communication between the office line and the terminal device or between the terminal devices. A central control means for transmitting a control signal to the central office line communication means, the extension communication means, the simultaneous broadcasting means, the information transmitting and receiving means, and the receiving means. broadcast trunk. (2) The broadcast trunk according to claim 1, wherein the receiving means includes a delay means for receiving the uplink information with a delay within the guard time. (3) The extension interface means transmits the downlink information using a signal of "1" or "0" by adding an odd numbered "1" and an even numbered "1" including the parity information. The broadcast trunk according to claim 1, further comprising code separating means for separating and outputting each code.