JPH01174095A - Key telephone system - Google Patents

Abstract

PURPOSE:To realize a telephone set with excellent economy by making a terminal equipment connectable without circuit modification even at a long distance as well as a short distance between a master control equipment and the terminal equipment even in a small sized system regardless of PCM processing. CONSTITUTION:Transmission lines 63A-63C interconnecting terminal equipments 70A-70C and a master controller 10 in 2-wire ping-pong transmission and transmitter-receivers 60A-60F sending a signal and receiving a signal from/to the transmission lines are provided between the master control equipments and the terminal equipments at both ends of the transmission lines, the reception circuit included to the master equipment is suitable for the 2-wire ping-pong transmission and copes with the transmission of a prescribed range and at a long distance. When the transmission line is long, no delay exists in the reception circuit and a signal is sent to an extension speech circuit, a trunk line speech circuit or a conference speech circuit and in case of a short distance, a reception signal is retarded for a prescribed time in the reception circuit and the reception signal is sent to the extension speech circuit, the trunk line speech circuit or the conference speech circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a button telephone device used for PCM (Pulse Code Modulation) communication. Specifically, the present invention aims to provide a button telephone device using a novel PCM that can arbitrarily connect terminal devices including telephones, data equipment, etc. between central office lines and terminal devices.

[Background Art] When transmitting and exchanging many communication signals and data signals, there are cases in which time division is generally used and cases in which space division is used.

In the case of time-division, as is well known, speech signals and the like are encoded into "019 or 1" and transmitted as digital signals over a single transmission line. Here, digital signal rate conversion and time division multiplexing are performed. In this time division multiplex transmission, the code arrangement and timing are determined in advance, and the receiving side separates the multiplexed call signals, rearranges the data order, etc., and then performs D/A conversion. You can now make calls.

In space-division communication channels, for example, the number of input and output lines corresponding to each terminal is exchanged by closing them with a cross point switch, and in this case, A/D conversion and D/A conversion are generally performed. It is transmitted as an analog signal without any conversion.

[Problems to be solved by the invention] In time division, PCM is used, and by increasing the bit rate, it is possible to multiplex as many communication channels as desired. , the cost per channel will go down. However, in order to perform transmission using digital codes, an A/D converter,
D/A converter.

Since a cog, a decoder, and a speed converter are required, there is a problem in that the cost becomes high in a small-scale system.

However, in space-division communication channels, the A/D converter, D/A converter, coder, decoder, and speed converter required for PCM transmission and exchange are not required in order to transmit analog signals as they are. As the number of lines increases, the number of cross point switches in the exchange increases in proportion to the square of the number of lines, resulting in higher costs.

In general, it has been difficult to handle digitally encoded signals in space-division communication channels. This is because there is a delay time (5 to 6 ns/m>) in the transmission line, and the phase between the transmission timing and the reception timing is shifted, so that it has not been possible to transmit and receive signals efficiently with a simple device.

[Means for Solving the Problems] The cost l- per line of a conventional PCM time-division communication path and a space-division communication path intersect when the number of lines is about 100. That is, in systems with 100 lines or less of terminals, it is cheap to use the spatial type, and in systems with 100 lines or more, it is cheap and effective to use the time division type with PCM.

However, with recent advances in LSI (Large-Scale Integrated Circuit) technology, PCM-based time-division communication channels have become smaller and more economical, and are more compatible with data equipment, making them less effective as a comprehensive system. dominance has increased.

The present invention has been developed in view of this situation, and it is an object of the present invention to provide a system which is excellent in both function and economy even in a small scale system.

To this end, we use PCM using digital codes that are resistant to noise and easy to process, and we have developed a main controller that controls each of the multiple terminal devices, and a two-wire ping-pong transmission to connect each terminal device to the main controller. A transmission line, and a transmitter/receiver for transmitting signals to the transmission line and receiving signals from the transmission line between both ends of this transmission line and the terminal equipment and the main control unit, respectively, and a transmitter/receiver that is included in the main unit. The receiver circuit is compatible with two-wire ping-pong transmission, and can handle transmission lines within a certain range (for example, within 200 m) and even longer transmission lines (for example, within 400 m, or even 600 m or more). I took it as a thing.

In addition to the receiving circuit, this main control device includes a central office line calling circuit, an extension calling circuit, a conference calling circuit, a broadcasting circuit, and a circuit for controlling these circuits, in order to enhance the overall functionality of this system. A CPU interface circuit for interfacing with a CPU (central control unit) and a timing circuit for generating timing signals necessary for each circuit included in this main device were provided.

[Function] If the transmission path is long (for example, within 400 m),
There is no delay in the receiving circuit, and the signal is sent to the extension telephone circuit, central office telephone circuit, or conference telephone circuit, and in the case of a short distance (for example, within 200 m), the signal is sent within the receiving circuit for a predetermined time (
After delaying the received signal (transmission time for 200 m of transmission line), the received signal is transmitted to the extension line communication circuit, office line communication circuit, or conference communication circuit.

Therefore, it has become possible to connect to terminal equipment using short-distance and long-distance transmission lines.

In this way, although it is a small-scale button telephone device, it has become possible to create a device that is PCM-based and has many functions that can be used with long-distance transmission lines.

[Example] The principle of the button telephone device according to the present invention will be explained with reference to FIG. 1A, and the waveforms at each part thereof will be explained with reference to timing charts of FIGS. 1B, 1C, 1D, and 1E.

In FIG. 1A, reference numeral 10 denotes a main control device that implements the present invention, and this main control device 10 operates in synchronization with a clock 51 from a clock generator 50.
20 and address bus signals 21, 22, 23, 808 and address bus signals 25. It operates by data bus signal 35. The main controller 10 has a signal 61△ (61B, 61C).
and signal 108A (108B, 108C) and signal 109
A (1098, 109C) and transmitter/receiver 60A (6
08, 60C), transmission line 63A (63B, 63C), transceiver 60D (60E, 60F), and signal 61D (
61E, 61 F>, signals 71A (71B, 71C), and signals 72A (72B, 72C), the terminal device 7
0A (70B, 70C) is connected. moreover,
This main controller 10 receives a signal 14A via a station line 12A (12B) and a station line interface 11A (11B).
(Connected by 14B> and signal 15A (15B>. Central line ink)
The arrival at the station is detected by the CPU 20 by the signal 16A (16B>) between the station line interface 1 and the LJ 20.
1A (11B>) provides information for sending a dial signal.

With such a configuration, the terminal devices 70A, 70B, 70
It is possible to communicate in any combination between terminal devices 70A (70B, 70C) and central office lines 12A (12B>).

FIGS. 1B (a) and (b) show the signal 108A between the main controller 10 and the transceiver 60A.

109A and the signal 61A are shown, and (C) shows the signal on the transmission line 63A. Signals 108A and 109A of (a> are outputted from the main controller 10 in the first half of one frame (125tIs>), and then signal 61A of (b) is outputted from the transmitter/receiver t160A side in the second half of one frame. (C ) on the transmission line 63A are (a>,
It shows how the signal shown in (b) is transmitted.

Figures 1C (a> and (b) show the contents of signals 108A, 109A and signal @61A shown in Figure 1B, where ST is the start bit and F is the frame synchronization. 87 to BO are voice information (data information), D is control information for connecting to the destination (hereinafter referred to as D information), P is information for connecting to the destination (hereinafter referred to as D information),
represents parity information (hereinafter referred to as P information) for maintaining DC balance in the transmission line 63A.

FIG. 1D shows uplink and downlink information of the transmission line 63A and their timing signals, and (a) shows the signal 10.
8A, 109A are shown, the signal 61A is shown in (d), and the main controller 10 is shown in (b), (C) and (e).
Internally generated signals 1268.1269. and 137
7 is shown.

Here, the signal 1268 represents the transmission period of the audio information 87 to BO, the signal 1269 in (C) represents the transmission timing of the audio information 87 to 80 shown in (a), and the signal 1269 in (e) represents the transmission timing of the audio information 87 to 80 shown in (a). The signal 1377 is the signal 5S shown in (d>
61A represents the reception timing signal of audio information 87-80.

Signals 108A and 109A of (a) and signal Q61A of (d>
A guard time T1 is provided between the two. This is the two signals 10 of (a) of a convenient type to be transmitted from the monarchy m device 10 side by 100% AMI signals.
A combination of 8A and 109A transmits a 100% AM ■ signal through the transmission path 63A via the transmitter/receiver ti60A, and transmits the signal 61D to the terminal device 70A via the transmitter/receiver 1ff60D.
The terminal device 70A receives the audio information 87 to BO excluding the start bit ST and frame bit F, control information, and parity information P.
The transmitter/receiver 60D and the transmission line 6 are connected by the signals e71A and 72A.
3A, when received by the main controller 10 as the signal 61A in FIG. 1D (d) via the transceiver 60A, (a)
This is the time provided so that the trailing edges of the signals 108A and 109A shown in (d>) do not collide with the leading edge of the signal 61A shown in (d>).

FIG. 1E explains the influence of the length of the transmission path 63Δ on uplink and downlink information, and corresponds to FIG. 1D. In FIG. 1E, signals 108A and 109A in (a)
is sent in the first half of the n-th frame, and as a result, the terminal device 70
The signal 61A (d>) sent back from the A side is delayed on the transmission path 63A and received in the nth frame,
In addition to the guard time T1, this signal 61A is recovered and the signal 108A of (a) in the (n+4)th frame.

The point is that a guard time T2 provided to prevent collision with the leading edge of the 109A is required, and the start time of the 2-bit configuration is from the straight 1 change of this guard time T2.
An addition time T3 for 2 bits is provided up to the middle of bit ST, which is used when a conference call is required. In this way, even on the short-distance or long-distance transmission line 63A, from the terminal device 70A to the main control device 10
the upstream signal in the direction and the terminal device 7 from the main control device 10 side.
Downlink signals in the 0A direction do not collide.

FIG. 1F shows a waveform diagram for explaining the reason why the length of the transmission line 63A is limited, and (a) shows
The case where the length of the transmission line 63A is 2 meters is shown in (b), and the case where the length is also zero meters is shown in (c).
>, audio information 87 to BO constituting the signal 61A in (b)
A signal 1376 is shown having a period equal to the period of each bit of . In contrast to the signal Q61A in (b), the signal 61A in (a) causes a delay time Td of 2×2 meters in the transmission path 63A, but this delay time Td is 1
Must be within bits. Otherwise, it would be impossible to distinguish it from the next bit. In the present invention, the delay time Td (0 to 778 bits) is set with a margin of 1/8 bit, for example.

If the bit rate is required, for example 256 KbDS, then 2 will be about 200 meters.

FIG. 1G shows the principle of connecting the button telephone device according to the invention to a central office line.

The terminal devices 70A, 70B, and 70C are telephones and other data devices, and these terminal devices are connected to the central office line communication circuit 25.
It is connected to the office line 12A via the OA and office line interface 11A. This office line communication circuit 250A includes the office line 1
The signal M15A is sent to the S/S register 26 from the 2A side via the office line interface IIA in the latter half of one frame.
The signal 268A is taken into the OA, and in the first half of the next frame, the signal 251A is sent from the demultiplexer 270Δ to one of the terminal devices 70A to 70C.
, 252A, or 253A.

From the terminal devices 70A to 70C side, for example, the terminal device 7
The signal 162A from 0A is selected by the multiplexer 28OA, is taken into the S/S register 260B that performs serial input and serial output in the second half of one frame, and is input to the S/S register 260B in the first half of the next frame.
A signal 268B is output from 0B, and sent to the peripheral line 12A via the office line interface 11A. In this way, communication between the office line 12A and the terminal devices 70A to 70C is performed.

FIG. 1H shows a principle diagram of an extension trunk, which allows communication between terminal devices in the key telephone device according to the invention without going through a central office line.

The signal 162A transmitted from the terminal device 70A is applied to the multiplexers 21OA and 210B, but is selected by the multiplexer 21OA by a control signal not shown here, and the selected signal 21
8A is S/S register 2 for serial manual output
2OA in the second half of one frame and output as a signal 225A in the first half of the next frame, which is applied to the demultiplexer 227Δ, and is output as a signal 23A by a control signal not shown here.
6A and applied to the terminal device 70B.

The transmission signal 162B from the terminal device 70B is selected by a control signal (not shown) in the multiplexer 210B, outputs the signal 218B, and sends the signal 218B to the S/S register 220.
B in the second half of one frame and output as a signal 225B in the first half of the next frame, which is applied to the demultiplexer 227B, selected by a control signal (not shown), and output as a signal 235B, and sent to the terminal. The voltage is applied to the device 70A.

FIG. 11 shows a principle diagram of a conference call trunk that allows simultaneous communication between two or more terminal devices.

Here, a conference call between terminal devices 70A, 70B, and 700 is illustrated, and a signal 61A (B, C) output from the terminal device 70Δ (B, C) is a conference call that enables the conference call. Multiplex circuit 360 within circuit 350
There, in the latter half of one frame, the respective signals are accumulated, and are sent to the adder 430 as a bus signal 420 from the multiplex circuit 360 in a time-sharing manner during the guard time T2 explained in FIG. 1E. Apply.

In this itching device 430, the signals from each terminal device 70A (B, C) sent by the bus signal 420 are added, and the addition result is output as a bus signal 652 and applied to the demultiplexer circuit 660. ing.

In the demultiplex circuit 660, the terminal device 70A (
B, C), the signal 693 (694, 695>) is output in the first half of the direct frame at guard time T2.Here, the signal 693 is output from the terminal device 70B,
The contents of signals 61B and 61G output from 70C are added. Similarly, signal 694 is
1A and 61C, and signal 695 represents the shoreline result of signals 61A and 61B.

In this way, a conference call is possible.

Figure 1J shows the principle of a broadcast trunk for simultaneously transmitting the same information to all or a designated part of a large number of terminal devices connected to the key telephone device related to the present invention. A diagram is shown.

Here, each signal 239 is transmitted from the terminal devices 70D, 70E or the office line via the office line interface 11Δ.
One of A, 239B, and 257A is broadcast circuit 7
00 is applied to the OR gate 701 and the signal 7
11, by simultaneously applying control signals 871, 872, 873, signals @712.713.714. as terminal device 7
It is output to 0A70B and 70C. In this way-
Simultaneous broadcasting becomes possible. Here, or gate 70
Q239A, 239B and 257 input to 1
A sends one signal to an OR gate 701 by a CPU (central control unit) 20, not shown here.
When input to , input of other signals is prohibited.

FIG. 2A shows a conceptual diagram of the structure of the main controller 10 including various circuits for realizing the various functions explained in FIGS. 18 to 1J. 10 is omitted.

100A to 100D are necessarily extension interface circuits.
The signals 108A, 109A to 108D, 109D can be sent directly to the terminal device 70 or via the transmission line 6 to the transceiver 60.
3 (see FIG. 1A).

150A to 150D are receiving circuits, which receive signals 61A to 61D from the terminal device 70 side.

170 is a D information transmitting/receiving circuit for transmitting and receiving dial information and information for controlling the terminal; Information is exchanged.

Reference numeral 200 denotes an extension call circuit, which performs the function of the extension call explained with reference to FIG. 1H.

Reference numerals 25OA and 250B are office line communication circuits, which perform the office line communication function explained with reference to FIG. 1G.

Reference numeral 350 denotes a conference call circuit, which performs the conference call function described with reference to FIG.

Reference numeral 700 denotes a broadcast circuit, which performs the broadcast function described with reference to FIG. 1J.

720 is a sound source circuit to which various signals 66 to 6 applied from outside the main controller 10 are applied, and these signals are selectively transmitted to the extension interface circuits 100A to 100A.
00D to the terminal device 70, and these various signals 66 to 69 include background music (BGM), hold music, doorbell chime sound, etc. .

800 is a CPU interface circuit, which receives and receives address bus signals @25.800 between the CPU 20 (not shown) and various circuits included in the main control device 10.
Data bus communication @35. Reset signal 21. Read signal 22. A write signal 23 and a signal 808 for interrupting the CPU 20 are interfaced.

A timing circuit 1000 generates various timing signals required inside the main control device 10 from a clock 51 applied from the outside and applies them to various circuits inside the main control device 10.

Reference numeral 358 is a μ/A switching signal applied from the outside, which is used to select the μ law or A law used for addition processing within the conference call circuit 350.

Signals 14A, 15A (14B, 15B> is the central line 12A
(See Figure 1A), signal 15A is a communication signal between
(15B> is directly input to the office line communication circuit 250Δ (250B), and the transmission signal of the office line communication circuit 250A (250B> or the conference call circuit 350 is input to the OR circuit 13A (250B)).
13B> to the central office line as a signal 14A (14B>).

In the case of an extension call, signals 61A to 61D sent from the terminal device 70 are sent to the receiving circuits 150A to 150D, the extension call circuit 200, and the extension interface circuits 100A to 100A.
Signals 108A, 109A to 108D via 100D,
109D to other terminal devices 70.

In the case of a local line call, the signals 61A to 61D sent from the terminal device 70 are sent to the local line side via the receiving circuits 150A to 150D, the local line communication circuit 25OA, and the OR circuits 13A and 13B. The signals 15A and 15B are
Signals 108A, 109 are sent via the office line communication circuits 25OA, 250B and extension line interface circuits 100△ to 100D.
It is sent to the terminal device 70 as A to 108D and 109D.

In the case of a conference call, signals 61A to 61D sent from the terminal device 70 are sent to the receiving circuits 150A to 150D, the conference call circuit 350, and the OR circuit 13A.

13B to the office line side, and further from the conference call circuit 350 to the extension interface circuits 100A to 100D.
Signals 108A, 109A-108D, 109D via
It is sent to other terminal devices 70 as a. Further, the signal 15A from the office line side is transmitted to the signal 108A,
It is sent to each terminal device 70 as 109A to 108D and 109D.

In the case of simultaneous broadcasting, the signals sent from the simultaneous broadcasting circuit 700 are sent to the extension interface circuits 100A to 100D.
via signals 10.8A, 109A-108D, 10
9D, and is sent to each terminal device 70. - The signals to be sent from the broadcast circuit 700 are the signals 61A to 61D output from the terminal device 70 to the receiving circuits 150A to 150.
Broadcasting circuit 700 via D and extension call circuit 200
In some cases, the signals are applied from the office line side as signals 15A and 15B via the office line communication circuits 25OA and 250B.

When the terminal device 70 sends out dial information instructing the destination, the receiving circuits 150A to 150A receive messages g61A to 61D.
150D, and is transmitted to the D information transmitting/receiving circuit (information transmitting/receiving means) 170. This dial information is
D information is read by the CPU 20 from the transmitter/receiver circuit 170 via the data bus signal 35 . When there is an arrival from the central office line, the central office line interfaces 11A and 11B (1st A
The CPU 20 reads this arrival from the station using signals 16A and 16B. There, the destination is transmitted to the D information transmitting/receiving circuit 170 by the data bus signal 35, and from there the destination is transmitted to the extension interface 10 connected to the destination terminal device 70.
The incoming call is notified to one or more of 0A to 100D.

FIG. 2B shows a terminal device 7 connected to the main control device 10.
0, and FIG. 2B (a) shows an example of the telephone 10.
A codec 103 converts the transmission and reception of 5 to a PCM signal, and a codec 103 that converts the transmission and reception of 5 to a PCM signal, and a signal 1
08A and 109A are applied, and a signal 61A is output from the PCM output connected to the pull-up resistor 104.

In FIG. 2B (b), a circuit is shown in which NOR gate 102 is replaced by a circuit including a transistor 106, the function of which is the same as that shown in (a).

FIG. 3A shows an extension interface circuit, e.g.
A, and FIG. 3B shows a timing chart of the waveforms of each part thereof.

The inputs of the OR gate 101 include a signal 712 from the broadcast circuit 700, a signal 736 from the sound source circuit 720, and a signal 179A (3B) which is the D information (Fig. 1C) from the D information transmitting/receiving circuit 170. (d)), the call @ 693 from the conference call circuit 350, the call @ 235 A and 235B from the extension call circuit 200, and the office line call circuit 25
Signal 251A from OA, 250B (Figure 313 (C)
), 251B, and a timing signal M1231.1317 from the timing circuit 1000 (FIG. 3B(a)).

(b>) is applied, and a signal 107 shown in FIG. 3B (e) is output. In this figure 3B, the CPU
20 and sends a signal 251 from the office line communication circuit 250Δ.
A case of a central office line call in which A is received at the OR gate 101 is shown.

The signal 1231 in Fig. 3B (a) is the start pill S.
(Fig. 1C), and the signal 1317 in (b)
represents the F bit (Fig. 1C), and the signal 251A in (C) represents the telephone call signal from the central office line. By ORing these signals with the D information in (d), (e) A signal 107 shown in FIG.

This signal @107 is applied to the code separation circuit 110Δ. The code separation circuit 110A is applied with a signal 1304, which is the P information of (f>) in FIG.
A signal 108A representing "1" and a signal 109A representing an even-numbered "1" are separated and output.

Signals 108A and 109A in (h) and (i) represent the contents of signal 107 in (e) and signal 1304 in (f). The “1” appearing in (h) is delayed by 1 bit in the signal 1098 of (q>), and then the signal @1 of (h)
Send as “1” of 08A, signal 107 of (e)
When the 1st "1" appears, the signal 109A of (i) is set to "1" in the same way, and the signal 109A of (e) is set to "1" in the same way, and the odd numbered "'1" of the signal 107 of (e) is set to (h). The signal 108A of (i) is set to "1" for even numbered "1", and the signal 10 of (h) is set to "1".
When the sum of the number of "1"s in 8A and signal 109A of (i) becomes an odd number, 1°' of signal 1304, which is required by P information (parity information) of (f>), is output in signal 109A of (i). As a result, (h) in one frame.

The numbers of "1" appearing in each of the signals 108A and 109A in (i) are equal, and the subsequent transmission line 63A
In this case, good DC balance can be obtained.

FIG. 3C is a detailed circuit diagram of the code separation circuit 110A, and the waveforms of each part are shown in the timing chart of FIG. 3D.

The signal Q107 shown in FIG. It is applied to one input terminal, and the output signal 133 shown in (e) is applied to the data terminal of the D flip-flop 111. One frame is connected to the clock terminal of this D flip-flop 111 at 32
A signal 1098 shown in (a) having equally divided periods is applied.

The signal 139 representing the output Q of the D flip-flop 111 (f> is initially “Ott”, and when “1” of the signal 107 in (b) is applied, the signal 139 at the odd number becomes “1′°”). Indicates "Off" at the even numbered number (f)
It outputs a signal 139.

Here, the signal 1304 shown in (C) is parity information that is set to ``1'' when ``1 par'' of the signal 107 indicating the timing of the downlink signal in (b) indicates an odd number in one frame. , which is applied to the other input of NOR gate 117.

Further, the signal 139 (f) is applied to the other terminal of the exclusive OR gate 120.

Signal 1304 (C), which is parity information, is applied to one input terminal of NAND gate 115, and signal 139 (f>) is applied to the other terminal, which outputs signal 134 (g). The (g> signal 134 indicates "OII" when the (C) signal 1304, which is parity information, indicates 1111+, and otherwise indicates 1.

Upon receiving the signal 131 and the signal 134 (q), the NAND gate 116 outputs the signal 135 (il), which is connected to D.
It is applied to the data terminal of flip-flop 112.

The clock terminal of this D flip-flop 112 has (
The signal 1098 of a) is applied. The signal 136 of (i) is (%) at its not-Q output. Here, (
The signal 136 in i) shows the inverted output obtained by adding the signal 1304 in FIG. 13B to the signal 107 in FIG.

(D flip-flop 11 inverting the signal 139 of f>
1 output knot Q signal Q140 and (i) signal 136
The NOR gate 118 to which is applied outputs a signal 137 shown in (j>. The output of the NOR gate 118, the signal 137 at (j>
#119 is shown when there is an odd number of 1″. This (
j> signal 137 is applied to the data terminal of the D flip-flop 113. Inverter 122 on clock terminal
The output Q of the D flip-flop 113 to which the signal g1098 of (a) is applied via the signal 108 shown in (ri)
A is obtained. This signal 108A is the signal 10 in (b).
When 7 has an odd number of 1s, it shows 1.

The NOR gate 119 to which the signal 139 of <f> and the signal 136 of (i) are applied outputs the signal 138 of (k>,
This is applied to the data terminal of the D flip-flop 114. Here, the signal 138 in (k) shows 111 II when 111 II is an even number by adding "1" of the signal 1304 in (C) to the signal 107 in (b).

The clock terminal of this flip-flop 114 has (a
) is applied via the inverter 122, and its output Q has a signal 109A of (m>). When I did this, it said, “It shows 1pa.

(The case where the sum of ll 1 II of belief g 107 shown in b> is an odd number is illustrated in Fig. 3D, but “1
'' is an even number, it is pariday information (C
) signal 1304 indicates “OIT”.

FIG. 4A shows a specific circuit of, for example, 150Δ among the receiving circuits 150A to 150D, and FIG. 4B shows the waveforms of each part as a timing diagram.

The signal 61A shown in FIG. 4B (a) or (b) from the terminal device 70 is received via the inverter 155 to the data terminal of the D flip-flop 151, and its clock terminal is connected to a clock terminal for receiving the upstream signal. A signal 1376 (C) having a period obtained by equally dividing the frame into 32 is applied, and a signal 161 shown in (d) is obtained at its output Q.

If the transmission distance from the signal 161 and the receiving circuit 150Δ of (d) to the terminal device 70 is, for example, 200 meters to 200 meters, the AND gate 152 indicates "OIt, for example, 150 to 350 meters." In the case of 2, a signal 861 indicating 1'' is applied. and gate 15
3, the signal 861 and the signal 61△ are connected to the inverter 155.
is applied via. both and goo to 152,
The output of 153 is applied to OR gate 154 to output signal 162A.

FIG. 4B (a) shows the case where the transmission distance is, for example, 0 meters, (b) shows the case where ff1=200 meters, and (e) shows the case where /2=150 meters. )
Signal 61A is shown for =350 meters.

When the transmission path length is zero meters, as shown in (a), the beginning of data information 87 to BO is at time t1.
It is applied to the receiving circuit 150A.

Transmission path length! ! , 1=200 meters, then (b
), the beginning of data information 87 to BO is at time t.
3 is applied to the receiving circuit 15OA. Similarly, when ri=150 meters, the voltage is applied to the receiving circuit 150A at time t2 as shown in (e), and when si3=350 meters, the voltage is applied to the receiving circuit 150A at time ↑5 as shown in (f). It shows that it will be done.

In the cases of (a) and (b), the signal 861 is "O", and the signal 1376 of (C) indicates time ta.

t7. The signal 61A is sampled and the data is taken into the D flip-flop 151, and the output signal 161 (d, ) is outputted as the signal 162A via the AND gate 152 and the OR gate 154. .

(In the case of e> and (f), the signal 861 is "1"
At time 16.18, the signal 61A sampled in another circuit is the signal 1377 (g), which is not shown in FIG. 4A for convenience of explanation.
55. It is outputted as a signal 162Δ via an AND gate 153 and an OR gate 154.

The output in cases (e) and (f) is delayed by the half period of signal 1376 of (C>) than in cases (a> and (b). In this way, various transmission lengths can be adjusted. We are trying to accommodate.

FIG. 5A shows the circuit configuration of the D information transmitting/receiving circuit 170, and FIG. 5B shows a timing chart showing waveforms of each part thereof.

The D information transmitting/receiving circuit 170 is a circuit for transmitting/receiving dial information and information for controlling the terminal device 70, and FIG. 5A shows four sets of D information transmitting/receiving circuits 170A.
~170D are exemplified, among which, for example, 170A
includes a D information transmitting circuit 171 and a D information receiving circuit 180.

The D information transmitting circuit 171 is applied with a signal 131B that determines the timing of transmitting the D information in FIG. 5B(a), and
Upon receiving the write signal 822 for capturing the data bus signal 35 from the PU 20, the captured signal (
Timing of signal 1318 in a), signal 179 in (b)
A is sent to the extension interface circuit 100A.

The D information receiving circuit 180 is applied with the signal 1379 (d) that determines the timing of receiving the D information in FIG. 5B.
The receiving circuit 150A takes in the signal 162A of (C>) and outputs it to the data bus signal 35 to the CPU 20 at the timing of the signal 817.

FIG. 5C shows a specific circuit diagram of the D information transmitting circuit 171.

Reference numeral 172 is a P/S register, which takes in signals 36 to 43 applied in parallel to input terminals A to H when the signal 822 applied to shift/load terminal S/L is "O".
At "'1", inverter 17 is connected to the clock terminal.
4 through signals g43, 42 . . . 36 as a serial signal, and is outputted as a signal 179A (FIG. 5B (b)) via an AND gate 173 to which signal 131B is applied.

FIG. 5D shows a specific circuit diagram of the D information receiving circuit 180.

The signal g162A from the receiving circuit 150A is applied to the A terminal of the 8-bit shift register 181, and every time the signal g1379 for taking in data is applied to the clock terminal, the data of the signal 162A is taken in. The signals are sequentially shifted and output in parallel to outputs OA- and -QH.

These parallel outputs QΔ to QH are input in parallel to the input terminals A-H of the 3-state buffer 182, and the signal 817, which is a read signal from the CPU 20 and applied to the control terminals G1 and G2, indicates "0". When the signals applied to the input terminals A-H are output to the output terminals YA-Y, respectively
The data bus signal 35 is output to the CPU 20 as signals 36 to 43 forming the data bus signal 35.

FIG. 6A shows a circuit configuration diagram of the extension call circuit 200, in which signals 16 from the receiving circuits 150A to 150D are shown.
2Δ to 162D, signals 66 to 69 indicating sound source information,
These signals 162A to 162D and 66 to 69 are selected by bus signal 885, and multiplexer 21OA outputs signal @218A to S/S register 22OA.

The S/S register 22OA receives the serial signal @2.
18A, received at the timing of signal 1377,
It is sent out as a signal 225A at the timing of the signal 1269, and this sending continues while the signal 1268 is at 1.

A signal 225A and a bus signal 92 for instructing the destination.
3, the demultiplexer 227A receives the signal 23
5A to 238A, respectively, as extension interface circuit 1.
Broadcasting signal 239A to 00A to 100D from broadcast circuit 70
Send to 0.

The multiplex clearer 21OB, the S/S register 220B, and the demultiplexer 227B each have a multiplexer clearer 21OB and a demultiplexer 227B.
210△, S/S register 22OA.

It corresponds to the demultiplexer 227A and operates in the same way.

FIG. 6B shows a specific circuit diagram of the multiplexer 21OA. 211 is an 8-bit multiplexer, 2
12 is a 4-bit multiplexer, and the signal 16 applied to data terminals D1 to D7 of 211 and Do of 212 is a 4-bit multiplexer.
2A ~ 162D, 66 ~ 69, selection letter @ 886 ~
889 is the select terminal A of the 8-bit multiplexer.
,B.

C, strobe terminal S, and 4-bit multiplexer 2
12 select terminals A, B, and strobe terminal S are applied via an inverter 214, and each selected output signal is applied to their Yea terminals 1q, and is output as a signal 218A via an OR gate 213 to S/S. It is output to register 22OA. The selection signals 886 to 889 are all “O”.
+t, the grounded data terminal Do of the 8-bit multiplexer 211 is selected, and a silent signal is output from the Y terminal via the OR gate 213 as the signal 218Δ. Data terminals D]-D3 of 4-bit multiplexer 212 are never selected.

FIG. 6C shows a specific circuit diagram of the S/S register 220Δ, and FIG. 6D shows a timing diagram showing the waveforms of each part.
A chart is shown.

Here, FIG. 6D (a) from multiplexer 21OA
The 8-pin shift register 221 to which the signal 218A shown in FIG.
77 and a signal 1269 for transmission timing are received via 223 to ORGOO 1, and at the time of reception, the signal 218A is serially inputted and latched, and the signal Q126 of (Cl>
During the period of ii 1 TJ of the signal 1268 of (f>), the signal Q225A of (h) is outputted via the AND gate 222. Here, the 8-bit shift register 221 output terminals OA, QB
---・-QH is (C), (d), <e) (D To explain from example 2, OA and QB are shifted one bit at a time, and from the output QH in (e) , data information 87 to O (B is omitted in the drawing) are output sequentially.

Signal 1377 shown in Figure 6D (b), (f), (Q)
．． 1268.1269 is (e), (b) in Figure 1E,
6C, and as is clear from these figures, the frame in FIG. 6D is displayed with a delay of half a frame.

A circuit diagram of demultiplexer 227A is shown in FIG. 6E. Select signals 936 to 938 to select terminal A
-C, the 3-power 8-output decoder 228 receives the signal 225 at the enable terminal GA, and its output terminal YO-Y
7, signals 235A to 239A are obtained from Y1 to Y5 via inverters 229 to 233. Here, when all of the selection signals 936 to 938 indicate "Ol?", no output is made in order to select the output terminal YO.

FIG. 6F is a circuit configuration diagram showing another implementation of the extension call circuit 200, and the difference from that shown in FIG. 6A is that transmission control circuits 24OA and 240B are added. Everything else remains the same.

Rather than applying the signal 225A from the S/S register 22OA directly to the demultiplexer 227, the signal 225A is
It is either allowed to pass through or prohibited from passing through. This has the advantage that the hierarchical structure of the software in the CPU 20 can be easily designed by separating the selection of the destination input to the demultiplexer 227A from the signal transmission.

A specific circuit of this output control circuit 24OA is shown in FIG. 6G, in which a control signal 964 is applied via the inverter 242, and a signal 225Δ is directly applied to the AND gate 241, so that the signal 964 becomes "0". Signal 2 which is output when
I am getting 48A. The operation of the sending control circuit 240B is also 24
The operation is similar to that of OA.

FIG. 7A shows the circuit configuration of two sets of office line communication circuits 25OA and 250B, and shows a case where an incoming call from the office line is transferred again to another office line.

The signal 15Δ from the central office line side is received by the S/S register 260A, outputting the signal g268A, which is applied to the demultiplexer υ27OA, and the signal 256A is output.
The signal 288B is applied to the multiplexer 28OB of the office line communication circuit 250B, and the signal 288B is outputted through it.
Signal 268D is output to the central office line via register 260D.

Similarly, the signal 15B from the other office line side is received by the S/S register 260C, outputting the signal 268C, which is applied to the demultiplexer 270B, and the signal 256
B is outputted and applied to the multiplexer 28OA of the office line communication circuit 25OA, through which the signal 288A is outputted, and the signal 268B is outputted through the S/S register 260B.
is output to the central office line side.

Here, the signal 1377 is ``S/S register 260A~
This is a reception timing signal applied to 260D,
Signal 1269 is also a signal for transmission timing,
Similarly, signal 1268 is a timing signal that indicates a sending period when it is "1". Bus signal 926 (925)
is a bus signal for instructing the destination, and 251A~
254△ (251B to 254B) is data information (87 to BO) to the extension interface circuits 100A to 100D.
is sent to each destination.

The signal 257A (257B>) sends data information (audio information) to the -simultaneous broadcast circuit 7OO.

Signal 255A (255B> is multiplexer 280△
(applied to 280B>. 162A to 162D are signals from receiving circuits 150A to 150D, and signals 66 to
69 indicates sound source information, and these signals 162
Bus signal e880 for selecting A-D, 66-69 (
875) and the signal 288A (288B>
is output to the S/S register 260B (260D>).

FIG. 7B shows a specific circuit diagram of the multiplexer 28OA. 281 is an 8-bit multiplexer,
282 is a 4-bit multiplexer, and signals 162A to 162D, 66 to 69.255A, 25 applied to data terminals D1 to D7 of 281 and Do to D3 of 282
6B, selection signals 881 to 884, select terminals A, B, and C of the 8-bit multiplexer, strobe terminal S, and select terminal A of the 4-bit multiplexer.
B and S1 lobe terminals S are applied through an inverter 284 to obtain each selected output signal at their Y terminals and are applied to the S/B and S1 lobe terminals as signal 288A through an OR gate 283.
It is output to the S register 260B. Selection signal 88
When 1 to 884 are all "'O'', the 8-bit
The grounded data terminal Do of the multiplexer is selected, and a silence signal is output from the Y terminal via OR gate 283 as signal 288A. Data terminal D3 of 4-bit multiplexer 282 is never selected.

FIG. 7C shows a circuit diagram of demultiplexer 27OA. Selection signal 931 included in bus signal 926
~933 to select terminal A-C, enable terminal GA
The decoder 271 with three outputs and eight outputs which receives the signal 268 outputs the signals 251 A to 25 from the output terminals YO to Y7 from Y1 to Y7 through the inverters 272 to 278.
7Awo! There is FT. Here, selection signals 931 to 933
When all of them indicate "011", no output is made in order to select the output terminal YO.

FIG. 7D shows another embodiment of the office line communication circuit 25OA or 250B, and the difference from the office line communication circuit 25OA shown in FIG. 7A is that a transmission switching circuit 290 is added. , a multiplexer 310 that is different from multiplexer 280 is used, so this difference will be explained.

The circuit shown in FIG. 7D is suitable for the transfer operation in the central office line explained in FIG. 7A. S/S register 26
OA (260B> has its input signal, signal 15
A (328) is captured in the second half of one frame as shown in (d> in Figure 1E), and sent out in the first half of the next frame as shown in (a) in Figure 1E. For wire transfer, signal 255A from demultiplexer 270Δ is immediately applied to multiplexer 310, and its output signal 328 is applied to S/S register 260B, but at the time of the send timing, FIG. 1E. Because the signals 1268 and 1269 in (b) and (c) are applied, the S/S
Since the signal 328 cannot be taken into the register 260B, the S/S register is bypassed and the OR circuit 13A, 1 is sent as the signal 298 via the transmission switching circuit 290.
It is sent to the central office line via 3B. S/S register 26
0B is bypassed and the signal 328 is sent to the transmission switching circuit 290.
The signal 329 from the multiplexer 310 determines whether or not to output the signal 298 from the multiplexer 310 .

FIG. 7E shows a specific circuit diagram of multiplexer 310. 311 is an 8-bit multiplexer, 3
12 is a 4-bit multiplexer, and signals 162A to 162D, 66 to 69.255A, 256 applied to data terminals D1 to D7 of 311 and Do-D2 of 312
B, selection signals 881 to 884 are connected to the select terminals A, B, C, and strobe terminal S of the 8-bit multiplexer, and inverters are connected to the select terminals A, B, and strobe terminal S of the 4-bit multiplexer 312. 317 to obtain the respective selected output signals at their Y terminals and output them as a signal 328 via the OR gate 315 to the S/S register 260B and the output switching circuit 290.

When the selection signals 881 to 884 are all 011, the grounded data terminal Do of the 8-bit multiplexer 311 is selected, and the data terminal is connected from the Y terminal to the OR gate 315.
A silence signal is output as signal 328 via . 4
Data terminal D3 of bit multiplexer 312 is never selected. The selection signals 881 to 884 are
It is applied via inverters 318-321 or directly to AND gates 313 and 314, and their outputs are ORed by OR gate 316 to output signal 329. Here, select signals 881-884 or signal 2.
When 55A or 256B is selected, the signal 329 is set to "1" in both cases.

In other cases, it becomes "O".

FIG. 7F(a) shows a specific circuit of the transmission switching circuit 290 of FIG. 7D.

A signal 268B output from the S/S register 260B,
A control signal @329 is applied to the AND signals 1 to 291 via an inverter 294, and its output is applied to an OR gate 293. AND GO 1- with signals 328 and 329 from multiplexer 310 applied.
The output of 292 is applied to an OR circuit 293, and the output of signal 29
8 is output. The relationship between the signal 329 and the signal 298 is as shown in FIG. 7F (b), and when the signal 329 is "1", the signal 328 is
When the signal 329 is O'', the signal 26 is output.
8B is output as signal 298.

FIG. 7G is a circuit configuration diagram showing another embodiment of the office line communication circuit 250Δ of FIG. 7D, and the difference from that shown in FIG. 7D is a transmission control circuit 24OA.

240B is added, and the rest is the same.

Rather than applying the signal 268Δ from the S/S register 260Δ directly to the demultiplexer 27OA, the signal 248Δ is applied by the control signal 96O in the transmission control circuit 240Δ.
It is either allowed to pass through A or prohibited from passing through. By doing so, there is an advantage that the creation of a software hierarchy in the CPU 20 is facilitated by separating the selection of a destination in the demultiplexer 27OA and the sending of a signal.

The specific circuit configuration of this output control circuit 24OA (240B>) is the same as that already shown in FIG. 6G.

FIG. 8A shows the circuit configuration of the conference call circuit 350. 360 is a multiplex circuit, which converts serially input signals 15A and 15B from the office line side and signals 162A to 162D applied from the terminal device 70 via receiving circuits 150A to 150D to bus signals 920,
Select according to the instructions of 921.922, multiplex,
It is converted into parallel data at the timing of signal 1377, and outputted in parallel as bus signal 420 at the timing of bus signal 1430.

430 is an adder, which outputs a bus signal 927 for setting the attenuation amount for each of the plurality of signals of the bus signal 420 from the multiplex circuit 360, a bus signal 1430 required as a timing signal for setting attenuation, and an initial value. In response to the signal 1480, which is necessary as a clear signal for setting the value to zero, and the signal 1482 for latching the addition data, a signal 545 representing the polarity of the signal and a bus signal 652 for outputting the addition result in parallel are generated. is outputting.

660 is a demultiplexing circuit which latches the input signal 545 and the bus signal 652 which is a parallel signal at the timing of the bus signal 1475 and according to the instruction of the bus signal 1470, and in the period indicated by the signal 1268, the bus signal 9 is latched.
The signals 20, 921, and 922 are sent to the destinations indicated by the signals 691 to 696 connected to the respective destinations at the timing of the signal 1269.

FIG. 8B shows a more specific circuit configuration of the multiplex circuit 360.

361A to 361C are multiplexers which receive signals 15A and 15B from the office line side and signals 162A to 162A applied from the terminal device 70 via receiving circuits 150A to 150D.
162D, multiplexed signals 362A to 362C are outputted using bus signals 920 to 922 indicating respective destinations.

Signal 36 of each output of multiplexers 361A to 361C
2A to 362C are S/p registers 364A, each of which is a register for converting serial input into parallel output.
~364C, is taken in at the timing of signal 1377, is output by parallel bus signal 365Δ~365C, and is applied to multiplexer 380.

At multiplexer 380, applied bus signal 365
Δ~365C is time-divided at the timing of signal 1430 and output as bus signal 420.

FIG. 8C shows multiplexer 361Δ (361B).

361C is the same), and the multiplexer 361A is connected to the receiving circuit 1
Signals 162A-1 applied via 50A-150D
62D, signals 15A and 15B from the office line side, and a signal 9 constituting a bus signal 920 for selecting each destination.
39 to 941 are applied to data terminals D1 to D6 and select terminals AC, and a multiplexed serial signal 362Δ is output to output terminal Y.

Figure 8D shows an S/P register 364△ (364B, 36
4C) is shown, in which a signal 362A from a multiplexer 361A is received at input terminal A,
Receive the signal 1377 for reception timing at the clock terminal, take in the signal 362A, and output the signal 3 in parallel.
6GΔ~373A (bus signal 365A> output terminal QA
- Obtained by QH.

FIG. 8E shows a specific circuit diagram of the multiplexer 380, which includes a set of AND gates 381 to 388 and an OR gate 406, a set of AND gates 1 to 389 to 396 and an OR gate 407, and a set of AND gates 381 to 388 and an OR gate 406.・Gates 397-40
4 and an OR gate 408, each set having the same configuration.

Therefore, to explain the first set, the signals g366A to 373A making up the bus signal 365A are as follows:
Signals 1431 and 1436 in the bus signal 1430, which are applied to one of the legitimate children of the AND gates 381 to 388 and indicate the timing for time-sharing transmission, are applied to the other legitimate child of each of the AND gates 381 to 388 via the OR gate 406. The signals 421 to 428 (bus signal 42
0) is output. AND gates 389-396 and 397-404 each input signal 421 at different times.
.about.428, time-division multiplexed signals @421 to 428 are obtained. Here resistance 411
418 is an open drain pull-up resistor used to wire-OR these three sets of AND gates.

FIG. 9A shows a more specific circuit configuration of adder 430.

440 is a nonlinear/linear converter which receives the bus signal 420, which is a nonlinear signal from the multiplex circuit 360, and instructs whether this nonlinear signal is based on the μ law or the He law. /A switching signal 3
58 is applied thereto, which is converted into a linear signal and output as a linear bus signal 445.

460 is an attenuation instruction circuit which outputs a signal 469 at the timing of the bus signal 1430 for distinguishing the amount of attenuation instructed by the bus signal 927 between callers.

470 is an attenuation circuit that attenuates the linear bus signal 445 according to the instruction of the signal 469, and outputs the bus signal 475 that has undergone the specified attenuation to the caller side.

This bus signal 475 is applied to the total adder 500, and the signal @4 in the bus signal indicating the polarity of the data in the bus signal @420 is applied.
28 and a signal e which is a clear signal to set the initial value to zero.
1480 and a signal 148 for latching the addition data.
2, the adder 500 outputs a bus signal 585 indicating the addition result and a signal 545 indicating its polarity.

650 is a linear/nonlinear converter, which converts the applied bus signal 585 into a linear bus signal 585 as a nonlinear bus signal 652 according to the μ law according to the μ/A switching signal 358. ing.

FIG. 9B shows a circuit diagram of nonlinear/linear converter 440.

441 and 442 are read-only memories <ROM
), signals 421 to 427 of the signals composing the bus signal 420 are applied to the respective input terminals 〇-A6, and the μ/A switching signal 358 is applied to the input terminal A7, so that the writing is performed. Store the linear data in the ROM442
output terminal.

-D7 outputs signals 446-453, and output terminal DO-D4 of ROM 441 outputs signals 454-45B, respectively. These signals 446-458 constitute a bus signal 445.

FIG. 9C shows a circuit diagram of the attenuation instruction circuit 460, in which three OR gates 461-463 have signals 1434, 1435, 1431, .
1436, 1432, and 1433 are applied to the three AND gates 464 to 466, and signals 942 to 944 constituting a bus signal 927 indicating the amount of attenuation, respectively.
The outputs of OR gates 461-463 are applied, and the outputs of each AND gate 464-466 are applied to OR gate 467.
is applied to output a signal 469.

FIG. 9D shows the attenuation circuit 470, which is a 2-bit
It is composed of multiplexers 471 to 474.

Linear signals 446-449, 450-453 and 454
~457 is a 2-bit multiplexer 47
1,472.473 respective input terminals A4. A3.
A2. The linear signal 458 applied to A1 is a 2-bit signal.
Applied to the input terminal A4 of the multiplexer 474, the rough signals 447°448.449.450 and 451,4
52.453.454 and 455.456, 457, 45
8 is a 2-bit multiplexer 471°4
72.473 input terminal B4. B3. B2. A signal 469 for selecting one input terminal A or B is applied to each select terminal S, and a signal 469 for selecting one input terminal A or B is applied to each select terminal S.
Signals 476 to 487 are output from Y4 of 474, and signal 488 is output from Y4 of 474, and these signals 476 to 48B constitute a bus signal 475.

FIG. 9E shows a more specific circuit configuration of full adder 500. The first adder 510 receives a linearized and attenuated lotus signal 475, a signal 428 indicating whether the polarity of the bus signal 475 is positive or negative, and a bus signal 620 indicating the previous addition result. is applied, and when the addition result is negative, the bus signal 530 is expressed as a two's complement number, and the bus signal 530 is
A signal 545 indicating the polarity of the data of the bus signal 530 is output. .

550 is a second caulking device, and when the bus signal 530 is expressed as a two's complement number, the polarity of the signal 530 is not indicated, and by applying the signal 545, the two's complement number is further taken. A bus signal 585 is output.

A temporary storage circuit 610 clears the signal 1480, latches the bus signal 530 required by the output of the first adder 510 with the signal 1482, and outputs the bus signal 620. When the data of the bus signal 475 indicates a negative value, the signal 545 indicates a negative value. 620 is advantageously summed with the bus signal 475 in the first adder 510.

FIG. 9F shows a circuit diagram of the first adder 510, which is composed of adders 511-514 and exclusive-OR gates 516-528.

Signals 476 to 488 forming the bus signal 475 from the attenuation circuit 470 are sent to the exclusive OR gate 5.
16 to 528, and the other terminal is the signal 47.
A signal 428 indicating the polarity of 6 to 488 is applied, and each output of exclusive or go 1 to 516 to 52B is input to input terminals A1 to Δ4 and 5 of adders 511 to 513.
A signal 428 indicating the polarity is applied to the input terminal Co of the Age-511 and the input terminals Δ2, 3 of the Adder 514, and the bus signal 620 from the Adder 514 is applied to the A1 of the Adder 514. The beliefs that make up the
1 to 635 or input terminal B of Age-511 to 513]
Applied to B4 and 81 to B3 of 51141, respectively,
The input terminals GO of the game machines 512 to 514 are applied with the carry up signals from the terminals 1 and 476 to 48ε3 and the signals 621 to 635, respectively. The addition result is adder 511-51
From the output terminals 81 to S4 of 3 and 51 to S3 of 514,
The signals are output as signals 531 and 545.

7A9G shows a circuit diagram of the temporary storage circuit 610, which is composed of latches 611 to 614 and an inverter 616.

Input terminals D1 to D4 of the latches 611 to 613 and D1 to D3 of the latches 614 are supplied with signals 531 to 531 of the output of the first adder 510.
545 is applied to each of the latches 611 to 614, a clearing signal 1480 is applied to each clear terminal CL of the latches 611 to 614 via the inverter 616, and a latch signal 1482 is applied to each clock terminal, so that the signal 531-5
45 is latched and signals 621 to 635 are output.

9)] shows a circuit diagram of the second adder 550, which is composed of adders 551-554, exclusive OR gates 556-569, and OR gates 571-583.

The bus signal 530 is the addition result from the first adder 510.
Signals 531 to 544 constituting are applied to one input terminal of exclusive or go 1 to 5':, G! 1. 545 indicating constancy
is applied to the input terminals CO of the adders 552 to 554, and a signal indicating a carry from the output terminal C4 of the adders 551 to 553 is applied to the input terminals CO of the adders 552 to 554, respectively. B2 is grounded to input zero. Output terminals 81 to S4 of adders 551 to 553 and 81 of adders 554 are OR/
It is connected to one input terminal of gates 571-583, and a signal representing an overflow from output terminal S2 of adder 554 is applied to the other terminal, and a signal is output from each OR gate 571-583, respectively. 586-598
is outputting.

These signals 586-598 constitute bus signal 585.

FIG. 91 shows a circuit diagram of a linear/nonlinear converter 650, which is a read-only memory, and includes a full adder 50.
The signals 586 to 598 that make up the bus signal 585, which is a linear signal with an output of 0, are connected to the input terminal AO-A12.
and the nonlinearized signals 653 to 659 are output to the output terminal Do in accordance with the μ law m or the He law directed by the μ/A switching signal 358 applied to the input terminal A13.
~ I got it on D6. These signals 653 to 659 constitute a bus signal 652.

FIG. 10A shows a more specific circuit configuration of the demultiplexer circuit 660 (FIG. 8A), which includes P/S registers 661A to 661C and a demultiplexer 670Δ.
~670C and OR gates 685~690.

In the P/S register 661A (661B, 661C) for serially outputting parallel signals, the adder 43
A bus signal 652 indicating the result of addition from 0 and a signal 545 indicating the polarity of data are used as a latch clock signal 14.
71 (1472, 1473) and the signal 1476 (1477, 1478) at the latch timing,
During the period indicated by the signal 1268, the serial signal 668Δ(668B, 668C) is generated at the timing of the signal 1269.
) is output.

Demultiplexer 670Δ (670B, 670C) receiving signal 668A (6688, 668C) sends signals 679A to 684A (679
B~684B, 6790~684C), and the outputs of each demultiplexer 670A~670C are ORed by OR gates 685~690, respectively.
The signals are output as signals 691-696. Of these signals, 691 and 692 are output to the office line side as signals 14A and 14B via OR circuits 13Δ and 13B, respectively (see FIG. 2A). Moreover, the signals 693 to 696 are
Via the extension interface circuits 100A to 100D,
Each is sent to the terminal device 70.

FIG. 10B shows the P/S register 661A (661B,
661C is the same).

Adder 4 is connected to input terminals A to G of shift register 662.
Signals 653~ constituting the bus signal 652 from 30
659 are respectively applied, a signal 545 representing the polarity is applied to the input terminal 1, and a signal 545 representing the polarity is applied to the shift/load terminal S.
A latch timing signal 1476 is applied to /L via an inverter 665, and an OR/L signal is applied to the clock terminal.
Through gate 663, the latch clock signal 1
471 and the transmission timing signal e1269 are applied, and during the period when the signal 1476 is "H", the signal 1471 is
Signals 653 to 659 and 545 are captured every time the signal 1269 rises, and are outputted as a signal 668A from the output terminal SO at the timing of the signal 1269 through the AND gate 664 during the period of the signal 1268.

FIG. 10C shows demultiplexer 670A (670B
, 670C are also shown). In the decoder 671, signals 939 to 941 constituting the bus signal 920 instructing the destination are sent to select terminals A to C, respectively, and P
/S register signal 668A to enable terminal GA
signals 679A to 684A from output terminals Y1 to Y6 via inverters 672 to 677, respectively.
It is output as .

FIGS. 10D and 10E are timing charts 1 to 1 representing the main operations of conference call circuit 350.

Figures 10D (a>, (b), and (c) show signals 362A, 362B, and 362C, which are the outputs of multiplexers 361A, 361B, and 361C (Figure 8B), respectively, and the signal 1377 shown in (d). is S/P register 36
Signals 362A, 4A, 364B, and 364C, respectively.
362B, 362C, (e
).

(f) and (q) respectively show signals @365A, 365B, and 365C that are captured and output in this way.

(h) of FIG. 10D shows P/S registers 661A to 6
Signal 1 representing the period of transmission from 61C (Figure 10A)
268 is shown, and (i) shows the signal 1 for sending timing.
269 is shown and (j>.

(k>, (J2) each have a P/S register 661
Signals 668A, 668B, 6 which are the outputs of A to 661C
68C is shown.

In Figure 10D, each signal (a) to (g) and (h)
A guard time T2 and an addition time T3 for 2 bits as described in FIG. It also allows conference calls to be held as needed. During the 2-bit period of addition time T3 following this guard time T2, the first
The joining work shown in the timing chart in Figure 0E is being carried out.

Here, in FIGS. 1E, 10D, and 10E, addition time T3 is provided immediately after guard time T2 for convenience of explanation;
2 or may be provided so as to end immediately before B7, which is the first bit of the data information.

FIGS. 10E (a) to (C) show the multiplexer 38
Signals @ 1431 to 1436 forming the bus signal M1430 (FIG. 8B) applied to the bus signal M1430 (FIG. 8B) applied to
The contents of 20 correspond to S/P registers 364A, B, and C, and 11 A #l.

It is designated as “31Z1”CT+. The bus signal 475 shown in (e) is obtained by converting the nonlinear bus signal shown in (d> into a linear signal and passing it through the attenuation circuit 470. After clearing the signal g1482 shown in (f) of Fig. 10E, the linear signal 44 of (e) is cleared.
5 is latched and temporarily stored in the special mention circuit 610,
It is output as shown in bus signal 5620 in (g).

(h) shows the bus signal 58 which is the output of the second adder 56550.
5 is shown, and this bus signal 585 shows the result of addition of the bus signal 475 in (e) and the bus signal 620 in (g).

(i) shows a bus signal 652 obtained by converting the linear bus signal 585 in (h) into a nonlinear one.

From the bus signal 652 shown in (i), <m>, (
n>, signals 1476 to 1478 shown in (p), respectively.
At the end of 1', data is taken into the S/P registers 661A to 66.1C (FIG. 10A) at the rising edge of signals 1471 to 1473 shown in (j>, (k>, N).

FIG. 11 shows a circuit diagram of the broadcast circuit 700, in which the signals 25 from the central telephone communication circuits 25OA and 250B are shown.
7A, 257B (FIG. 7A), signals 239A, 239B (FIG. 6A) from the extension communication circuit 200 are ORed by an OR gate 701 to obtain a signal 711, and this signal 711 is one of the AND gates 702 to 705. is applied to the input terminal of

Signals 871 to 874 indicating the destination are applied to the other input terminals of each of the AND gates 702 to 705, and signals 712 to 715 are output from each of the AND gates 702 to 705. Signal 712~
715 are extension interface circuits 100A to 100A, respectively.
100B to each terminal device 70.

FIG. 12A shows a specific circuit configuration of the sound source circuit 720, in which multiplexer 721 receives signals 66 to 69 from various sound sources and sends signals 916 to 99 to select a destination.
The signal @722 selected by 18 is obtained and applied to the serial input/serial output S/S register 725. Therefore, the signal 728 is taken in at the signal 1377 and sent out at the timing of the signal 1269 during the period of the signal 1268.

This signal 728 is applied to one input terminal of AND gates 731 to 734, and signals 866 to 869 indicating the destination are applied to the other input terminals of each of AND gates 731 to 734. The output of
Signals 736 to 739 are obtained, and these signals 73
6 to 739 are extension interface circuits 100, respectively.
It is sent to each terminal device 70 via A to 100D.

FIG. 128 shows a circuit diagram of an 8-bit multiplexer 721. Signals 66 to 69 from various sound sources are applied to input terminals D1 to D4, respectively, and select terminals A, B, and C are applied to input terminals D1 to D4. are applied with signals 916 to 918 for selecting a destination, respectively, and a signal 7 is applied to the output terminal Y.
I got 22.

The circuit of the S/S register 725 shown in FIG.
In the circuit shown in Figure C, signal 218A is connected to signal 722.
This is the same as converting the signal 225Δ to the signal 728.

FIG. 13A shows the internal configuration of CPU interface circuit 800.

801 is an interrupt circuit, and a signal F for interrupt timing.
1316, the reset signal 21 for initialization when the power is turned on, and the signal 848 applied to reset when the work is completed, the 1°
' is outputted as a signal 808.

Reference numeral 810 denotes an address decoding circuit, which receives a reset signal 21 for initialization when the power is turned on and an address bus signal @25, and outputs a bus signal 816 indicating the timing and address for reading according to the read signal 22. The write signal 23 also provides bus signals 821 and 82 indicating the write timing and address.
A signal 848 for outputting 6,834.844 and resetting the interrupt circuit 801 when a series of operations is completed.
Output.

850 is a 4-bit latch circuit, which is reset by the reset signal 21 for initialization when the power is turned on, and outputs a bus signal 826 indicating write timing and address.
and bus signals 860, 865, 870 which are applied with the signals 36 to 39 included in the data bus signal 35 and send the data of the signals 36 to 39 to the designated address at the timing of the bus signal 826. ,875,880,8
It is outputting 85.890.

900 is a 3-bit latch circuit, which is reset by the initialization sensor L- signal 21 that is opened when the power is turned on.
Bus signal 83 indicating timing and address for writing
4 and signals 36 to 3B included in the data bus signal 35
is applied, and at the timing of the bus signal 834, bus signals 915, 920 to 927 are outputted to send the data of signals @36 to 38 to the designated address.

950 is a 2-bit latch circuit, which is reset by the reset signal 21 for initialization when the power is turned on, and outputs a bus signal 844 indicating write timing and address.
, signals 36.37 included in the data bus signal 35 are applied, and at the timing of the bus signal 844, signals 960 to 965 are outputted to send the data of the signal 36.37 to the specified address. ing.

FIG. 138 shows a circuit diagram of the interrupt circuit 801, and FIG. 13C shows a timing chart showing waveforms of each part thereof.

In FIG. 13B, 802 is a D flip-flop, and 111 +1 is always applied to its data terminal, and the reset signal 21 at power-on shown in FIG. 13C (b) and at the end of work shown in FIG. 13C (d) are applied. A reset signal 848 is received at the clear terminal CL via the inverter 804 and the NOR gate 803, and each time the interrupt timing signal 1316 shown in (a>) is applied, it is determined that the interrupt period is in progress. Signal 80 of (C) indicated by 14141
8 is output to the CPU 20 (FIG. 1A).

FIG. 13D shows a circuit diagram of the address decoding circuit 810, and FIG. 13E shows a timing diagram showing the waveforms of each part.
Showing a chart.

A decoder 811 sends signals 29 to 33 of the top five hits included in the address bus 25 to terminal A.

B, C, G2A, G2B to select the decoder, the signals are applied to terminals YO, Y1 . It is output to Y2.

812 is a decoder, which sends the read signal 22 to terminal G1.
, the signal from the terminal YO of the decoder 811 is transferred to the terminal G2A.
The reset signal 21 for initialization when the power is turned on is connected to terminal G.
2B receives signals 26 to 2B of the lower three bits of the address bus signal 25 at terminals A to C, and outputs the signal 8 included in the bus signal 816 indicating read timing and address.
17 to 820 are connected to terminals YO to Y3 by 1.

813 is a decoder, which sends the write signal 23 to terminal G1.
, the signal from the terminal YO of the decoder 811 is transferred to the terminal G2A.
The reset signal 21 for initialization when the power is turned on is connected to terminal G.
2B, signals 26 to 28 of the lower three bits of the address bus signal 25 are received by the legitimate children A to C, and the signal 8 included in the bus signal 821 indicating the timing and address for writing is transmitted.
22 to 825 and some signals 8 included in the bus signal 826
27 to 830 are obtained at terminals YO to Y7.

814 is a decoder, which sends the write signal 23 to terminal G1.
, the signal from terminal Y1 of decoder 811 is transferred to terminal G2A.
The reset signal 21 for initialization when the power is turned on is connected to terminal G.
2B, signals 26 to 28 of the lower three bits of the address bus signal 25 are received at terminals A to C, and some signals 831 to 833 and the bus signal 831 to 833, which are matched with the bus signal 826 indicating the timing and address for writing, are received at the terminals A to C. Some signals 835 to 839 included in signal 834 are obtained at terminals YO-Y7.

815 is a decoder, which sends the write signal 23 to terminal G1.
, the signal from terminal Y2 of decoder 811 is transferred to terminal G2A.
The reset signal 21 for initialization when the power is turned on is connected to terminal G.
2B, signals 26 to 28 of the lower three bits of the address bus signal 25 are received by the legitimate children A to C, and some signals 840 to 843 included in the bus signal 834 indicating the timing and address for writing and the bus Some signals 845 to 847 included in signal 844 and signal 848 are obtained at terminals YO-Y7.

In the circuit shown in FIG. 13D, the address bus signal 25 including signals 26 to 33 is applied as shown in FIG. 13E (a), and the write signal 23 is applied at the timing shown in FIG. 13E (b). , at the timing of the write signal 23 in (b), at the address bus signal 25 in (a), (d
A bus signal 826 shown in > is output. When the read signal 22 is applied (not shown in (C)), at that timing, (
A bus signal 816 shown in (e) instructed by the address bus signal 25 of a> is output.

FIG. 14Δ shows a circuit diagram of the 4-bit latch circuit 850, and FIG. 148 shows a timing chart showing waveforms at various parts thereof.

851 to 857 are D flip-flops, and the reset signal 21 is inverted to their clear terminal C+ via an inverter 858, and the signal in FIG.
is applied to those data terminals D1 to D4,
Some signals 36 to 39 of the data bus signal @25 shown in FIG. 14B (a) are applied, and signals 827 to 83 indicating write timing and address are applied to each clock terminal.
3 is applied as partially shown in (C) to (e), and the signals 36 to 36 in (a) are applied at the timing of each signal 827 to 833.
Bus signal 860 (Figure 14B (
f)), 865 (g), 870 (h), 875,8
It outputs 80,885,890.

FIG. 14C shows a circuit diagram of the 3-bit latch circuit 900, and FIG. 14D shows a timing chart showing waveforms at various parts thereof.

901 to 909 are D flip-flops, and the reset signal 21 is inverted to their clear terminal CL via an inverter 910, and the signal 914 in FIG. 14D(b) is output.
is applied to those data terminals D1 to D3,
Some signals 36 to 38 of the data bus signal 25 shown in FIG. 14D (a) are applied, and signals 835 to 84 indicating write timing and address are applied to each clock terminal.
3 is applied as partially shown in (C) to (e), and at the timing of each signal 835 to 843, the signals 36 to 36 of (a>
Bus signal 915 (Figure 14D (
f)>, 920 (Q), 921 (h), 922-9
27 is output.

FIG. 14E shows a circuit diagram of the 2-bit latch circuit 950, and FIG. 14F shows a timing chart showing waveforms at various parts thereof.

951 to 956 are D flip-flops, and the reset signal 21 is inverted to their clear terminal CL via an inverter 957, and the signal 958 in FIG. 14F(b) is output.
and the 14th F is applied to those data terminals.
Some signals 36 of the data bus signal 25 shown in FIG.
．． 37 is applied, and signals 845 to 847 indicating write timing and address are applied to each clock terminal (C
) to (e), 8 signals @845 to 84
Signals 960 and 961 (Fig. 14F (f>>, 96
2 and 963 (g), 964 and 965 (h) are output.

FIG. 15A shows the internal configuration of the timing circuit 1000, and FIGS. 158 and 15C show timing charts showing waveforms of each part thereof.

The 1090 receives the reset signal 21 when the power is turned on and, for example, changes the clock 51 with a frequency of 2.048 Mtlz to 2.
Divide the signal @1096, divide the frequency by 4 and convert the signal 1097 to 8
It divides the frequency and outputs a signal 1098 with a frequency of 256KH2.

1100 is a frame pulse circuit, which is reset in response to the reset signal 21, and is reset in response to the signal @1098.
Based on the signal 1128 output for each frame and the frame number, the bus signal 1120 shown in FIG. 15B (a) is output.

1150 is a multi-frame pulse circuit, which is reset by the reset signal 21 and receives the signal 1128 output for each frame, and performs the multi-frame pulse circuit in FIGS. 15C (b) and (C
) signals 1177 and 1176 are output. here(
Signal 1177 in b) indicates the frame period during which D information can be sent. That is, frame numbers O to 7
This shows the period during which the data will be sent.

A signal 1176 in FIG. 15C (C) indicates the period of frame number 8, which is a frame that transmits the F bit (see FIG. 1C), which is information for obtaining the frame period.

1200 is a first to fourth transmission timing circuit;
For example, 25
6KH2 frequency signal g1098 and Figure 15C (b)
, signals 1177 and 1176 shown in (C) and the 15th B
The bus signal 1120 shown in FIG.
A signal 1231 indicating the timing for transmitting the start bit in FIG. 15B(d), a signal g1268 indicating the timing for transmitting data information B in FIG. 15B(e), and P information in FIG. Signal 13 indicating timing to send
04 and a signal 108A shown in FIG.

109A (see Figures 1A to 1E) and a signal @1269 indicating the timing of each bit during the period of sending the CPU.
a signal 1316 for interrupt timing for 20;
A signal 1317 indicating the timing of sending out the F bit and a signal 1318 indicating the sending period of data information B are output.

1350 is a reception timing circuit, which receives reset signal 2
1, the signal 1098, the clock 51, the signal 1177 (FIG. 15C (b)), and the signal 1120 indicating the frame number (FIG. 15B (a)) are received, and the signal shown in FIG. Up signal 61A (1st B) shown in
For example, the signal @1376 shown in FIG. 15B(g) having a frequency of 256KH2 (see FIGS.
(see Figure (C)) and the signal 13 shown in (h) of Figure 15B.
77 (Fig. 1D, Fig. 1E, Fig. 1F.

(see Figure 4B) and the signal 13 shown in (1) of Figure 15B.
79 (see FIG. 5B).

1400 indicates the first and second conference timing circuits, and the signals from the frequency divider circuit 10.90 @1096~109
8 and the clock 51, a conference signal 1431 is generated.
A bus signal 143 consisting of ~1436 (see Figure 10E)
0, a bus signal 1470 consisting of latching signals 1471 to 1473 (see FIG. 10E), a bus signal 1475 consisting of signals 1476 to 1478 (see FIG. 10E) indicating a latch period, and a - hour storage circuit 610. A signal 1480 for resetting (see FIG. 10E) and a latch signal 1482 (first
(See Figure 0E) is output.

Here, during the period of addition time T3 for the conference call (between O and 1 bit in one frame) shown in FIG. be done.

Similarly, in the transmission timing period (between 0 and 12 bits in one frame) shown in FIG. 158(C),
Signal 1231, 1268.1269.1304.131
6 to 1318 are sent out.

Similarly, the reception timing period (1
Between bits 21 and 29 of the frame), signals 1376.1377.1379 are sent out.

FIG. 15D is a timing chart showing the circuit of the frequency dividing circuit 1090, and FIG. 15E is a timing chart showing the waveforms of each part thereof.

1090 is a frequency divider circuit, and a reset signal @ when the power is turned on.
21 is received at the clear terminal CL via the inverter 1091 and cleared, and when the clock 51 of FIG. A signal 1097 (C) after dividing the frequency by 4 is sent to the terminal QA, and a signal 1098 (d) after dividing the frequency by 8 is sent to the output terminal QC (q).

FIG. 15F shows the frame pulse circuit 1100, and FIG. 15G shows a timing chart of waveforms of each part thereof.

1110 and 1111 are hexadecimal counters, and both have a reset signal 2 at their clear terminal CL when the power is turned on.
1 is applied via the inverter 1117, and the clock terminal is applied via the inverter 1118, as shown in FIG. 15G(a).
A signal 1098 shown in is applied. , the outputs OA, QB, QC, and QD of the hexadecimal counter 1110 include the 15th
As shown in Figure G (b), (c), (d), and (e), (a
) is obtained by dividing the signal 1098 by two, 1121, a signal obtained by dividing it by 4, 1122, a signal obtained by dividing it by 8, 1123, and a signal 1124, obtained by dividing the signal 16 by 16. When the hexadecimal counter 1110 reaches the full count state, the carry-out terminal CO
The output is applied to the enable terminals P and T of the hexadecimal counter 1111, and the output terminal QA outputs the signal 1098 of <a> to 32 as shown in FIG. A frequency-divided signal 1125 is obtained.

Each of the frequency-divided signals 1121 to 1125 is passed through an AND gate 1114 to a signal 1126 shown in FIG. 15G (q).
is applied to the data terminal of the D flip-flop 1112. The signal 109B in FIG. 15G (a) is applied to the clock terminal of this D flip 70 tube 1112 via two inverters 1118 and 1119, and the signal 1127 in (h) is obtained at its Q output. This signal 1127 is applied to the data terminal of the D flip-flop 1113, and the signal 1098 in (a) is applied to its clock terminal via an inverter 1118, and its Q output is applied to (:). A signal 1128 shown is obtained.

FIG. 15H shows multiframe pulse circuit 1150.
FIG. 15I shows a timing chart showing the waveforms of each part of the circuit.

1151 and 1152 are hexadecimal counters, and both have a reset signal 21 at their clear terminal CL when the power is turned on.
is applied via an inverter 1160, and a signal 1128 shown in FIG. 15I (a) is applied to the clock terminal. Output QA, QB, Q of hexadecimal counter 1151
For C, QD, Fig. 151 (b), (c), (d), (
As shown in e), a signal 1171 is obtained by dividing the signal 1128 in (a) by 2, a signal 1172 . ,! A signal 1173 whose frequency is divided by 3 and a signal 1174 whose frequency is divided by 16 are 1q. When the hexadecimal counter 1151 reaches the full count state, an output is output from the carry-out terminal CO, which is applied to the enable terminals P and D of the hexadecimal counter 1152, and from the output terminal QA, the output is output from the carry-out terminal CO (FIG. 151). As shown in f), a signal 1175 obtained by frequency-dividing the signal 1128 in (a) by 32 is obtained.

The frequency-divided signal g1174 of (e) is directly applied to the frequency-divided signals 1171 to 1173. becomes a signal 1176 shown in FIG. 151(h). Also, inverter 11
AND gate 115 with signal 1174 applied through 58 and signal 1175 through inverter 1159.
4 outputs a signal 1177 shown in FIG. 15I (g).

FIG. 16A shows the first to fourth transmission timing circuits 120.
The circuit diagram of the first transmission timing circuit included in
FIG. 6B shows a timing chart of the waveforms of each part.

Signals 1 of (b) to (f>) constituting the bus signal 1120 whose bit numbers are expressed numerically in FIG. 16B (a)
121 to 1125 are inverters 1221 to 1, respectively.
225 to AND gate 1212;
A signal 1231 shown in (h) is output from there.

The flip-flop 1 receives the reset signal 21 when the power is turned on and is applied to the clear terminal CL via the inverter 1226.
The clock terminal of 211 receives the signal 1098 shown in (g).
is applied, and the signal 12 of (h) is applied to the data terminal.
31 is applied, and the signal Q1 shown in (i) is applied to its Q output.
232 is obtained.

Each output of inverters 1221, 1223 to 1225 and signal 1122 are applied to AND gate 1213, and (
The signal g1233 shown in j) is output.

FIG. 16C shows the first to fourth transmission timing circuits 120.
Timing charts showing the waveforms of each part of the second transmission timing circuit included in the second transmission timing circuit 0 are shown in FIG.
(k).

Signals 1121 to 1125 constituting the bus signal 1120 whose bit numbers are expressed numerically in FIG. 16E (a)
Of these, signals 1121 to 1123 are directly connected to signal 112.
4 and 1125 are inverters 1251 and 1252
applied to Nando Goo 1-1244 via (C
) is output, and the AND gate 1
245 and inverters 1251 and 1252
The output of is also applied to an AND gate 1245, and its output becomes a signal 1262 shown in (d>), which is applied to terminals A and B of an 8-bit shift register 1241.

Clear terminal CL of 8-bit shift register 1241
In this case, the reset signal 21 at power-on is sent to the inverter 12.
53, and the signal 1098 shown in (b) is applied to its clock terminal, and its third and fourth outputs QC, QD output signals (e) and Signals 1263 and 1264 shown in (f) are output.

Clears the output of inverter 1253 when power is turned on.Terminal C
D flip-flop 12 reset by applying to L
The signal 1098 in (b) is applied to the clock terminals of 42 and 1243 via the inverter 1254, and the signal 1263 in (e) is applied to the data terminal of the D flip 70 tube 1242, causing the Q output. It is obtained as a signal 1265 shown in (CJ).

The signal 1265 is applied to the data terminal of the D flip-flop 1243 to obtain the signal 1266 shown in FIG. A signal 1268 shown in i) is obtained.

The AND gate 1246 to which the output of the inverter 1254 and the signal 1264 are applied outputs the signal 1267 shown in (j>
This signal 1267 is applied to the AND gate 1247 together with the signal Q1266, and the signal 1269 shown in (k) is outputted.

FIG. 16D shows the first to fourth transmission timing circuits 120.
A circuit diagram of the third transmission timing circuit included in the third transmission timing circuit 0 is shown, and timing charts of waveforms of each part are shown in (a), (b), D') to (p) of FIG. 16E.

Signals 1121 to 11 constituting the bus signal 1120 in which the bit numbers shown in FIG. 16E (a) are expressed numerically
Signals 1121, 1123.1125 of 25 are connected to inverters 1291 to 1293, and signals 1122.
1124 is directly applied to a NAND gate 1283 to output a signal 1301 shown in (e), which is applied to the data terminal of a D flip-flop 1281.

A reset signal 21 at power-on is applied to the clear terminal CL of this D flip-flop through the inverter 1294, and the D flip-flop has already been reset. A signal 1098 shown in (b) is applied to the clock terminal of the D flip-flop 1281, and a signal 1302 shown in (m) is obtained at the not-Q output.

This signal 1302 is applied to a D flip-flop 1282. The clear terminal CL of this D flip-flop 1282 is the clear terminal C of the D flip-flop 1282.
It is connected to L and is reset when the power is turned on. D
The clock terminal of flip-flop 1282 receives signal 1.
098 is applied via the inverter 1295, and the signal 1303 shown in (n> is output to the Q output thereof.

The inputs of AND gate 1284 include signal 1121.1
122 and 1125 are inverters 1291 and 1, respectively.
via 296.1293 and also signal 1123.112
4 is directly applied, and a signal 1304 shown in (p> is obtained at its output.

FIG. 16F shows the first to fourth transmission timing circuits 120.
FIG. 16G shows a timing chart showing the waveforms of each part of the fourth transmission timing circuit included in the fourth transmission timing circuit.

In FIG. 16G (a), a bus signal g1170 in which the frame number is expressed numerically is shown to explain the timing relationship with other signals.

The AND gate 1311 has the signal @123 shown in (f).
2 and a signal 1176 shown in (C) are applied, and a signal 1316 not shown in (h) is output.

The AND gate 1312 has a signal 123 shown in (Q).
3 and a signal 1176 shown in (C) are applied, and a signal 1317 shown in (i) is output. and gate 131
3 is applied with a signal 1303 shown in (d) and a signal 1177 shown in (b), and outputs a signal 1318 shown in (e). Since each signal shown in FIG. 16G is drawn based on the bus signal 1170 representing the frame number shown in (a), the signal 1177 in FIG. 15I ([7)] and the signal 1176 in FIG. , signal 130 of FIG. 16E(n)
3. Figure 16B (i) and (j>'s belief j'1232,
1233, the time is significantly shortened and displayed.

FIG. 17A shows a circuit diagram of the reception timing circuit 1350, and FIGS. 17B, 17C, and 17D show timing charts of waveforms of each part thereof.

1351 is an 8-bit shift register, and its input terminals A and B receive the signal 10 shown in FIG. 17C (b).
98 is applied to the clock terminal of the inverter 1.
The clock 51 shown in FIG. 17C (a) is applied through the 361, and from the third output terminal QC, the clock 51 shown in FIG.
A signal 1371 shown in C) is output. This output is D
applied to the data terminal of flip-flop 1352;
The clock terminal of this D flip-flop 1352 has
The clock 51 shown in FIG. 17C (a) is applied, the signal 1376 shown in FIG. 17C (d) is applied to the Q output, and the signal 1376 shown in FIG.
You will get the inverse of that.

In FIG. 178(a), among the signals 1121 to 1125 of (b) to (f) constituting the bus signal 1120 in which the bit numbers are expressed numerically, the signal 1125 is directly transmitted, and the signal 1124 is transmitted by the inverter. 1362 to an AND gate 1356, the output of which is a signal 1372 shown in (i>).

This signal 1372 is applied to the D flip-flop 1353, and the (d> signal 1123 is applied to the clock terminal of the D flip-flop 1353, and the (j> signal 1373 is obtained at its Q output. b) Signal 11
21 applied to the clock terminal of D flip-flop 1
A signal 1373 of (j>) is applied to the data terminal of 354, and a signal 1374 shown in (k) is obtained at its Q output.

AND gate 1357 has signals 1374 and (h)
The inverted signal of the signal 1376 of is applied, and the signal 1377 of (at) is obtained at its output. Here the 17th B
The relationship between the clock 51 and the signal 1376 in FIGS. The falling edge is clock 51 in FIG. 17B (g).
It is synchronized with the rise of

The AND gate 1355 receives the signals 1121 . (d) belief @1123. (e) Faith 1124
．． The signal 1125 in (f) is directly connected to the signal @112 in (c).
2 is applied via the inverter 1363, and the signal (m) @1375 is output. This signal 1375 and (h
) and the inverted signal 1376 of the AND gate 1358 outputs the signal 1378 of (n>).

The AND gate 1359 has a signal 1378 commonly shown in FIG. 17B (n) and FIG. 17D (C), and a period of frame numbers O to 7 as shown in FIG. 15C (b). In response to the signal 1177 shown in FIG. 17D, the signal 1379 shown in FIG.
and (b> is a bus signal 1170 representing the frame number.
and signals 1378 in (C) and (d).
．． 1379.

Figure 18A shows 1. Second conference timing circuit 1400
The circuit diagram of the first conference timing circuit included in the 18th
Figure B shows a timing chart of the waveforms of each part.

Figure 188 (C) shows the bus signals @1120 (d) to (i) showing the bit numbers in one frame as numbers.
) among the signals 1121 to 1125, the signals 1122 to 1
125 is applied to the NOR gate 1413 and (p)
A signal 1437 is output.

A signal @1121 of (d> is applied to the NAND gate 1414 via an inverter 1421, and a signal 1437 of (p) is directly applied to the NAND gate 1414, and a signal 1438 of (Q>) is obtained at its output.

The input terminals A and B of the decoder 1411 are supplied with the signals of FIG. 18B (a>
) and (b) signal 1098 (see FIG. 15E(d)
) is applied, and the signal 1438 of (Q) is applied to the enable terminal G, and the output terminals YO-Y3 output the signals via inverters 1422 to 1425, respectively.
Signals 1431 to 1434 shown in (i) to (e>) are output.

A signal 1121 of (d>) and a signal 1437 of (p) are applied to the NAND gate 1415, and a signal 1437 of (r) is applied.
439 is output. Input terminal A of decoder 1412
and B include the signals 1097 and (a), respectively.
The signal 1098 of b) is applied, the signal 1439 of (r) is applied to the enable terminal G, and the output terminal Y
O.

Yl outputs (m) and (n> signals @1435.1436 via inverters 1426 and 1427, respectively).

FIG. 18C shows the first. Second conference timing circuit 140
The circuit diagram of the second conference timing circuit included in
Figure 8D shows a timing chart of the waveforms of each part.

1451 and 1452 are D flip-flops,
188<j
>, (e>, signal 1432.143 shown in (n>)
4.1436 is applied.

The clear terminal CL of the D flip-flop 1451 is applied with the signal 1096 shown in FIG. Each (j) ~
Signals 1471 to 1473 shown in (2) are output.

The D flip-flop 1452 sends the signal 1097 obtained by dividing the frequency of the signal (b) @ 1096 by 2 to its clear terminal CL.
A signal 1096 of (b>) is applied to the clock terminal, and signals 1476 to 1478 of (q) to (i) are output to outputs 01 to Q3, respectively.

The signal 1096 in (b) is input to the NOR gate 1455 by 2.
The frequency-divided signal 1097 and the signal 1096 (b) are applied, and the output is the signal 1479 (C).
It is applied to the data terminal of flip-flop 1453. The signal 1096 in (b) is applied to the clear terminal CL of this D flip-flop 1453 via the inverter 1458, and the clock 51 in (a) is applied to its clock terminal.
is applied via an inverter 1459, and a signal 1480 of (d>) is obtained at its Q output.

The signal 1096 in (b) is input to the NOR gate 1456 by 2.
The frequency-divided signal 1097 and the signal 1096 in (b) are applied via the inverter 1458, and the signal 14 in (e) is
81 is output. D to which this signal 1481 is applied
The clear terminal CL of the flip-flop 1454 has (b
) signal 1096 is applied to this clock terminal (
The clock 51 of a) is applied via an inverter 1459, and a signal 1482 shown in (f> is obtained at its Q output.

19-1 to 19-22 are flowcharts showing the flow of operations of the main device 10 and CPU 20 shown in FIGS. 1A and 2A.

The CPU 20 checks at regular intervals whether or not the D information representing control information is output from the terminal device 70 (3200
1, Figure 19-1), if the D information is not detected (32
001N>, checks whether a signal from the office line interface 11, so-called station arrival, is being output (82002>,
If it is not issued from the central office line interface 11,
Return to step 32001 (82002N>).

In step 32002, the signal from the office line interface,
When the CPU 20 detects a so-called station arrival (S2002Y
), detects an incoming call from the office line 12, puts it on the D information, and sends the D information transmitting/receiving circuit 170 to the extension line interface 1.
00 to the terminal device 70 32021, the first
9-4), the process returns to step 32001.

In step 52001, if there is D information, the CPU 20
(32001Y), reads the content of the information, checks whether or not a call is being requested from the terminal device 70 to the central office line 12 (32003, Figure 19-1), and if so, (S2003Y), the process moves to the station line origination subroutine, and if no request has been made (32003Y).
N>, I terminal device 70 is another terminal device 7 in the same system
It is checked whether the call is a so-called extension call to 0 (32004>).

If the CPtJ 20 confirms that the call is an extension call, it moves to the extension call subroutine (52004Y), and if it is not an extension call (32004N), it checks whether a simultaneous broadcast is requested (52005>).

When it confirms that a simultaneous broadcast is requested, it moves to the simultaneous broadcast subroutine (52005Y), but when it finds out that it has not requested it (32005N>), it requests a background music (hereinafter abbreviated as BGM) broadcast. It is confirmed whether or not (S2006>).

If it is confirmed that a BGM broadcast is requested, the process moves to the BGM broadcast subroutine (52006Y), and if it cannot be confirmed (32006N>), it is checked whether or not a conference call is requested (S2007, 19-2 figure).

If it is confirmed that a conference call is requested, the process proceeds to the conference call subroutine (52007Y), and if it cannot be confirmed (32007N), the terminal device that received the notification that the terminal device 70 was notified of the call arrival in step 52002Y 7
It is checked whether the response is a so-called local response, which is a response from 0 (32008>).

If it is confirmed that it is a station arrival response, the process moves to the station arrival response subroutine (52008Y), and if it cannot be confirmed (32008N>, another terminal in response to calling another terminal device 70 in the same system in step 52004Y). It is checked whether the response signal from the device 70 is a so-called fixed response (32009>).

If it is confirmed that it is a stuck response, the process moves to the stuck response subroutine (52009Y), and if it cannot be confirmed (32009N>, a so-called so-called check is performed to determine whether or not the call with the central office line 12, which was executed as a result of step 52008Y, has ended. Check the end of the local line (S2010>, and if the end of the local line is confirmed, proceed to the subroutine of the end of the local line 52010Y)
If it cannot be confirmed (3201ON>), it is checked whether the call between the terminal devices 70, which was executed as a result of step 52009Y, has ended, that is, a so-called extension termination request has been made (S2001>).

After confirming that the request is to end an extension call,
If the process cannot be confirmed (32011N>, the process moves to the subroutine (52011Y)), and it is checked whether the conference call executed as a result of step 52007Y has ended, that is, a so-called conference termination request is being made (32012>).

If the request to end the conference is confirmed, the process will proceed to the conference end subroutine (32012Y), and if the request cannot be confirmed (32012Y).
32012N>, 52005Y, it is checked whether or not the executed simultaneous broadcast has ended, that is, a so-called - simultaneous broadcast termination is requested (82013, Fig. 19-3).

If the request to end all broadcasting is confirmed, the process moves to the subroutine for ending all broadcasting (32013Y), and if the request cannot be confirmed (32013N>, the so-called BGM ending is completed, which is the end of the 80M broadcast executed as a result of step 52006Y). Check whether the request is made (32014>).

If the request for ending the BGM call is confirmed, the process moves to the subroutine for ending the BGM call (32014Y), and if the request cannot be confirmed (32014N>, an incoming call response is made in step 52008Y, and then the call between the central office line 12 and the terminal device 70 is terminated. 32015).

If it is confirmed that the station line hold is requested, the process moves to the station line hold subroutine (52015Y), and if it cannot be confirmed (82015N>), the station line hold is canceled in step 52015Y, so-called station line hold. Check whether cancellation is requested (32016>).

If it is confirmed that the station line hold release is requested, the process moves to the station line hold release subroutine (32016Y), and if it cannot be confirmed (82016N>, step 5200).
Check whether the fixed response of 9Y requests temporary hold of the extension call, so-called extension hold (
S2017>.

If it is confirmed that the extension is on hold, the process moves to a subroutine for releasing the extension from hold (32017Y), and if it cannot be confirmed (32017N), the process moves to step 52017Y.
32018).

If you confirm that you are requesting to release your extension from hold,
S20'18Y to move to subroutine for releasing extension hold
), if it could not be confirmed (32018N>,
Return to step 32001.

In step 32003 (FIG. 19-1), when the CPU 20 confirms that the call has been made to the central office line, the central office line 12 is connected to the central office line interface 111, the central office line communication circuit 250. Connected to the terminal device 70 via the extension interface circuit 100, dial tone from the office line 12 is sent to the terminal device 70, and upstream signals are sent to the receiving circuit 1502 and the office line communication circuit 25.
0. It is connected to the office line 12 via the OR circuit 13 and the 8-wire interface 11 (32031, Fig. 19-5).

Distinguish whether the central office line 12 is for dial pulse (DP>) or button button (PB) (32032>, and in either case (S2032P)
52033.2034), and if dial information is not included (S2033N, 5203).
4N>, the process returns to step 52001, and if it is included (S2033Y, 2034Y), the transmission control circuit 240 in the office line communication circuit 250 prohibits the dial signal from returning to the terminal device 70 as a sidetone (5203).
6.52041, Figure 19-6.

(Fig. 19-7), the dial signal from the terminal device 70 is
The PU 20 reads the information, and in the case of DP, the CPU 20 instructs the office line interface 11 to send only a dial signal to the office line, and in the case of PB, the office line communication circuit 250. OR circuit 1
52037.32042>, and sends the dialed numbers (32038, 32043>).

Here, dial pulse (DP>
When transmitting a dial number, the central office line interface 11 generates a dial pulse signal and sends it to the central office line, and when transmitting a dial number using the button button (PB), the button dial The signal 66, which is the sound source of the signal, is transmitted to the central telephone communication circuit 250. OR circuit 131
It is sent to the office line 12 via the office line interface 11.

When the dial signal is sent out, the sending control circuit 240
The sidetone prohibition is canceled, a downward communication path from the terminal device 70 to the office line is formed (82039, 32044>, and an upward communication path from the office line to the terminal device 70 is also formed (82039, 32044>).
2040.32045).

This process continues until there is no more dialing information (S
2033, 2034, Figure 19-5).

In step 52004 (FIG. 19-1), if the terminal device 70 is making an extension call to a separate terminal device 70 (S2004Y), the dial tone signal 67 is transmitted to the extension communication circuit 200° and the extension interface circuit 100. 52 and sends a dial tone to the originating terminal 70 via the originating terminal 70.
051, FIG. 19-8), the CPU 20 receives the dial information from the caller via the D information transmitting/receiving circuit 170, deciphers the destination, and notifies the destination terminal device 70 of the incoming call (3
2052>. After that, the process returns to step 52001. .

In step 32005 (Figure 19-1), if it is determined that the request is for simultaneous broadcasting (32005Y)
, to form a transmission path from the requesting terminal device 70 to the extension call circuit 200 via the receiving circuit 150 32061
, FIG. 19-9), a transmission path is formed from the extension communication circuit 200 to the broadcasting circuit 700 (32062>), and in the opposite direction, - from the broadcasting circuit 700 to the extension interface circuit 100. 52063>, step 5200
Return to 1.

When a request for 80M broadcasting from one terminal device 700 is confirmed in step 2006 (Figure 19-1) (S200
6Y), connect the signal 68 from the BGM sound source to the sound source circuit 720 (52071, Figures 19-10), the sound source circuit 72
0 to the extension interface circuit 100, and sends the signal 68, which is a BGM sound source, to the terminal device 70 that requested the 80M broadcast (52072>. Then, the process returns to step 32001.

In step 52007 (Fig. 19-2), when it is confirmed that the request for a conference call is from a terminal device 70 other than the terminal device 70 that is currently communicating with the central office line 12 (S2007Y
), from the office line 12 to the office line interface 11,
Office line communication circuit 250. The downlink route connecting to the terminal device 70 in communication via the extension interface circuit 100 is disconnected (52081, FIGS. 19-11), and from the same terminal device 70 to the receiving circuit 1501 and the central office line communication circuit 250. The route connecting the OR circuit 139 to the office line 12 via the office line interface 11 is disconnected (S2082).

Therefore, from the office line 12 to the office line interface 11° conference call circuit 350. Form a down route to the terminal device 70 via the extension interface circuit 100 (32083)
, from the terminal device 70 to the receiving circuit 150 and the conference call circuit 35
0. OR circuit 132 forms a route connected to the office line 12 via the office line interface 11 (32084>
. Both routes formed in steps 32083 and 32084 are formed for other terminal devices 70 that have requested to participate in the conference call, and audio information is converted between each terminal device 70 and the office line 12 to complete the conference call. Enabling a call (32085°) When it is confirmed in step 32008 (Figure 19-2) that it is a response to the call in step 52021 (Figure 19-4) (32008Y), the central office line 1
52091, No. 19-
12), and from the receiving circuit 150 to the central office line communication circuit 250.
A transmission path to the OR circuit 13 is formed via (3209
2>, a call is made between the office line 12 and the terminal device 70,
Return to step 82001.

In step 32009 (Fig. 19-2), when it is confirmed that an incoming call from another terminal device 70 is applied via the D information transmitting/receiving circuit 170 in step 32052 (Fig. 19-8) (S2009Y), an extension call is received. circuit 200
32101 (FIGS. 19-13)) and the receiving circuit 150.
to the extension call circuit 200 (321
02>, form a transmission path to one terminal device 70, and similarly form transmission paths to other terminal devices (S2103
．． 82104>, a call is made between both terminal devices 70, and the process returns to step 32001.

In step 32010 (Figure 19-2), the 19th
- When it is confirmed that the call between the office line and the terminal 70 in Figure 12 has ended (S201Y), the transmission path from the office line communication circuit 250 to the extension interface circuit 100 and the reception circuit 150 are confirmed.
The transmission line from the office line communication circuit 25O to the OR circuit 13 is cut off (S2110.3211L No. 19-14).
), the connection between the office line 12 and the terminal device 70 is terminated and the process returns to step 52001.

In step 32011 (Figure 19-2), the 19th
- When it is confirmed that the call between the terminal devices 70 in FIG.
50 to the extension call circuit 200, and
52121.3 Disconnect connection to one terminal device 70
2122゜Figures 19-15), and similarly disconnect the other terminal device 70 (32123, 521).
24>, return to step 2001.

In step 2012 (Figure 19-2), the 19th-
After confirming that the conference call in Figure 11 has ended (S20
12Y), the route from the office line 12 formed in step 2083 (FIGS. 19-11) to the extension interface circuit 100 via the conference call circuit 350 is clearly established 321.
31, Figures 19-16〉, the route from the reception circuit 150 formed in step 32084 to the OR circuit 13 via the conference call circuit 350 is established 32132>, and at the same time, the participants in the conference call formed in step 82085 are (32133). Also, the two routes cut off in steps 82081 and 32082 are re-formed (2134, 2135>
, the conference call is terminated, the process returns to step 32001, and in order to resume the call between the office line 12 and one terminal device 70 before the conference call, the call is returned to the subroutine for calling response shown in FIGS. 19-12. enter.

In step 82013 (Figure 19-3), the 19th
-9 When it is confirmed that the subroutine for broadcasting shown in Figure 9 has ended (32013Y), the transmission line is transmitted from each terminal device 70 to the extension call circuit 200 via the reception circuit 150, and from the extension call circuit 200 to the broadcast circuit 700. (52141.2142, Figures 19-17), and - The transmission path from the broadcast circuit 700 to each terminal device 70 formed via each extension interface circuit 100 is cut off ( 82143>, return to step 2001.

In step 32014 (Figure 19-3), the 19th
- After confirming that the BGM broadcast in Figure 10 has ended (3
2014Y), the sound source circuit 720 makes sure that the transmission route of the signal 68 which is BGM is 5215L (Figs.
Disconnect the route to (32152>, step 200
Return to 1.

In step 52015 (Figure 19-3), the 19th
- In a call between the central office line and the terminal device 70 in Figure 12,
When the request for station line hold from the terminal device 70 is confirmed (S2
015Y), from the receiving circuit 150 to the central office line communication circuit 250
(32161, Figure 19-19)
, the hold tone signal 69 is sent to the central office line communication circuit 250 . 32162>, the process returns to step 2001.

In step 82016 (Figure 19-3), the 19th
- When it is confirmed that the terminal device 70 requests cancellation of the station line hold shown in Figure 9 (S2016Y), the transmission path of the signal 69 which is the hold tone is cut off and the transmission of the hold tone is terminated.
171, Figures 19-20), a transmission path is formed from the receiving circuit 150 to the central office line communication circuit 250 to resume communication.52
172), return to step 32001.

In step 82017 (Figure 19-3), the 19th
- 13 When there is a request from any of the terminal devices 70 to hold the extension during a call between the terminal devices 70 in the extension shown in FIG. No. 19-21
), the transmission line connecting the signal 69 to the extension call circuit 200 is turned on, and the hold tone that is the signal 69 is transmitted to the extension call circuit 200.
32182), and returns to step 32001.

In step 32018 (Figure 19-3), the 19th
- When the request to release the extension call on hold shown in Figure 21 is confirmed (52018Y), the extension call circuit 100 disconnects the transmission route of the hold tone (32191, Figures 19-22), and then the receiving circuit 150 transmits the extension call. A transmission path to the circuit 200 is formed to resume the call between the terminal devices 70 (32192), and when the call ends, the process returns to step 52001.

"Effect of the invention" As is clear from the above explanation, according to the present invention,
It is now possible to connect terminal devices without changing the circuit, not only when the distance from the main control device to the terminal device is short, but also over long distances, and it is also possible to provide many functions. In addition, despite the PCM conversion, it has become possible to realize an economical system even in a small scale. Therefore, the effects of the present invention are extremely large.

[Brief explanation of the drawing]

Figure 1A is a basic configuration diagram of the button telephone device; Figures 1B, 1C, 1D, and 1E are timing charts showing the waveforms of each part in Figure 1A; Figure 1F is the length of the transmission path. Fig. 1G is a diagram showing the principle configuration when the button telephone device according to the present invention is connected to a central office line, and Fig. 1H is a timing chart showing waveforms to explain why the button telephone device according to the present invention is limited. FIG. 11 is a diagram showing the principle configuration of an extension call trunk that enables communication between terminal devices of the present invention, and FIG. Fig. 1J is a principle block diagram of a broadcast trunk for simultaneously transmitting the same information to a large number of terminal devices connected to a key telephone device according to the present invention, and Fig. 2A is a diagram showing the principle structure of a broadcast trunk for simultaneously transmitting the same information to a large number of terminal devices connected to a key telephone device according to the present invention. A conceptual configuration diagram showing an embodiment of the main control device 10 including various circuits for realizing the various functions shown in the figure, and FIG. 2B is a terminal connected to the main control device 10 shown in FIG. 2A. 3A is a circuit configuration diagram showing an example of the extension interface circuit 100; FIG. 3B is the extension interface circuit 1 shown in FIG. 3A.
A timing chart showing the waveforms of each part of 00, Figure 3C is the extension interface circuit 1 shown in Figure 3A.
3D is a timing chart showing waveforms of each part of the code conversion circuit 110 shown in FIG. 3C, and FIG. 4A is a circuit diagram showing an embodiment of the code conversion circuit 110 included in A circuit diagram showing one embodiment; FIG. 4B is a timing chart showing waveforms of each part of the receiving circuit 150 shown in FIG. 4A; FIG. 5A is a circuit configuration diagram showing one embodiment of the D information transmitting/receiving circuit 170; FIG. 5B is a timing chart showing the waveforms of each part of the D information transmitting/receiving circuit 170 shown in FIG. 5A, and FIG.
FIG. 5D is a circuit diagram showing an embodiment of the information transmitting circuit 171; FIG. 5D is a circuit diagram showing an embodiment of the D information receiving circuit 180; FIG. 6B is a circuit diagram showing an embodiment of the multiplexer 210, FIG. 6C is a circuit diagram showing an embodiment of the S/S register 220, and FIG. 6D is a timing chart showing waveforms of various parts of the S/S register 220. , FIG. 6E is a circuit diagram showing one embodiment of the demultiplexer 227A, FIG. 6F is a circuit configuration diagram showing another embodiment of the extension communication circuit 200, and FIG. 6G is a circuit diagram showing one embodiment of the sending control circuit 240. Circuit diagram: FIG. 7A is a circuit configuration diagram showing an embodiment in which the office line communication circuit 250 is connected for communication between office lines; FIG. 7B is a circuit diagram showing an embodiment of the multiplexer 280; FIG. 7C is a circuit diagram showing an embodiment of the multiplexer 280; 7D is a circuit diagram showing another embodiment of the demultiplexer 270A, FIG. 7E is a circuit diagram showing another embodiment of the multiplexer 310, and FIG. 7F is a circuit diagram showing another embodiment of the demultiplexer 270A. The figure shows a circuit diagram of one embodiment of the transmission switching circuit 290 and a table showing the relationship between the switching signal and the output signal, FIG. 7G is a circuit configuration diagram showing another embodiment of the central office line communication circuit 250, and FIG. 8B is a circuit diagram showing an embodiment of the conference call circuit 350; FIG. 8B is a circuit diagram showing an embodiment of the multiplexer 360; FIG. 8C is a circuit diagram showing an embodiment of the multiplexer 361; 8D is a circuit diagram showing one embodiment of the S/P register 364A, FIG. 8E is a circuit diagram showing one embodiment of the multiplexer 380, FIG. 9A is a circuit diagram showing one embodiment of the adder 430, and FIG. 9B is a circuit diagram showing one embodiment of the multiplexer 380. 9C is a circuit diagram showing an example of the attenuation instruction circuit 460; FIG. 9D is a circuit diagram showing an example of the attenuation circuit 470; 9E is a circuit diagram showing an embodiment of the full adder 500; FIG. 9F is a circuit diagram showing an embodiment of the first adder 510; FIG. 9G is a circuit diagram showing an embodiment of the temporary storage circuit 610. Circuit diagram: FIG. 9H is a circuit diagram showing an embodiment of the second force adder 550; FIG. 91 is a circuit diagram showing an embodiment of the linear/nonlinear converter 650; FIG. 10A is a demultiplexing circuit 660. 10B is a circuit diagram showing one embodiment of the P/S register 661; FIG. 10C is a circuit diagram showing one embodiment of the demultiplexer 670; FIGS. 10D and 10E. 11 is a circuit diagram showing an embodiment of the broadcast circuit 700, FIG. 12A is a circuit diagram showing an embodiment of the sound source circuit 720, 128 is a circuit diagram showing an embodiment of the multiplexer 721, FIG. 13A is a circuit configuration diagram showing an embodiment of the CPU interface circuit 800, FIG. 13B is a circuit diagram showing an embodiment of the interrupt circuit 801, 13C is a timing chart showing the waveforms of each part of the interrupt circuit 801, FIG. 13D is a circuit diagram showing one embodiment of the address decoding circuit 810, and FIG. 13E is a timing chart showing the waveforms of each part of the address decoding circuit 810. 14A is a circuit diagram showing one embodiment of the 4-bit latch circuit 850, FIG. 14B is a timing chart showing waveforms of various parts of the 4-bit latch circuit 850, and FIG. 14C is a 3-bit latch circuit 850.・
A circuit diagram showing one embodiment of the latch circuit 900, FIG. 14D is a timing chart showing waveforms of various parts of the 3-bit latch circuit 900, and FIG. 14E is a 2-bit latch circuit 900.
14F is a timing chart showing waveforms of various parts of the 2-bit latch circuit 950; FIG. 15A is a circuit configuration diagram showing an embodiment of the timing circuit 100Q; 15B and 15C show timing circuit 1000.
15D is a circuit diagram showing an embodiment of the frequency dividing circuit 1090, FIG. 15E is a timing chart showing the waveforms of each part of the frequency dividing circuit 1090, and FIG. 15F is a frame・A circuit diagram showing an embodiment of the pulse circuit 1100, FIG. 15G is a timing chart showing waveforms of each part of the frame pulse circuit 1100, and FIG. 15H is a circuit diagram showing an embodiment of the multi-frame pulse circuit 1150. , FIG. 151 is a timing chart showing waveforms of each part of the multi-frame pulse circuit 1150, and FIG. 16A is a circuit showing an embodiment of the first transmission timing circuit included in the first to fourth transmission timing circuits 1200. 168 is a timing chart showing waveforms of each part of the first transmission timing circuit, and FIG. 16C is a circuit showing an embodiment of the second transmission timing circuit included in the first to fourth transmission timing circuits 1200. Figure 16D is a circuit diagram showing an embodiment of the third transmission timing circuit included in the first to fourth transmission timing circuits 1200, and Figure 16E is a circuit diagram showing waveforms of each part of the first to third transmission timing circuits. FIG. 16F is a circuit diagram showing an embodiment of the fourth transmission timing circuit included in the first to fourth transmission timing circuits 200; FIG. 16G is a waveform of each part of the fourth transmission timing circuit. 17A is a circuit diagram showing one embodiment of the reception timing circuit 1350; FIGS. 17B, 17C, and 17D are timing charts showing waveforms of each part of the reception timing circuit 1350; Figure 18A is the first. 188 is a circuit diagram of the first conference timing circuit included in the second conference timing circuit 1400. FIG. 188 is a timing chart showing waveforms of each part of the first conference timing circuit. FIG. A circuit diagram of the second conference timing circuit included in the second conference timing circuit 1400, FIG. 18D is a timing chart showing waveforms of each part of the second conference timing circuit, and FIGS. 19-1 to 19-22 are Main device 10 and CP
It is a flowchart showing the flow of operation of U20. 10... Main controller 11A, 11B... Office line interface 12A, 12
B... Station lines 13Δ, 13B... OR circuits 14A, 14B, 15A, 15B. 16A, 16B...Signal 20...CPU 21...Reset signal 22...Read signal 2
3...Write signal 25...Address bus signal (including signals 26-33) 35...Data bus signal (including signals 36-43)
50... Clock generator 51... Clock 60A-60F... Transmitter/receiver 61A-61F... Signals 63A-63C... Transmission lines 66-69... Signals 70, 70A-70E... Terminal devices 71A to 71C, 72A to 72C...Signal 100A to
100D...Extension interface 101...
OR gate 102...NOAH gate 103...CODEC 104...Resistor 105...Telephone 106
...Transistors 107, 108A, B, C, D to 109A, B. C, D... Signal 110... To code separation circuit 111 114... D flip-flop 115.11
6... Nando Gate 117-119... Noah Gate 120... Exclusive or Gate 121.
122... Inverter 131-140... Signal 150A-150D... Receiving circuit 151... D flip-flop 152.153... AND gate 154... OR gate 155.156... Inverter 161.162A-D...Signals 170A-170D...D information transmitting/receiving circuit 172...
・P/S register 173...AND gate 174...Inverter 177.178.179A-179D...Signal 180
...D information receiving circuit 181...8-bit shift register 182...
3-state buffer 200... extension call circuits 21OA, 210B... multiplexer 211...
8-bit multiplexer 1/212... 4-bit multiplexer 213... OR gate 214... Inverter 218A, 218B... Signal 22OA, 220B... S/S register 221...
8-bit shift register 222... AND gate 223... OR gate 225A, 225B... Signal 227A, 227B... Demultiplex 1 node 228
...Decoders 229-233...Inverters 235A, B-239A, B...Signals 24OA, 24
0B... Sending control circuit 241... AND gate 242... Inverter 248A, 248B... Signal 25OA, 250B... Office line communication circuit 251A, B~
257A, B...Signal 260A-260D...S/
S registers 268A to 268D...signals 27OA, 270B...demultiplexer 271...
・Decoders 272 to 278...Inverters 28OA, 280B...Multiplexer 281...
8-bit multiplexer 282... 4-bit multiplexer 283... OR gate 284... Inverter 288A, B... Signal 290... Output switching circuit 291, 292... AND gate 293...・OR gate 294...Inverter 298...Signal 310・
...Multiplexer 311...8-bit multiplexer 312...4
Bit multiplexer 313.314...AND gate 315.316...OR gate 317-321...Inverter 328.329...Signal 350...Conference call circuit 358...μ/ A switching signal 360...Multiplex circuit 361A, B, C...Multiplexer 362A, B,
C... Signal 364Δ, B, C... S/P register 365A, B,
C... Bus signal 366A, B, C ~ 373A, B, C... Signal 380
... Multiplexers 381-404 ... AND gates 406-408 ... OR gates 411-418 ... Resistor 420 ... Bus signal (including signals 421-42B) 4
30...Adder 440...Nonlinear/linear converter 441.442...ROM 445...Bus signal (including signals 446 to 458) 4
60... Attenuation instruction circuit 461-463, 467... OR gate 464-4
66...AND gate 469...Signal 470...Attenuation circuit 47
1 to 474...2-bit multiplexer 475...
・Bus signal (including signals 476 to 488) 500...
Full adder 510...First adder 511-514...Adder 516-528...Exclusive OR gate 530...Bus signal (including signals @531-544) 5
45...Signal 550...Second adder 55
1 to 554... Adder 556 to 569... Exclusive OR gate 571 to 583... OR gate 585... Bus signal (including signals 586 to 598) 6
10...-Hour storage circuits 611-614...Latch 616...Inverter 620...Bus signal (including signals 621-635) 6
50... Linear/nonlinear converter 652... Bus signal (including signals 653 to 659) 6
60... Demultiplex circuits 661A to 661C... P/S register 662...
Shift register 663...OR gate 664...AND gate 665...Inverters 668A to 668C...Signals 670A, 670B, 670C...Demultiplexer 671...Decoders 672 to 677... Inverter 679A, B, C ~ 684A, B, C... Signal 685
~690...OR gates 691-696...signal 700...-simultaneous broadcast circuit 701...OR gates 702-705...AND gates 711-715...signal 720... Sound source circuit 721... Multiplexer 722... Signal 725... S/S register 728... Signals 731-734... AND gates 736-739... Signal 800... CPU interface circuit 801.・・υ
J-included circuit 802...D flip-flop 803...NOR gate 804...Inverter 808...Signal 810
... Address decoding circuits 811 to 815 ... Decoder 816 ... Bus signals (including signals 817 to 820) 8
21... Bus signal (including signals 822 to 825) 82
6... Bus signal (including signals 827 to 833) 834
... bus signal (including signals 835 to 843) 844.
...Bus signal (including signals 845 to 847) 848...
・Signal 850...4-bit latch circuit 851-857...D flip-flop 858...
Inverter 859... Signal 860... Bus signal (including signals 861 to 864) 865... Bus signal (
(including signals 866 to 869) 870... bus signal (including signals 871 to 873) 875... bus signal 880... bus signal (including signals 881 to 884) 8
85... Bus signal (including signals 886 to 889) 89
0...Bus signal 900...3-bit latch circuits 901-909...D flip-flop 910...
Inverter 914...signal 915...bus signal (including signals 916-918) 920-922, 924
゜925.927... Bus signal 923... Bus signal (including signals 936 to 938) 9
26... Bus signal (including signals 931 to 933) 95
0...2-bit latch circuits 951-956...D flip-flop 957...
Inverter 958...signal 960-965...
Signal 920...bus signal (including signals 939 to 941) 9
27... Bus signal (including signals 942 to 944) 10
00... Timing circuit 1090... Frequency divider circuit 1091... Inverter 1096-1098... Signal 1100... Frame pulse circuit 1110.1111... Hexadecimal counter 1112.1
113...D flip-flop 1114...AND gates 1117-1119...Inverter 1120...Bus signal (including signals 1121-1124) 1125-1128...Signal 1150...Multi-frame pulse Circuit 1151.
1152... Hexadecimal counter 1153.1154...
- AND gates 1155 to 1160... Inverter 1170... Bus signal (including signals 1171 to 1175) 1176.1177... Signal 1200... 1st to 4th transmission timing circuit 1211.
...D flip-flop 1212.1213...AND gate 1221-1
226... Inverters 1231-1233... Signals 1241... 8-bit shift register 1242.
1243...D flip-flop 1244.1245
... To Nando Gool 1246-1247 ... AND gate 1248 ... OR gate 1251-1254 ... Inverter 1261-1269 ... Signal 1281.1282 ... D flip-flop 1283
．． 1284... Nando Gate 1291-1296.
...Inverters 1301-1304...Signals 1311-1313...AND gates 1316-1
318... Signal 1350... Reception timing circuit 1351... 8-bit shift register 1352~
1354...D flip-flop 1355-1359
...AND gates 1361-1363...Inverters 1371-1379...Signal 1400...First and second conference timing circuits 1411.
1412...Decoder 1413...NOR gate 1414.1415...NAND gate 1421-1
427...Inverter 1430...Bus signal (including signals 1431-1436) 1437-1439...Signals 1451-1454...D flip-flop 1455
．． 1456...Noah Gate 1458.1459...
- Inverter 1470... bus signal (including signals 1471 to 1473) 1475... bus signal (including signals 1476 to 1478) 1479 to 1482... signal 87 to BO... data information D...D Information P...P information.

Claims (3)

[Claims] (1) A central office line communication means for connecting to at least one central office line, an extension interface means for sending signals to each terminal device, and a receiving means for receiving signals from each of the terminal devices. , an extension communication means for enabling communication between the respective terminal devices; an information transmitting/receiving means for transmitting and receiving control information for connecting to a destination; and each frame of a plurality of frames included in the multi-frame. a start bit, a bit representing data information, and a bit representing parity information; a bit representing control information for connecting to the destination in at least one frame among the plurality of frames;
including frame synchronization information for obtaining frame synchronization in at least one frame in one multiframe,
Downlink information from the extension interface means to each terminal device, including at least bits representing data information, bits representing parity information, and bits representing control information for connecting to the destination, is received from each terminal device. The first half of each frame contains one of the downlink information and the uplink information, and the second half contains the other information, so that the mutual downlink information and uplink information included in each frame are A guard time, which is a time longer than the sum of the propagation time of the signal from the extension interface means to the terminal device and the propagation time of the signal from the terminal device to the receiving means, is provided between the downlinks. The timing of transmitting information from the extension interface means to each of the terminal devices, the timing of receiving the upstream information from the terminal device to the receiving means, and the timing of transmitting data information from and to the central office line to the central office line. The timing for sending and receiving data by the telephone communication means, the timing for transmitting data information from the office line communication means to the extension interface means, and the timing for transmitting the uplink information received by the reception means to the office line communication means and the extension communication means. the timing at which the extension communication means outputs this data information to the extension interface means upon receiving the data information included in the uplink information received by the receiving means; timing creation means for creating a timing that indicates to the information transmitting/receiving means the position of a bit representing control information for connecting to the destination included in the uplink and downlink information; The central office line communication means, the extension telephone communication means, and the information A button telephone device characterized in that it comprises transmitting and receiving means and central control means for transmitting to said receiving means. (2) The button telephone device according to claim 1, wherein the receiving means includes a delaying means for receiving the uplink information with a delay within the guard time. (3) The extension interface means transmits the downlink information using a signal of "1" or "0" by adding an odd numbered "1" and an even numbered "1" including the parity information. 2. The button telephone device according to claim 1, further comprising code separating means for separating and outputting the respective codes.