JPH01176121A - Fm reception circuit - Google Patents

Fm reception circuit

Info

Publication number
JPH01176121A
JPH01176121A JP33600387A JP33600387A JPH01176121A JP H01176121 A JPH01176121 A JP H01176121A JP 33600387 A JP33600387 A JP 33600387A JP 33600387 A JP33600387 A JP 33600387A JP H01176121 A JPH01176121 A JP H01176121A
Authority
JP
Japan
Prior art keywords
signal
frequency
output
controlled oscillator
voltage controlled
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP33600387A
Other languages
Japanese (ja)
Inventor
Atsushi Mori
淳 森
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP33600387A priority Critical patent/JPH01176121A/en
Publication of JPH01176121A publication Critical patent/JPH01176121A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To improve the quality of electric field information of a broadcast station by selecting a frequency of an output of a voltage controlled oscillator as twice the IF frequency, applying 1/2 frequency division, giving the result to a phase comparator in the state of locking an output of a voltage controlled oscillator and giving a frequency signal of the voltage controlled oscillator to a synchronous detector via an inverter and a 1/2 frequency divider. CONSTITUTION:A phase comparator 6, a low pass filter 7, a voltage controlled oscillator(VCO) 7, and a 1/2 frequency divider 9 form a PLL detector. The oscillating frequency of the VCO 7 is doubled to a frequency of the IF signal at locking. Since the synchronizing input signal of the synchronous detector 12 is synchronous with the IF signal by an inverter 10 and a 1/2 frequency divider 11 and the detected IF signal is a signal extracted from a mixer output, the detected output has a linearity with respect to the antenna input signal. Thus, the quality of the electric field information of a broadcast station is improved.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はFM受信機に関し特にシグナルメータ回路に関
する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an FM receiver, and more particularly to a signal meter circuit.

〔従来の技術〕[Conventional technology]

従来、この種のシグナルメータ回路はFM受信機の周波
数変換回路(ミキサ回路)より出力されたIF倍信号増
幅する多段のIF信号増幅回路のレベルを検波し、それ
ぞれのIF信号増幅回路より検波された信号を加算し、
シグナルメータ出力としている。
Conventionally, this type of signal meter circuit detects the level of a multistage IF signal amplification circuit that amplifies the IF signal output from the frequency conversion circuit (mixer circuit) of the FM receiver, and then detects the level of the multistage IF signal amplification circuit that amplifies the IF signal output from the frequency conversion circuit (mixer circuit) of the FM receiver. Add the signals and
It is used as a signal meter output.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来のシグナルメータ回路は、それぞれの工F
信号増幅回路が、FM信号を安定し受信するためリミッ
タ増幅器となっているため、その検波された信号もリミ
ッタがかかったような特性となり、更にその検波信号を
加算し、シグナルメータ出力としているため、第3図の
ように入力信号に対して直線的でないという欠点があっ
た。
The conventional signal meter circuit described above has each
Since the signal amplification circuit is a limiter amplifier to stably receive the FM signal, the detected signal also has the characteristics of a limiter, and the detected signal is further added to become the signal meter output. , as shown in FIG. 3, has the disadvantage that it is not linear with respect to the input signal.

〔問題点を解決するための手段〕[Means for solving problems]

本発明のシグナルメータ回路はIF比出力一方の入力に
加えられる位相比較器と該位相比較器の出力がローパス
フィルタを介して印加される電圧制御発振器とを供え、
該電圧制御発振器の発振出力を前記位相比較器の他方の
入力に加えて前記ローパスフィルタ出力にFM検波した
音声信号を取り出すPLL検波器を有し、前記電圧制御
発振器の出力をロック時にIF周波数の2倍の周波数と
し位相比較器の入力へは1/2分周を行い入力し前記電
圧制御発振器の周波数信号をインバータ及び1/2分周
器を介して同期検波器に送り同期検波の入力は周波数変
換のためのミキサ回路出力のIF倍信号して検波してい
る。
The signal meter circuit of the present invention includes a phase comparator to which an IF ratio output is applied to one input, and a voltage controlled oscillator to which the output of the phase comparator is applied via a low-pass filter,
It has a PLL detector which adds the oscillation output of the voltage controlled oscillator to the other input of the phase comparator and takes out the FM detected audio signal to the output of the low pass filter, and when the output of the voltage controlled oscillator is locked, the IF frequency is The frequency signal of the voltage controlled oscillator is doubled and input to the input of the phase comparator by dividing the frequency by 1/2, and the frequency signal of the voltage controlled oscillator is sent to the synchronous detector via the inverter and the 1/2 frequency divider. The IF multiplied signal of the mixer circuit output for frequency conversion is detected.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の一実施例のブロック図である。FIG. 1 is a block diagram of one embodiment of the present invention.

アンテナ1で受信した電波は高周波増幅回路2で増幅さ
れ、局部発振回路3の信号により、ミキサー回路4で周
波数変換され、IF倍信号なる、IF倍信号IF増幅回
路5で増幅され位相比較器6の入力となる。位相比較器
6、ローパスフィルタ7、電圧制御発振器(VCO)7
.1/2分周器9はPLL検波器を形成する。VCO7
の発振周波数はロック時IF信号の2倍となっている。
The radio waves received by the antenna 1 are amplified by a high frequency amplifier circuit 2, frequency-converted by a mixer circuit 4 based on the signal from a local oscillation circuit 3, and the IF-multiplied signal is amplified by an IF-multiplied signal by an IF amplification circuit 5 and a phase comparator 6. becomes the input. Phase comparator 6, low pass filter 7, voltage controlled oscillator (VCO) 7
.. The 1/2 frequency divider 9 forms a PLL detector. VCO7
The oscillation frequency of is twice that of the IF signal when locked.

10はインバータ、11は172分周器で、これらによ
り同期検波12の同期入力信号はIF倍信号同期し、検
波されるIF倍信号ミキサー出力より取り出された信号
としているため、第3図のように、検波出力はアンテナ
入力信号に対して直線性を持つ。なお、13はシグナル
メーター出力の周波数を低くするローパスフィルタであ
る。
10 is an inverter, 11 is a 172 frequency divider, and the synchronized input signal of the synchronous detection 12 is synchronized with the IF multiplied signal, and the signal is taken out from the detected IF multiplied signal mixer output, as shown in Figure 3. In addition, the detection output has linearity with respect to the antenna input signal. Note that 13 is a low-pass filter that lowers the frequency of the signal meter output.

第2図は本発明の他の実施例のブロック図である。第1
図とのちがいはミキサー出力と同期検波入力との間に、
帯域制限を行うフィルター15が挿入されている。本ブ
ロック図では帯域制限された同期検波となるため隣接局
に信号がある場合シグナルメータ出力に隣接局の信号情
報が入りにくいという利点がある。
FIG. 2 is a block diagram of another embodiment of the invention. 1st
The difference from the diagram is that between the mixer output and the synchronous detection input,
A filter 15 for band limiting is inserted. In this block diagram, since band-limited synchronous detection is used, there is an advantage that if there is a signal from an adjacent station, the signal information of the adjacent station is difficult to enter into the signal meter output.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明はシグナルメータ出力がアン
テナ入力信号に対し直線性をもつため、放送局の電界情
報の質が良くなり、受信機において、ごの周波数に放送
局があり、しかも、その強さの順位を比較することが要
易となり、受信機のマイクロコンピュータ制御により、
受信放送局の順位付けが要易になるという効果がある。
As explained above, in the present invention, since the signal meter output has linearity with respect to the antenna input signal, the quality of the electric field information of the broadcasting station is improved. It becomes easy to compare the ranking of strength, and the microcomputer control of the receiver allows
This has the effect of making it easier to rank receiving broadcast stations.

マタ、13のローパスフィルタの帯域をひろげIF倍信
号AM成分を取り出すことも可能であり、IF倍信号A
M成分はマルチパス情報や外部ノイズ情報となるため、
検波の直線性が良いということはその情報の質も良いと
いうことになる。
It is also possible to widen the band of the 13 low-pass filters and extract the IF multiplied signal AM component, and the IF multiplied signal A
Since the M component is multipath information and external noise information,
Good linearity of detection means that the quality of the information is also good.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図および第2図はそれぞれ本発明の実施例を示すブ
ロック図、第3図は本発明によるシグナルメータ出力図
である。 1・・・・・・アンテナ、2・・・・・・高周波増幅回
路、3・・・・・・局部発振回路、4・・・・・・ミキ
サー回路、5・・・・・・IF増幅回路、6・・・・・
・位相比較器、7・・・・・・ローパスフィルタ、訃・
・・・・電圧制御発振器、9,11・・・・・・1/2
分周器、10・・・・・・インバータ、12・・・・・
・位相検波器、13・・・・・・ローパスフィルタ、1
4・・・・・・音声増幅器、15・・・・・・帯域フィ
ルタ。 代理人 弁理士  内 原   晋 V 、$ l 閉 $ 2 回
FIGS. 1 and 2 are block diagrams showing embodiments of the present invention, and FIG. 3 is a signal meter output diagram according to the present invention. 1...Antenna, 2...High frequency amplification circuit, 3...Local oscillation circuit, 4...Mixer circuit, 5...IF amplification circuit, 6...
・Phase comparator, 7...Low pass filter,
...Voltage controlled oscillator, 9, 11...1/2
Frequency divider, 10... Inverter, 12...
・Phase detector, 13...Low pass filter, 1
4...Audio amplifier, 15...Band filter. Agent: Patent Attorney Susumu Uchihara, $l Closed $2

Claims (1)

【特許請求の範囲】[Claims] IF出力が一方の入力に加えられる位相比較器と、該位
相比較器の出力がローパスフィルタを介して印加される
電圧制御発振器とを備え、該電圧制御発振器の発振出力
を前記位相比較器の他方の入力に加えて前記ローパスフ
ィルタの出力にFM検波した音声信号を取り出すPLL
検波器を有するFM受信回路において、前記電圧制御発
振器の出力をロック時にIF周波数の2倍の周波数とし
位相比較器の入力へは1/2分周を行い入力し、前記電
圧制御発振器の周波数信号をインバータ及び1/2分周
器を介して同期検波器に送り、同期検波の入力は周波数
変換のためのミキサー回路出力のIF信号として検波し
、この検波信号を電界強度情報であるシグナルメータ出
力とすることを特徴とするFM受信回路。
A phase comparator to which an IF output is applied to one input, and a voltage controlled oscillator to which the output of the phase comparator is applied via a low-pass filter, and the oscillation output of the voltage controlled oscillator is applied to the other input of the phase comparator. PLL which extracts the FM detected audio signal to the output of the low pass filter in addition to the input of the
In an FM receiving circuit having a wave detector, the output of the voltage controlled oscillator is made to have a frequency twice the IF frequency when locked, and the frequency is divided into 1/2 and inputted to the input of the phase comparator, and the frequency signal of the voltage controlled oscillator is inputted to the input of the phase comparator. is sent to a synchronous detector via an inverter and a 1/2 frequency divider, and the input of the synchronous detection is detected as an IF signal of the mixer circuit output for frequency conversion, and this detected signal is sent to the signal meter output, which is electric field strength information. An FM receiving circuit characterized by:
JP33600387A 1987-12-29 1987-12-29 Fm reception circuit Pending JPH01176121A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP33600387A JPH01176121A (en) 1987-12-29 1987-12-29 Fm reception circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP33600387A JPH01176121A (en) 1987-12-29 1987-12-29 Fm reception circuit

Publications (1)

Publication Number Publication Date
JPH01176121A true JPH01176121A (en) 1989-07-12

Family

ID=18294688

Family Applications (1)

Application Number Title Priority Date Filing Date
JP33600387A Pending JPH01176121A (en) 1987-12-29 1987-12-29 Fm reception circuit

Country Status (1)

Country Link
JP (1) JPH01176121A (en)

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