JPH01175438A - Block synchronization system by start-stop synchronization - Google Patents

Abstract

PURPOSE:To increase the use efficiency of a line and to set the best termination monitoring time corresponding to a line speed automatically by setting a basic time for block termination detection corresponding to transmission unit bits and detecting block termination from the continuance of a mark state. CONSTITUTION:A transmission-side device sends data without inserting a mark state which is >=n times transmission unit bits between sent data in the same block and inserts a mark state which is >=n times the transmission unit bits at the end of one block of data. The block termination detecting mechanism 15 of a line control part 1 makes a termination bit counter 19 counts up by one every time a timer signal is applied from a timer mechanism 14. When a mark state appears after a final character is received, this mark state continues by >=n bits, so the counter value of the termination bit counter 19 exceeds (n) and when the value of the counter 19 becomes equal to the block termination detection value (n), the block termination detecting mechanism 15 sends interruption indicating the end of block reception to a central processor 2 through a common bus 4, thereby indicating the termination of the block.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a data transmission method between systems that performs data transmission via an asynchronous communication line, and in particular, the present invention relates to a data transmission method between systems that performs data transmission via an asynchronous communication line. This relates to a block synchronization establishment method that synchronizes blocks by determining the mark state of 0 times .

[Conventional technology]

Conventionally, in systems that perform data communication using a start-stop synchronization communication line, there is a professional system that detects the end of data transmission of a block (a group of data transmitted at one time) and synchronizes the blocks. There is the following method.

■Block termination character method This method uses a specific character to terminate a block, and the carriage return (C
R), line feed (LF).

Use End' of Text (ETX), etc. An example of the wooden method is the JIS C6326r basic data transmission control procedure. In this method, non-code data such as image information (hereinafter referred to as binary data) in which a block termination character may exist in the transmission data cannot be transmitted using the above method.

Therefore, transmission extension characters such as data link escape code (DLE) are used to enable the transmission of binary data. In other words, if the sending side sends the same character as the transmission extension character, the transmission extension character is sent twice consecutively, and the receiving system ignores the first transmission extension character, and if the second character is the end-of-block character, it sends the same transmission extension character twice. Block termination and transmission extension characters are processed as transmission data, making it possible to transmit binary data as well.

■Fixed block length method This is a method in which the transmission block length is fixed and consecutive fixed length characters are regarded as one block. This method is also capable of transmitting binary data.

■Variable-length block method This is a method in which a data length is set at the beginning of a transmission block, and up to the specified data length is considered a block, and binary data can also be transmitted.

(2) Timer monitoring method If data is not received for n times the basic timer value after data is received, the block is considered to have ended. This method is a control method typified by the bucket, 71, and transmission timing of the packet assembly and division function (PAD) of CCITT Recommendations X, 28 and X, 3, and is also capable of transmitting binary data.

[The problem that the invention attempts to solve]

The above conventional technology has the following problems.

■Block termination character method In both transmission and reception, it is necessary to determine whether all transmitted data Q is a block termination character, which complicates the processing of the communication control device and increases the processing load. Not suitable.

Furthermore, since transmission extension characters such as DLE have to be transmitted extra, there is also the problem that line usage efficiency decreases.

■Fixed block length method Is this method suitable for block transmission of binary data? It is not suitable for general communication because the data length must always be fixed, and it is not versatile.

■Variable block length method It is also possible to transmit binary data, and the transmission data length can be arbitrary.

However, when the data length is short, line usage efficiency tends to decrease, and processing becomes complicated when data cannot be received normally due to a line failure.

■Timer monitoring method If the line speed is high, the line usage efficiency will deteriorate unless the block end judgment time is shortened, so in a system that accommodates multiple lines such as a host computer, the basic timer value for block end judgment is not connected. The setting must be based on the maximum line speed among the multiple lines set. For example, when a line with a line speed of 1200°4800.9600 bps is accommodated, the basic timer value is set to 9600 bps in the communication control device that controls data exchange between terminal devices connected to the host computer. , must be 1/960 seconds or less. So °C19600bps
When the basic timer timeout is repeated 0 times for a 4800 bps line, when it is repeated zXn times for a 4800 bps line, and 8
When lil is repeated, it must be determined that the block has ended each time. Such a short basic timer significantly increases the load on the communication control device and reduces the amount of data that can be processed. Furthermore, if the line speed is changed, it becomes necessary to change the n value. Furthermore, if a basic timer is provided for each line individually, the amount of hardware will increase.

The present invention has been made in view of these circumstances,
The purpose of this is to automatically set the optimum block end monitoring time according to the line speed, to have a simple block end detection hardware configuration with a small amount of hardware, and to enable efficient line data transmission. The object of the present invention is to provide a method for establishing program synchronization that allows for

[Means for solving problems]

In order to achieve the above object, the present invention provides a system in which data communication is performed between a transmitting side device and a receiving side device via an asynchronous line. In this case, a means for transmitting without inserting a mark state of n times the transmission unit bit or more between transmission data in the same block, and inserting a mark state of 0 times or more of the transmission unit bit at the end of data transmission of one block. and the receiving side device is provided with means for determining whether or not a mark state continues for more than n hits of a transmission unit hint between data received from the asynchronous line, and determining that the block has ended if it continues. , the same jtJi of a block is established based on the presence or absence of a mark state of n times or more the transmission unit hit.

[Effect]

The basic time for detecting the end of a block is set to correspond to the jiii bit of the transmission, and the transmitting side device
When the mark state is sent for twice the time, the receiving device determines that the block has ended by determining that the mark state has continued for a time equal to the transmission unit hit x n or more.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment in which the present invention is applied to a terminal device. The central processing unit 2 and the main memory 3 are connected via a common lotus 4, and
A terminal device in which a control unit 1 is connected to an asynchronous line 5 via a connector 6 is shown.

The line control unit l includes a start bid/nod detection mechanism 11. Binoto Zambling Mechanism 12. Clock mechanism 14 that outputs a timer signal every unit bit time. Block end detection mechanism 15. Serial-parallel conversion mechanism 16.
Block reception status flag 175 used to determine the end of a block Character reception status flag 18 indicating the reception status of characters.
It consists of a termination counter 19 for counting the timer signal output from the clock mechanism 14, and a start bit detection mechanism 11. Hino I Sunprinter Mechanism 12. human output mechanism] 3 is connected to the connector 6, and the clock mechanism 14 is connected to the binot sample ring mechanism 12. Bit sending mechanism 13. Connected to the floc end detection mechanism 15, via 1-sampling mechanism 12. The bit sending mechanism 13 is connected to the serial-to-parallel conversion mechanism 16, and the serial-to-parallel conversion mechanism 16. A block end detection mechanism 14 is connected to the common lotus 4.

FIG. 2 shows the hit pattern on the asynchronous line 5 and changes in the block reception status flag 17 and character reception status flag 18 when data is transmitted according to the present invention. In Fig. 2, one character has one start bit and eight data bits.

It has a 1 stop bit configuration. As shown in FIG. 2, in asynchronous data transmission to which the present invention is applied, the hit pattern on the line of one transmission block starts from the start hit of the first character, and the stop hit of the last character is 1 & n bits or more. It is configured to end at the mark (8iii principle "'1" focus). In addition to stop bits and start bits, mark states of less than n bits can be inserted between each character. Below, based on FIG. 2, the transmission operation of the terminal device in FIG. 1 receives one character.

The operation of determining the end of a flock will be explained.

First, the transmission operation will be explained. When transmitting data, the central processing unit 2 applies the transmission data stored in the main storage device 3 to the serial-to-parallel conversion mechanism 16 via the common lotus 4 at a predetermined timing.

The serial-parallel conversion mechanism 16 converts this into a serial hint string and then sends it to the hit sending mechanism 13. The hit sending mechanism 13ij transmits the signal to the asynchronous line 5 via the connector 6 in accordance with the timer signal from the clock mechanism 14. Furthermore, the bit sending mechanism 13 is a serial-to-parallel converting mechanism 16.
The start bit and stop bit are also added according to instructions from . In data transmission as described below, the central processing unit 2 controls the timing of data transmission so that the mark state of n or more hits does not continue in one block, and when the data transmission of one block is completed, the central processing unit 2 The block is terminated by keeping the line in the marked state for a time longer than n times the unit bit.

Next, the character reception operation is performed as follows.

The start hit detection mechanism 11 monitors the state of the asynchronous line 5 via the connector 6. When the star 1-bit is detected, the start focus detection mechanism 11 instructs the bit sampling mechanism 12 to start hint sampling and the clock mechanism 14 to start clocking for reception, and performs block reception as shown in FIG. Status flag 17. Turn on the character reception status flag 18.

The bit sampling mechanism 12 starts hint sampling based on a timer signal outputted from the clock mechanism 14 every time corresponding to transmission i1i.

The bit-sampled hints are sent to the serial-to-parallel conversion mechanism 16, assembled into 8-bit characters, and then stored in the receiving area in the 1a device 3 via the common lotus 4. After the bit sampling mechanism 12 sends the data focus to the 8-bit 1 to the serial-parallel conversion mechanism 16, it checks the stop bit and turns off the character reception status flag 18 as shown in FIG. This completes the reception operation for one character, and if the second and subsequent characters are not to be received, the same operation as described above is repeated.

On the other hand, in parallel with the above operation, the block end detection mechanism 15 constantly judges whether the block reception state flag 17 is on and the character reception state flag 18 is off, and if so, the Timer signal from time mechanism 14 (this is bit sampling mechanism 12.Hino) / Sending mechanism 1
(This is the same as the timer signal sent in step 3) The end hit counter 19 is incremented by 1 each time the power output changes, and if the block reception status flag 17 is off or the character reception flag fcF flag 18 is on. , Termination
An operation is performed to maintain the counter 19 at O.

Therefore, when a mark state appears between characters, the block reception state flag 17 is turned on and the character reception state flag 18 is turned off, so that the block end detection mechanism 15 counts up the end hit counter 19. However, as mentioned above, since the transmitting side is configured not to insert mark states of n or more times between characters in one tree block, before the value of the signature bit counter 19 reaches the end-of-flock detection value n. The character reception status flag 18 is turned on. Therefore, the block end detection mechanism 15 sets the end bit counter 19 to O.
and the counter value of the final bit counter 19 does not reach n or more.

On the other hand, if a mark state appears after receiving the last character, this mark state continues for n bits or more, so that the counter value of the final bit counter 19 exceeds n. The block end detection mechanism 15 monitors whether the value of the end pick I/counter 19 has become equal to the block end detection value n, and when it becomes equal, the block reception end is sent to the central processing unit 2 via the common lotus 4. The end of the block is notified by generating a fill-in without indicating the end of the block. Then, the block reception status flag 18 is turned off to prepare for reception of the next block.

Although the above embodiments apply the present invention to a terminal device, the present invention can be widely applied to other transmitting and receiving devices that perform asynchronous data transmission, such as a communication control device connected to a host computer. [Effects of the Invention] As explained above, the present invention detects the end of a block based on the duration of the mark state, similar to the conventional timer monitoring system, so that it can be used even when transmitting binary data. Line usage efficiency can be increased.

Furthermore, since the basic time for block end detection is set in the transmission unit bit, it is possible to automatically set the optimal block end monitoring time according to the line speed even if n is fixed. Therefore, when the present invention is applied to a communication control device or the like that accommodates multiple lines with different transmission speeds, the load on the program is reduced.

Furthermore, since the time equivalent to a transmission unit hit can be obtained by a timer mechanism that is essential for a start-stop jl1 type communication mechanism, this timer mechanism can also be used for block end detection, reducing the amount of hardware involved. can do.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a terminal device to which the present invention is applied, and FIG. 2 is a diagram showing bit patterns of transmission data on a line. In the figure, 1... line control section 4... common lotus 2.
・Central processing unit 5 ・Start-stop synchronization line 3 ・
...Main 'L'l device 6...Connector 11...Star 1~Bit detection mechanism 12...Hint sampling mechanism 13...Bit sending mechanism 14...Clock mechanism 15...Block Termination detection mechanism 16... Serial-parallel conversion mechanism 17... Block reception status flag 18... Character reception status flag 19... Termination bit counter

Claims (1)

[Scope of Claims] In a system in which data communication is performed between a transmitting side device and a receiving side device via an asynchronous line, when data is transmitted to the transmitting side device on the asynchronous line, the transmission side device transmits data to the same block. Transmission is performed without inserting a mark state of n times the transmission unit bit or more between the transmission data in the block, and means is provided for inserting a mark state of n times or more of the transmission unit bit at the end of data transmission of one block; The side device is provided with means for determining whether or not the mark state continues for more than n transmission unit bits between the data received from the asynchronous line, and determining that the block has ended if the mark state continues for n bits or more of the transmission unit bits; A method for establishing block synchronization using start-stop synchronization, characterized in that block synchronization is established depending on the presence or absence of a mark state of n times or more.