JPH01174165A - Image data processing unit - Google Patents

Abstract

PURPOSE:To execute direct magnification and reduction to a compressed data by subtracting repetitively a reciprocal of designated magnification from run length information till the result of reduction reaches zero or negative and outputting the same color information by the number of times of subtraction. CONSTITUTION:An MH code inputted to a signal line 1 is decoded by a decode section 2 and the outputted color information is latched in a register 22 and a run length is latched by a register 10 respectively as the result of decoding. Then a reciprocal of a multiple given to the register 13 is subtracted from the content of the register 10 by a subtractor 16 synchronously with the clock CLK and the result of subtraction is latched in the register 10. The subtraction is implemented until the result of subtraction reaches '0' or negative and the color information latched in the register 22 is outputted by the number of times of subtraction. Thus, the image data magnified and reduced is obtained according to the said designation multiple.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention simultaneously executes decompression processing (encoding/decoding processing) of image data compressed in the -dimensional direction and processing of enlarging/reducing the image according to a specified magnification. The present invention relates to an image data processing device that enables image data processing.

(Prior Art) Conventionally, when compressed data is expanded and image data obtained by the same process is enlarged or reduced, these processes are performed separately. That is, as shown in FIG. 6, compressed data is once expanded into image data, and the expanded image data is subjected to enlargement/reduction processing.

Therefore, unless a special architecture such as vibline processing is adopted, decompression and enlargement/reduction cannot be performed in parallel, and therefore the processing time becomes the sum of the two processing times: decompression processing and enlargement/reduction processing. It ends up. In addition, if the size of the image data after expanding the original image is constant even if pipeline processing is performed, the bus Bus-A in FIG.
The amount of data flowing through is constant, and the processing time is determined by this transfer rate during reduction. Conversely, this means that it takes four times as long to display A4 18 lines/mu data as it does to display A4 8 lines/mm data on an A4 8 lines/mm display. Become.

As a specific example, M H (Modify
Consider the dllaff[1Ian) code. A) in Figure 2
When the code of ~(F) is expanded, 20 on the input side of Figure 5
This is an image of bits (20 bits). If the bus BLIS-A in FIG. 6 has 1 bit, 20 cycles are required to process this 20 bits. In the case of enlargement, the output is greater than the input, so the processing time varies depending on the magnification.

(Problems to be Solved by the Invention) As described above, conventionally, when compressed data is decompressed and image data obtained by the same process is enlarged or reduced, after decompressing the compressed data, the image data is Expansion processing and expansion/reduction processing are applied to the image.
The two reduction processes were performed separately. Therefore, the processing time becomes the sum of the two processing times of decompression processing and enlargement/reduction processing, making it impossible to realize high-speed image processing.

Therefore, in order to achieve high-speed image processing, decompression processing and enlargement/
It is conceivable to perform the reduction processing in parallel using a pipeline processing mechanism, but in this case there is a problem that the processing mechanism becomes complicated and expensive, and the overall processing speed cannot be expected to improve much.

The present invention has been made in view of the above-mentioned circumstances, and has a relatively simple and inexpensive configuration without employing a special architecture such as pipeline processing. An object of the present invention is to provide an image data processing device that can simultaneously perform enlargement and reduction processing.

[Structure of the Invention] (Means for Solving the Problems) The present invention does not expand or reduce compressed data once and then expand or reduce the image data directly from the compressed data according to a specified magnification. The method is to obtain color information and run length information from compressed data, subtract the reciprocal of the specified magnification from the run length information, repeat the subtraction until the result becomes zero or negative, and calculate the number of subtractions. and means for outputting the same color information as the above color information.

(Operation) Decode the compressed data to obtain color information and run length information, subtract the reciprocal of the specified magnification from the run length information, and repeat the subtraction until the result becomes zero or negative, for the number of times of subtraction. Output the same color information as the above color information,
Obtain image data according to the specified magnification. With this kind of image processing, −
It becomes possible to simultaneously perform decompression processing of image data compressed in the dimensional direction and processing of enlarging/reducing the image according to a specified magnification. Furthermore, since there is no need to once generate image data before reduction during reduction, if the manual speed of the compressed data is sufficiently fast, the processing time will be shorter as the reduction ratio becomes larger, which is faster than the pipeline processing shown in Figure 6. High-speed processing becomes possible.

(Example) An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit block diagram showing one embodiment of a device according to the present invention. Here, an MH code is taken as an example of the input one-dimensional compressed code.

In the figure, ■ is a signal line for inputting a compressed code to be expanded (decoded) and expanded/reduced, that is, an MH code as shown in FIG. 2 here. 2 is a decoding unit that decodes the MH code and outputs run length information on the signal line 3 and color information (white or black is expressed as "L" or "H") on the signal line 4. It is. 5 is an AND gate provided corresponding to each bit of run length information (hereinafter simply referred to as run length), and when the signal line 19 is "H" (high level), the manually inputted run length is directly signaled. line 6
When the signal line I9 is "L" (low level), the output to the signal line 6 is set to "0" (all bits are "L").

7 is an adder that adds the data on the signal line G output from the AND gate 5 and the output data 17 of the subtracter 1B, and outputs the sum to the signal line 8. If the sum is "0" or less, "H" is output to the signal feedback line 9. lO is signal line 1
This is a register that latches input data in synchronization with the clock (CLK) of 1, and the sum on the signal line 8 obtained from the adder 7 is placed in the upper part, and the decimal part of the difference from the subtracter 16 (described later) is placed in the lower part. They are respectively input, latched, and output to the signal line I2. 18 is a register for setting the reciprocal of the specified magnification for decoded image data.

The output of this register 13 is input to the AND gate 14, and when the signal on the signal line 21 is "L", it is masked and the signal output line 15 of the same gate becomes "0", and the signal line 21
When is “H”, the contents of the register 13 are output to the signal line 15. 16 is a subtracter that subtracts the content of the output signal line I5 of the AND gate I4 from the content of the output signal line I2 of the register IO.

Here, the accuracy of the magnification is assumed to be 16 bits for the integer part and 16 bits for the decimal part. In this case, register 13 is 32 bits wide. Since the run length information is an integer, signal line 3,
6.8 are each 16 bits wide.

The subtraction result of the subtracter 16 is 32 bits, and the integer part 16
The bits are connected to signal line 17, and the 16 bits of the decimal part are connected to signal line 18.
Output each. Also, as a result of the above subtraction, the difference is “0”
'', outputs H'' to the signal line 19. Then, the integer part data on the signal line 17 is input to the adder 7, and the decimal part data on the signal line 18 is input to the lower register 10. The output signal line 12 of register 1o is 32 bits wide.

20 is a logic circuit that determines the output of the next cycle;
The signal state is outputted to 21. 22 is a register that latches the color information on the signal line 4 output by the decoding section 2, and the signal line 19 is set to "H" in synchronization with the clock (CLK).
When the signal line 19 is at "L", the value on the signal line 4 is latched, and when the signal line 19 is at "L", it is held. 23 is the output of the register 22.

When the output of the register 22 is valid, the signal line 21 is “L”.
"become.

Note that the input signal line l of the MH code moves to the next cycle when the signal line 19 is at "H". That is, a clock (C
When LK) is input, the following code is given. When the decoder 2 receives an input, it outputs the run length to the signal line 3 and the color information to the signal line 4 within the same cycle. It is assumed that the input (MH code) does not change when the signal line 19 is "L".

2 to 5 are for explaining the operation of the above embodiment, respectively, and FIG. 2 is a diagram showing an example of a human cover turn of the MH code input to the signal line 1.

Figures 3 and 4 respectively show the signal lines (3, 4, 6, 9, 12, 15, 17, 18, 19°2) shown in Figure 1 above.
1, 23) is a diagram showing the relationship between the above signal states and operation steps 81 to SIO, where (17, 18) is the integer part signal line (bus) 17 and the decimal part signal line (bus) I8.
means the number of pairs read. The same applies to (8, 18). Note that here, data (numeric values) expressed by multiple-bit signal lines (buses) are expressed in decimal notation, and 1-bit signals are expressed in H/L.

FIG. 5 shows the relationship between the input dot pattern and the output dot pattern. Here, an example is shown in which the one-dimensional dot pattern according to the input pattern shown in FIG. 2 is multiplied by 215 and output.

The operation of one embodiment of the present invention will now be described with reference to FIGS. 1 to 5.

In explaining the operation of one embodiment of the present invention, the principle of operation of the present invention will be explained.

In the case of MF code, by decoding it, the color (
white or black) and its run length.

In the present invention, any code other than the MH code may be used as long as the color and run length can be obtained by decoding it, but the MH code is taken up here as a representative example.

The present invention subtracts the reciprocal of the magnification from the run length obtained as described above, repeats the subtraction until the result becomes "0" or negative, and outputs the color. For example, the color is white and the run length is "4"! When reducing the size to /2, the reciprocal of the magnification (1/2) is 2, so 2 can be subtracted twice, so the output is 2 white.
Outputs dots.

Also, when expanding the same input data twice, 4-0.
5-3. 5 3. 5-0. 5-3 3-0. 5-2. 5 2, 5-0. 5-2 2-0. 5-1. 5 1.5-屹 5-1 1-0. 5-0. 5 0, 5-0. 5-0 In this case, since 0 and 5 can be subtracted 8 times, it is sufficient to output 8 dots of white.

If the result of subtracting the reciprocal of the magnification is "0" or negative, obtain the color and run length of the next code, and add the run length to the previous subtraction result. Then, the reciprocal of the magnification is repeatedly subtracted from the addition result.

By repeating this process, expansion and reduction can be performed simultaneously with expansion.

When the circuit of FIG. 1 is made to correspond to the above-mentioned operating principle, the MH code input to the signal line 1 is decoded by the decoder 2, the color information is output to the signal line 4, and the run length is output to the signal line 3. . Then, the color information is latched into the register 22, the run length is latched into the register 10, and the following code is applied to the input signal line 1. Then, in synchronization with the clock (CLK), the subtracter 16 subtracts the reciprocal of the multiple given to the register 13 from the contents of the register 10, and the subtracted result is latched in the register IO. Also, the subtraction result is “0”
Or, if it becomes negative, the next run length information is added by the adder 7 and the result is latched in the register 10. The reduced/enlarged results are output to the signal line 23, but since the output results are not always obtained in each cycle (details will be described later), it is important to check whether the data being output to the signal line 23 is valid or not. A signal line 21 exists as an output indicating. Therefore, the image data that is output is the signal line 21.
is “H”, the color output on the signal line 23 is clocked (CL
This can be obtained by latching in synchronization with K).

Next, specific operations according to the embodiment will be explained. Here, the MH code shown in Fig. 2 is given to the circuit shown in Fig. 1, and it is
Consider the case of multiplying by 5. Since the magnification is 215 times, the reciprocal number r2.5J is set in the register 13. Also,
As an initial state, registers 20 and 22 are set to "L" and register 10 is set to "0". Then, the first human input (MH code) on the signal line 1 is decoded by the decoder 2, and "5" is displayed as run length information on the signal line 3, and "white" is displayed on the decoder 2. It is assumed that color information "L" is output. The operation after this state will be explained with reference to FIG.

FIG. 3 shows the values of each part for each operation step synchronized with the clock (CLK). The subsequent operation will be explained along the cycle shown in FIG.

Note that each step St, S2 . S3. ... SlO
A clock (CLK) is generated during this period.

Since the output signal line 21 of the S-digital meta 20 is "L2", the output signal line 15 of the AND gate 14 is "0", and the subtraction results are also ro, OJ (signal lines 17 and 18 are both rOJ
), the signal line 19 becomes "Hl". As a result, the first run length "5" outputted from the decoding section 2 is outputted to the signal line 6 via the AND gate 5, and further to the signal line 17.
It is supplied to the adder 7 together with the subtraction result data "0" of the integer part above and added.

As a result of this addition, "5" appears on the output signal line 8 of the adder 7.
is output, and this data is then used as the first clock (C
LK) is latched into register IO in synchronization with LK. Also, at this time, since the signal line 19 is "H", color information "L" indicating white, which is the first color on the signal line 4 outputted from the decoding section 2, is manually inputted to 22. Furthermore, since the output signal line 8 of the adder 7 is "5", the sign output signal line 9 of the adder 7
becomes “L” and the register 20 becomes “H” in the next cycle.
is set to Therefore, in the next cycle, the output signal line 21 of the logic circuit 2 becomes "H", indicating that the "white"("L") color information output from the signal line 23 is valid. The input data (MH code) on I is also shifted by 4 bits and decoded by the decoder 2, and in the next cycle, "3" is placed on the signal line 3 as the run length, and black "H" is placed on the signal line 4 as the color information. is obtained.

82-54 As in the case of SL, when the subtraction result is "0" or less, that is, when the signal line 19 is "H", the next run length is added and set in the register 10, and the color information is stored in the register 22.
Set to . If the subtraction result is positive, that is, signal line 1
When 9 is "L", the reciprocal of the magnification (value of register 13) is subtracted from the contents of register IO.

If the result of subtraction is negative, and the result is negative even after adding the next run length (signal lines 19 and 9 are both H#), the data for that run length is ignored as it has been lost due to reduction. do. Therefore, the next clock (CLK
) sets the register of the logic circuit 20 to "L", indicating that the output of the register 22 is invalid. That is, this logic circuit 20 performs so-called thinning-out reduction in which unselected input bits are ignored during reduction. As a result of adding the run lengths, some processing is performed without discarding the data while the signal line 8 is negative, and the next color (value of register 22) is
By determining this, reduction other than thinning out can be performed.

Since the signal line 21 is at "L", the output signal line 15 of the AND gate 14 is at "0". From this, the next run length is directly added to the value (-1, 0) of the register IO. This time, since signal lines 8 and 18 are positive, the next clock (C
LK), the register of the logic circuit 20 becomes "H".

87-5lO Performs the same processing as 82-S4 and outputs the reduction result.

In the above process, when the color information output signal line 23 when the output signal line 21 indicating that the color information output (value of the signal line 23) is "H'" is extracted and arranged, the result is shown in FIG. This is shown in (A) to ( in the input cover pattern in Figure 2).
After expanding to F), we process 20 dots of data considering the image before reduction, and thereby 8 dots (215x).
This means that the output is obtained.

In addition, in order to know what kind of thinning (reduction) is being performed in this processing example, a sequential number (1 to 6) is assigned to the input, and the output of the register 22 also takes a sequential number (0 to 5). Assuming that the run lengths (values of signal line 3) are all "0", let's examine which colors are valid and output using FIG. 4.

According to this, among the input data, the color of "1" and "
It can be seen that the valid flag is set only for the color "3" (the value of the signal line 21 is "H"). Further, the state of S6 is the same as the state of Sl except for the color, and from S6 onwards, S1 to S5 are repeated. Therefore, an 8-bit image is obtained by thinning out the processed 20-bit image as shown in FIG.

When enlarging, the same operation as when reducing is performed. However, in the case of expansion, the reciprocal is a number less than 1, so the result of the subtracter 16 will never be less than "1". Since the run length is "1" or more (a natural number), the adder 7
The output of is always positive.

Therefore, all outputs are valid (value of signal line 21 is always 'H')
)become.

Regarding the processing speed, in the case of reduction, the conventional technology has a speed of 20
However, in the above embodiment, when the input cover turn shown in FIG. 2 is multiplied by 215, the process is completed in 10 cycles.

In addition, the make-up code of MH code (Makeup
Code) is processed inside the decoder 2, outputs the same color as before from the signal line 4, and outputs the run length to the signal line 3.

By using the image processing means according to the embodiment of the present invention as described above, code decoding processing and expansion/reduction processing in the X direction can be performed simultaneously, thereby eliminating the need for special architectures such as pipeline processing. Both can be processed at high speed. In addition, since image data before reduction is not generated when performing reduction, if the input speed of encoded data is sufficiently fast, the processing time will be shorter as the reduction ratio becomes larger, and the processing time will be shorter than the pipeline processing means shown in Fig. 6. can also be processed quickly.

[Effects of the Invention] As detailed above, the image data processing device of the present invention includes means for obtaining color information and run length information from compressed data, and subtracting the reciprocal of a designated magnification from the run length information. and means for outputting the same color information as the corresponding color information for the number of subtractions until the result of the subtraction becomes zero or negative, and the image is enlarged or reduced according to a specified magnification directly from the compressed data. By adopting a configuration for obtaining data, it is a relatively simple and inexpensive configuration without special architecture such as pipeline processing, and -
It is possible to simultaneously perform decompression processing of image data compressed in the dimension direction and processing of enlarging/reducing the image according to a specified magnification. In addition, since there is no need to generate image data before reduction during reduction, if the manual speed of compressed data is sufficiently fast, the larger the reduction ratio, the shorter the processing time.
Faster processing than conventional pipeline processing is possible.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a diagram showing an example of the input cover pattern in the above embodiment, and FIGS. 3 and 4 are signals of each part in the above embodiment. FIG. 5 is a diagram showing the relationship between the input dot pattern and the output dot pattern in the above embodiment. FIG. 6 is a diagram showing the image decoding and enlargement/reduction processing means using a conventional pipeline. FIG. 1, 3.4.6.8.9.11.12.15.17.1
8゜19, 21.23... Signal line, 2... Decoding section, 5... AND gate, 7... Adder, 10.
13.22...Register, 14...And gate,
16...Subtractor, 20...Logic circuit. Applicant's agent Patent attorney Takehiko Suzue

Claims (1)

[Claims] In an apparatus having means for decompressing image data compressed in one dimension and means for enlarging/reducing the image according to a designated magnification, means for obtaining color information and run length information from the compressed data, and means for obtaining color information and run length information from the compressed data; and a means for outputting the same color information as the corresponding color information for the number of subtractions until the result of the subtraction becomes zero or negative from the compressed data. An image data processing device that directly obtains image data that is enlarged or reduced according to a specified magnification.