JPH01174125A - Duplicate structural electronic device - Google Patents

Abstract

PURPOSE:To prevent occurrence of deformed waveform at switching by detecting the reduction of a power voltage of an active system electronic section just before it is dropped up to an operation disable voltage and activating a standby system electronic section. CONSTITUTION:The device is provided with two clock generating sections 10a, 10b, either of them is used as an active system and the other is used as the standby system. The generating section 10a is oscillated synchronously with a signal S5 when an external signal S5 is supplied and generates a clock signal CK through self-oscillation when no signal S5 is supplied. The generating section 10b is constituted similarly. Through such constitution above, the circuit 17 detects the reduction in the voltage V1 before the generating section 10a is malfunctioned due to the voltage drop of the power voltage V1 and a signal S8 is outputted from the circuit 16. Thus, before the generating section 10a malfunctions, the standby system generating section 10b is activated.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a dual structure electronic device used in data communication systems and the like.

(Prior Art) In a data communication system, a clock generation device (duplex structure electronic device) is provided in each device connected to a network, and a clock generation device (duplex structure electronic device) is provided in each device connected to the network to generate a clock signal based on an external signal supplied from the network. is generated to synchronize each of these devices.

FIG. 2 is a block diagram showing an example of a clock generation device provided in such equipment.

The device shown in this figure has two clock generators 1a and 1b.
Of these clock generators 1a, 11], one is used as the active system and the other is used as the backup system.

One clock generation section 1a includes an external signal S supplied from a network, a clock extraction circuit 2 that extracts a clock component from the inside, an oscillation circuit 3 that extracts a frequency corresponding to the output of this clock extraction circuit 2, and an oscillation circuit 3 that extracts a clock component from the external signal S supplied from the network. A frequency dividing circuit 4 that divides the output of the excavation circuit 3, a drive circuit 5 that generates a clock signal C corresponding to the output of this frequency dividing circuit 4, and a monitoring circuit 6 that monitors the operating state of this drive circuit 5. and a selection circuit 7 that operates or stops the drive circuit 5 based on the signal S2 supplied from another clock generator 1b and the output of the monitoring circuit 6.

Further, the other clock generating section 1b is configured similarly to the clock generating section 1a.

Then, normally, the clock generating section 1a designated as the active system operates to generate a clock signal C synchronized with the external signal s1, and supplies this to each required section.

When a failure occurs in the active clock generating section 1a for some reason, this clock generating section 1a
The signal S3 is output from a and the standby clock generator 1
b starts a clock generation operation and outputs a clock signal CK in place of the active system clock generation section 1a.

However, in this method, when the output of the drive circuit 5 provided in the clock generation section 1a becomes abnormal, the monitoring circuit 6 detects this and outputs the signal S3 from the selection circuit 7. If the characteristics of the internal elements (active elements) that make up the
As shown in the figure, before the selection circuit 7 outputs the signal S3, the operation of the clock generator 1a becomes unstable and the fourth
As shown in FIGS. (a) and (b), there is a drawback that the output of the clock generating section 1a causes waveform distortion.

(Object of the Invention) The present invention has been made in view of the above circumstances, and is capable of preventing waveform cracking from occurring when switching from a working system clock generating section to a backup system clock generating section. The object of the present invention is to provide a dual structure electronic device.

(Summary of the Invention) In order to solve the above-mentioned problems, in the dual structure electronic device according to the present invention, the power supply of the active system electronic section is improved. +! Immediately before the voltage drops to an inoperable voltage, this is detected and the standby electronic section is brought into operation. As a result, the operation of the standby electronic section is started before the output of the active electronic section becomes abnormal.

(Embodiment) FIG. 1 is a block diagram showing an embodiment of a dual structure electronic device according to the present invention.

The device shown in this figure has two clock generators lOa, 1
0b, each of these clock generators 10a, 1
One of 0b is used as a working system, and the other is used as a backup system.

The clock generation section 10a includes a clock extraction circuit ll, an oscillation circuit 12, a frequency dividing circuit 13, and a drive circuit! 4 and
Monitoring circuit 15, selection circuit 16, and power-off detection circuit 17
When the external signal S5 is supplied, it oscillates in synchronization with this external signal S5, and when this external signal S5 is not supplied, it automatically oscillates to generate the clock signal CK. is supplied to each part of the equipment.

The clock extraction circuit 11 is configured to extract a clock component from an external signal S supplied from the network, and supplies this clock component to the oscillation circuit 12.

The oscillation circuit 12 generates a frequency signal by oscillating at a frequency based on the clock component, and supplies this to the frequency dividing circuit 13 .

The frequency divider '#i13 divides the frequency signal to generate a frequency signal corresponding to the frequency of this frequency signal, and supplies this to the drive circuit 14.

While the selection signal S7 is being supplied to the control terminal, the drive circuit 14 generates a clock signal C having a predetermined voltage and current based on the frequency signal supplied from the frequency dividing circuit 13. Supplied to each part of the device.

The monitoring circuit 15 is a circuit that monitors whether the drive circuit 14 is operating normally, and generates a drive failure signal S6 when the input or output of the drive circuit "#J14" becomes abnormal. Then, it is supplied to the first input terminal 16a of the selection circuit 16.

The selection circuit 16 is configured to operate in either a master mode or a slave mode, and when operating in the master mode, the drive failure signal S6 is not supplied to the first input terminal 16a, and When the power-off detection signal S is not supplied to the second input terminal 16b, a selection signal S7 is generated and the selection signal S7 is sent to the drive circuit 1.
Supply to 4. Then, the drive failure signal S6 is supplied to the first input terminal 16a, or the drive failure signal S6 is supplied to the second input terminal 16b.
When the power-off detection signal S is supplied to the clock generating section 10b, it generates a signal S8 and supplies this to the selection circuit in the other clock generating section 10b.

Further, when operating in slave mode, a signal S, is sent to the input/output terminal 16c. is supplied, the first and second
It checks whether a drive failure signal S6 and a power-off detection signal S are supplied to the input terminals 16a and 16b, and when these are not supplied, a selection signal S7 is generated and supplied to the drive circuit 14. .

Further, when the power supply voltage V1 supplied to the clock generating section lOa becomes smaller than the threshold value SH2, the power-off detection circuit 17 generates a power-off detection signal S, and the selection circuit 1
6 to the second input terminal 16b.

In this case, the threshold value SH is set higher than the power supply voltage value at which the clock generator 10a malfunctions.

Further, the clock generating section 10b is also similar to the clock generating section 10.
It is configured similarly to a.

As described above, in this embodiment, before the clock generating section 10a malfunctions due to a drop in the power supply voltage V1, the power-off detection circuit 17 detects a drop in the power supply voltage and activates the selection circuit 1.
Since the signal S6 is outputted from the clock generator 6, the standby clock generator 10b can be brought into operation before the clock generator 10a malfunctions.

This makes it possible to prevent problems such as output cracking of the clock generator 10a from occurring.

(Effects of the Invention) As explained above, according to the present invention, when switching from the working system clock generating section to the backup system clock generating section,
It is possible to prevent waveform cracks from occurring.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a dual structure electronic device according to the present invention, FIG. 2 is a block diagram showing an example of a conventional dual structure electronic device, and FIG. 3 is a block diagram showing an example of a conventional dual structure electronic device. Show 2
Voltage waveform diagrams for explaining the switching operation between the active system and the standby system of the multilayer electronic device, FIGS. 4(a) and 4(b) are output waveform diagrams of each clock generator shown in FIG. 2, respectively. . 10a... Current system electronic section (clock generation section), 10b
. . . Standby electronic section (clock generation section), 16 . . . selection circuit, 17 . . . power failure detection circuit. Patent applicant: Toyo Tsushinki Co., Ltd.

Claims (1)

[Claims] In a dual structure electronic device having a working electronic section and a standby electronic section and operating either of them, a power-off detection signal is sent immediately before the power supply voltage of the working electronic section drops to an inoperable voltage. A dual structure electronic device comprising: a power-off detection circuit that generates a power-off detection circuit; and a selection circuit that puts the standby electronic section into an operating state when a power-off detection signal is output from the power-off detection circuit. Device.