JPH01174084A - Transfer system for picture data - Google Patents

Abstract

PURPOSE:To decrease the transfer speed per one picture element, to improve the operating efficiency of the circuit and to make the circuit hardly susceptible to the effect of noise by storing a picture element data subject to A/D conversion once into a memory, reading a picture element data from the memory in a period larger than the timing of a video signal and transferring the data. CONSTITUTION:Only a processed range having a picture element data among video signals B1 of the NTSC system outputted from a camera 1 is A/D- converted and a digital signal B2 synchronously with the timing of the video signal is written in a memory 7 for each line and read by a controller 9 and outputted to an image bus 10, but the readout period of the data by one line is far larger than the product of the processing picture element number of one line and the transfer time per one picture element. Then after the required processing is implemented, the picture element data B4 of the image bus 10 is written in a memory 11 and read by an output controller 12 and outputted to a D/A converter 4 and the readout period at that time is the same as the period at A/D conversion.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an image data transfer method for converting a video signal into a digital signal and transferring the converted digital signal.

[Conventional technology]

FIG. 4 is a block diagram showing this type of image data transfer system. In the figure, l is a camera, and 2 is this camera 1.
A/D (analog/analog signal) that converts a predetermined processing range valve into a digital signal
3 is a processing circuit that processes the digitized pixel data, and 4 is a D/A (digital/analog) converter that converts the processed data into an analog signal, and transfers these image data. is controlled by a video signal controller 5.

Reference numeral 6 denotes a monitor that displays images using video signals synthesized through the D/A converter 4.

FIG. 5 is a diagram showing the output timing of the output signals of each part in FIG. 4. A video signal (A1) such as the NTSC system output from the camera 1 is input to the A/D converter 2, where the signal of a predetermined range valve with a pixel signal is converted into a digital signal (A2), and the signal is processed. Transferred to circuit 3. The output signal A2' of the signal processing circuit 3 is converted into an analog signal (A, ) by the D/A converter 4 at the same timing as the above-mentioned A/D conversion, and is output to the monitor 6.

[Problem that the invention seeks to solve]

In conventional image data transfer, pixel data is transferred at the same timing as the video signal as described above, so the transfer speed per pixel is fast, the operating efficiency of the circuit decreases, and it is not affected by noise. The problem was that it was easy.

The present invention has been made in view of these problems, and provides an image data transfer method that improves the operating efficiency of the circuit and is less susceptible to the effects of noise.

[Means for solving problems]

The image data transfer method of the present invention includes a memory that stores pixel data converted from a video signal into a digital signal, and reads the pixel data from this memory at a cycle larger than the conversion cycle and outputs it to an image bus. It is equipped with a controller, a memory for storing pixel data output to the image bus, and a controller for reading out pixel data from this memory at the conversion cycle, thereby reducing the transfer speed of pixel data.

(Operation) In the image data transfer method of the present invention, A/D converted pixel data is temporarily stored in a memory, and the pixel data is read out from this memory at a cycle larger than the timing of the video signal and transferred. Therefore, the transfer speed per pixel decreases.

〔Example〕

FIG. 1 is a block diagram showing one embodiment of the present invention.

In the figure, 1 is a camera, 2 is an A/D converter that converts a certain processing range from the video signal into a digital signal, and 7
is a memory that stores pixel data converted into digital signals, and data transfer between these is performed by the input controller 8.
controlled by 9 is a bus controller that reads out pixel data from the memory 7 at a cycle larger than the A/D conversion cycle and outputs it to the image bus 10; 11 is a memory that stores the pixel data output to the image bus 10;
Reference numeral 12 denotes an output controller that reads out pixel data from the memory 11 by returning it to the above-mentioned A/D conversion cycle.The read pixel data is input to the D/A converter 4, where a video signal is synthesized and displayed on the monitor. 6 is input.

Next, the operation will be explained using the timing chart shown in FIG. This FIG. 2 shows the output timing of signals from each part of FIG. 1.

NTSC video signal output from camera 1 (B
1) is obtained by scanning the screen line by line from left to right as shown in FIG. 3, and there is a processing range of pixel data between them. Furthermore, there is a horizontal blanking period in which there is no pixel data between each line, and there is a vertical blanking period in which no data is present between the screens.

Then, the video signal (B1) is A/D converted for the above processing range, and a digital signal (B2) synchronized with the timing of the video signal is stored line by line in the memory 7.
will be written to. The pixel data written in this memory 7 is read out by the controller 9 and is transferred to the image bus 1.
The readout period for one line of data is larger than the number of pixels processed in one line multiplied by the transfer time per pixel. Thereafter, after necessary processing is performed, the pixel data (B4) on the image bus 10 is written into the memory 11. The data in this memory 11 is read by the output controller 12 and output to the D/A converter 4 (B5), but the read cycle at that time is the same as the cycle for A/D conversion mentioned above. There is. Then, the D/A converter 4 synthesizes the output signal (B5) of the memory 11 and a video signal (B5) in phase, and outputs the synthesized signal to the monitor 6.

Here, for example, the above A/D conversion is performed at 12MH2,
Assuming that 512 pixels of these are the processing range, approximately 30
% is the period with no data.

Therefore, for example, the data processed as above is 8.31
When transferred to the image bus 10 with a clock of 3MH,
The period with no data is less than 2%. Therefore, 83.3
``What must be processed with 7 pixels is 120 degrees''/
This improves the pixel size, simplifies circuit design, and improves the operating efficiency of the circuit. At this time, since the periods of the horizontal period and water drop period of the video signal do not change, conversion between the video signal and the signal of the image bus 10 can be easily realized in real time. Also, since the data transfer speed is reduced, it is less susceptible to noise.

〔Effect of the invention〕

As explained above, according to the present invention, a rewritable memory for pixel data is provided to reduce the transfer speed per pixel, which improves the operating efficiency of the circuit and makes it less susceptible to noise. There is an effect.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a timing chart showing the output timing of signals of each part in Fig. 1, Fig. 3 is an explanatory diagram showing the screen scanning method, Fig. 4 is a block diagram showing a conventional image data transfer method,
FIG. 5 is a timing chart showing the output timing of signals from each part in FIG. 4. 2.------A/D converter 4------D/A converter 7---Memory 8---Manual controller 9---Bus controller 10- ---Image bus 11--Memory 12--Output controller Applicant: Stanley Electric Co., Ltd. Figure 2. Engraving of the drawings Figure 3. 11) Correct? j;' (Method) Showa 63
June 20, 2017 Director General of the Patent Office Kunio Ogawa 1, Indication of Case Patent Application No. 329909 of 1988
No. 2, Title of the invention Image data transfer method 3, Person making the amendment'1 Relationship with the matter Patent applicant address 2-9-13 Nakameguro, Meguro-ku, Tokyo Name
(230) Representative of Stanley Electric Co., Ltd.
Hand, A Toru 4, Agent address: 3-3-14-5 Shinbashi, Minato-ku, Tokyo, Date of amendment order: March 29, 1988 (all date of delivery) 6, Subject of amendment

Claims (1)

[Claims] A memory that stores pixel data converted from a video signal into a digital signal, a controller that reads pixel data from this memory at a cycle larger than the conversion cycle and outputs it to an image bus, An image data transfer method comprising a memory for storing pixel data and a controller for reading out the pixel data from the memory at the conversion cycle, and reducing the transfer speed of the pixel data.