JPH01173985A - Time base correcting circuit for video signal - Google Patents

Abstract

PURPOSE:To correct the time base of a video signal without any troublesome switching control by using a high-speed line memory which can write and read data asynchronously and simultaneously as a memory to store a digital video signal. CONSTITUTION:When a writing starting signal A is risen to an 'H' level at a time t1 by the control of a controller 3, a reproduced video signal is converted by an A/D converter 2 in the timing of a writing clock and written to a high- speed line memory 9. Next, when a reading starting signal B is risen to the 'H' level at a time t2 with the delay of certain time, the digital video signal written in the high-speed line memory 9 are read by a stable reading clock Rc generated by a clock generating circuit 11 for a reading. Thus, an analog video signal Y, from which time base fluctuation is eliminated, is passed through a low-pass filter 14 and outputted from an output buffer 15.

Description

[Detailed description of the invention] (Industrial application field) The present invention relates to a time axis correction circuit for video signals.

(Conventional technology) Improves video quality by using video cheap recorders and electronic still cameras.
When recording ILF raw images, unevenness in the rotation of the magnetic tape or magnetic disk causes so-called time axis fluctuations in which the time axis expands or contracts with respect to a constant nof quasi-time, and this is called jitter, where the Ilf raw image partially fluctuates. A phenomenon occurs.

Conventionally, time axis correction circuits for correcting this time axis fluctuation have been known, and the basic idea of time axis correction is to adjust the video signal based on a signal (advanced signal) that is a certain amount of time ahead of the standard signal. 11, the time axis fluctuation leads or lags behind the advance signal, so for the advanced part, increase the delay amount, and for the delayed part, reduce the delay to the original standard 0 Gin. This allows you to obtain images with consistent timing.

There are two types of time axis correction circuits: one that corrects the time axis using the analog video signal as it is, and one that corrects the time axis after converting the analog video signal '-) into a digital video signal. An example of a conventional digital time base correction circuit using a shift register as a line memory is shown.

When the luminance signal Y of the reproduced video signal that has undergone time axis variation is inputted via the input buffer, it is converted into a digital video signal by the A/D converter 2. The A/D converter 2 is composed of a PLL, in which the horizontal synchronization signal is separated by the synchronization separation circuit 4 in a state where the write start signal A is output from the controller 3, and synchronized with the horizontal synchronization signal HD having a time axis variation. Write clock generation circuit 5
A write clock Wc of 614.3MH is output. When the write start signal A from the controller 3 reaches the ``H'' level, the write clock Wc passes through the ant gate G1 and is applied to the A/D converter 2, where the video signal is A/D converted.The A/D converted video signal is sent to the one-stage shift register 10 by the multiplexer 6, which is switched in response to the selection signal from the controller 3.At this time, the old clock Wc selected by the multiplexer 7 is input to the clock terminal C of the shift register IO, and the digital The video signal is input. When the shift register 10 is filled, the digital video signal output from the A/D converter 2 is changed to 0 by the multiplexer 6.
It is switched and sent to the stage shift register 20, and the clock MA f C is inputted with the I; input clock Wc selected by the multiplexer 8, and a digital video signal is written therein. At this time, only the write clock Wc is no longer input to the clock terminal C of the shift register 10.

Below, the same operation is performed in the 0-stage shift register 30.40.1O
120, . . . are repeated in this order.

On the other hand, the write operation starting from the shift register 10 writes 1! to the shift register 20! When the I input is completed and the read start signal B from the controller 3 becomes -H level at the same time as the start of input to the shift register 30, the time axis fluctuation of 14.3 MH from the read clock generation circuit 11 is detected. The read clock Re, which is not available, is input to the D/A converter 13 and the multiplexer 7 via the ant gate G2. As a result, a digital video signal or a clock signal synchronized with a reference signal with no time axis fluctuation is read out from the shift register 10, and the multiplexer 12 sends the video signal to the D/A converter 13 in response to a command from the controller 3 to receive an analog video signal. Convert to The analog video signal is passed through a low pass filter (LPF) 14 and output via an output buffer 15. After that, according to the command from the controller 3, the shift register 20.30.40.10.20,
... is read out at 1111.

According to this method, if the write clock frequency is fwc, a time axis correction of ±l/f wcX n (seconds) can be achieved.

In the time axis correction circuit with the above circuit configuration, it is necessary to use a shift register as a delay element, or there is a difference between the 3-inclusive timing and the readout timing, and in order to widen the correction width, a shift register is used as a delay element. It requires multiple line memories configured as registers, and also requires control to switch line memories.

In addition, when a RAM is used as the 8-bit element, it is necessary to control the readout and readout timings so that they are performed apparently independently.

However, unlike shift registers, FIFOs (First-in-Front memory) have recently been developed, which perform reading and reading independently and asynchronously at different timings and at different speeds.
A high-speed line memory with an irst-out structure has been developed and put into practical use.

(Objects and Structure of the Invention) The present invention has been made to solve the above problems by using a high-speed line memory with a FIFO structure, and has a simple circuit structure and eliminates the troublesome control of reading and writing into the memory. In order to achieve this goal, we used a high-speed line memory in which 11 asynchronous data writes and reads can be performed simultaneously as the memory for storing digital video signals. It is something.

(Example) The present invention will be explained below based on the drawings.

FIG. 1 shows a -x embodiment of a time axis correction circuit according to the present invention, in which the same reference numerals as in FIG. 3 indicate rotating components.

1 is a large buffer, 2 is an A/D converter, 3 is a controller that controls the timing of writing start and reading start, 4 is a synchronous separation circuit, 5 is a 3-input clock generation circuit composed of PLL, 9 is a FIFO structure 11 is a read clock generation circuit, 13 is a D/A converter, 14 is a low-pass filter, and 15 is an output huffer.

Next, the circuit operation will be explained.

The luminance signal Y of the reproduced video signal having time axis fluctuation is applied to the synchronization separation circuit 4 via the input huffer l, and the water f synchronization signal is separated.The horizontal synchronization signal separated by 0 is added to the write clock generation circuit 5. Here, a 14.3 MHz write clock Wc synchronized with the horizontal synchronizing signal is generated. This write clock follows the time axis fluctuation of the input reproduced video signal and is synchronized with the water motion synchronization signal.

Under the control of the controller 3, as shown in FIG. 2(a), when the preload start signal A rises to the "H" level at time t1, the reproduced video signal is output to the A/D at the timing of the old clock.
After being A/D converted by the converter 2, it is written into the high-speed line memory 9 as a digital video signal.

Next, under the control of the controller 3, as shown in FIG.
When it rises to H“ level, the read clock generation circuit 11
The digital video signal occupied by the high-speed line memory 9 is read out by the 14.3 MHz stable read clock Rc generated by the 14.3 MHz stable read clock Rc, and after being D/A converted by the D/A converter 13, the low-pass filter 1
Analog video signal Y from which time axis fluctuations have been removed through 4
' is output from the output huffer 15. The memory capacity of the high-speed line memory 9 used here: If yo is N words, then (t2-t,) is 1 N 12-1□ = x - (seconds) 14, 3
By selecting xlO' 2 , the time axis correction range becomes ±(t2-tl). Therefore, in order to enlarge the correction range, it is sufficient to increase the memory capacity N of the high-speed line memory.

In the above embodiment, digital lpl! to high-speed line memory!
14.3 as image signal interpolation and readout clock frequency
Although we chose MHz, this frequency can be chosen arbitrarily. Furthermore, it goes without saying that the video signal to be subjected to time axis correction may be a color difference signal in addition to the luminance signal.

(Effects of the Invention) As explained above, in the present invention, a high-speed line memory in which writing and reading of data can be performed asynchronously and simultaneously is used as a memory for storing digital video signals, so that the memory is composed of a plurality of line memories. It is possible to easily correct the time axis of the video signal with a simple circuit configuration without using a block, and without complicated switching control.

[Brief explanation of the drawing]

11''A is a block diagram of an embodiment of the video signal time base correction circuit according to the present invention, and FIG. 2 is a digital video signal i)
FIG. 3 is a block diagram of an example of a conventional video signal time axis correction circuit. 2... A/D converter, 3... Controller, 4
... Period separation circuit, 5. Old clock generation circuit, 9.-FIFO structure high-speed line memory, 11.
Read clock generation circuit, 13...D/A converter

Claims (1)

[Claims] a synchronization separation circuit that separates a synchronization signal from a video signal; a first clock generation circuit that generates a write clock pulse that is synchronized with the synchronization signal; and a second clock that generates a read clock pulse that is synchronized with a reference signal. a generation circuit, an A/D converter that digitizes the video signal, a high-speed line memory with a FIFO structure that writes the digitized video signal in synchronization with a write clock pulse, and the readout circuit from the high-speed line memory. A digital video signal that converts digital video signals read out in synchronization with the
1. A time axis correction circuit for a video signal, comprising: an A converter; and a controller that controls read timing so that reading of the digital video signal from the high-speed line memory is delayed by a certain period of time from the start of writing.