JPH01173143A - Memory management unit - Google Patents

Abstract

PURPOSE:To extend the physical address space of a computer system and at the same time to reduce the load of a processor due to the extension of a physical address by giving an access to an extension memory address space based on the extension address signal received from a selector. CONSTITUTION:A memory management unit 2 always monitors the signal delivered to a data bus DB and the control signal CS for peripheral control of an MPU 1 via an instruction decoder 6. Then an auxiliary address signal extended synchronously with the timing where the signal corresponding to an address bus AB is delivered in case an instruction that extends the address signal is carried out when the instruction of the MPU 1 is decoded. Thus the available physical address space of the MPU 1 can be extended by the unit 2. Furthermore no load is applied to the unit 2 at all except the minimum necessary initialization.

Description

DETAILED DESCRIPTION OF THE INVENTION OBJECTS OF THE INVENTION Field of the Invention The present invention relates to a memory management unit (MMU) used to expand a fixed memory address space in a computer.

(Prior Art) In recent years, small and medium-sized computers and microcomputers have been applied to various fields, but the scale and amount of data of their application software has become enormous year by year. It is becoming difficult to fit all programs into fixed memory. To solve this problem, conventionally,
A method using an auxiliary storage device or a method using a memory management unit has been adopted.

First, the method of using an auxiliary storage device is to divide a huge program that cannot fit into the main storage device, move the program and data from the auxiliary storage device to the main storage device each time it is needed, and execute it. This is the way to do it.

However, this method has the disadvantage that the data transfer speed between the auxiliary storage device and the main storage device is slow, and it is reported that it is more expensive than the currently mainstream semiconductor memory.

In addition, the method using a memory management unit is
This is a method of expanding the physical address space, and representative methods include the page mapping method and the bank switching method.

The page mapping method is a method of converting a logical address into a physical address according to a conversion table. A logical address is divided into about 16 pages, and each page has one conversion table.

However, this method has a problem in that the effort required to initialize the conversion table and the effort required to convert the table places a large burden on the processor.

The bank switching method is such that when a value is written to a latch around a processor, the physical address assigned to the range from a specific logical address to a specific logical address is switched to another physical address from the moment the value is written. It is a method.

However, like the page mapping method, this method also has a problem in that the program for switching places a large burden on the processor. Furthermore, if the area to be switched is an area consumed as a stack by the stack pointer, the system may go out of control.

(Problems to be Solved by the Invention) In this way, the conventional method of expanding the physical address space using a memory management unit is based on the software of the processor, in both the page mapping method and the bank switching method. There is a problem in that it places a large burden on people. Especially in the bank switching method, there is a risk of inadvertently switching the bank containing the stack pointer, system work area, etc.
The problem is that it is a very large burden.

The present invention has been made in consideration of the above circumstances, and an object of the present invention is to provide a memory management unit that expands the physical address space of a computer system and reduces the burden on the processor due to the expansion of the physical address. do.

[Structure 1 of the Invention (Means for Solving the Problem) A memory management unit according to the present invention includes an instruction decoder that independently decodes a program being executed by a processor installed in a computer, and a predetermined extension address. It includes a register that holds signals and a selector that receives a signal from an instruction decoder and outputs an extended address signal held in the register, and allows access to the extended memory address space based on the extended address signal from the selector. Features.

(Function) The memory management unit according to the present invention monitors the program being executed by the processor, outputs an extended address signal when necessary, and expands the usable physical address space of the processor.

(Embodiment) FIG. 1 shows a block diagram of a microcomputer system using a memory management unit according to an embodiment of the present invention. The microcomputer system according to this embodiment has an MPU (microprocessor unit) 1 serving as its core, a program decoding type memory management unit 2, and a main storage device 3.4.5. 3, 4.5 to the MPUI, and the MPUI and main memory 3.4.
5 and external peripheral circuits by a data bus DB used for exchanging data with external peripheral circuits.

The program executed by the MPUI is connected to the address bus AB output from the MPU 1 and the expanded address bus EAB output from the memory management unit 1.
is read from the address in main memory 3.4.5 specified by and executed. Furthermore, the direction of the signal on the data bus DB, such as whether it is human input or output for the MPU 1, and the nature of the signal on the data bus DB, such as whether it is human output data or a program to be executed, are determined in the main memories 3, 4, . 5 and a control signal C8 for identification by external peripheral devices are output from the MPUI to the memory management unit 2 and the main storage device 3.4.5.

In a normal microcomputer system, there is no memory management unit 2 and an extended address bus EAB output from the management unit 2, and in that case, this is a completely common connection method for those skilled in the art.

Next, FIG. 2 shows a block diagram of a memory management unit according to an embodiment of the present invention. The memory management unit according to this embodiment is used in the microcomputer system shown in FIG. 1, and is composed of an instruction decoder 6, a register 7, and a selector 8.

The instruction decoder 6 is connected to the control signal C8 outputted by the MPUI shown in FIG. 1 for peripheral control and to the data bus DB, and while referring to the control signal C8, the instruction decoder 6 detects the current MPUI on the data bus DB. This is a decoder that decodes the program being executed.

Further, register 7 is also connected to control signal C8 and data bus DB, and is extended address bus E.
This is a latch that holds the value output to AB.

The selector 8 includes the instruction decoder 6 and the register 7.
This is a selector for the number of bits of the extended address bus EAB which receives the signal EAON from the instruction decoder 6 and outputs the value held in the register 7 to the extended address bus EAB. Each selector 8 is composed of, for example, an inverter 8a, an AND gate 8b18c1, and an OR gate 8d, as shown in FIG.

The signal EAON from the command decoder 6 is directly input to one input terminal of the AND gate 8b, and the ground voltage is input to the other input terminal. A signal EAON is inputted to one input terminal of the AND gate 8c via an inverter.
A signal from the register 7 is input to the other input terminal. At the input end of the Noah gate 8d are ant gates 8b, 8.
The output end of c is connected.

Next, the operation will be explained. However, in this embodiment, in order to simplify the explanation, only instructions that perform stack processing are decoded. This is because all computers with recent architectures are equipped with a stack pointer, so it is easy for engineers involved in this field to understand.

During normal operation, the MPUI stores instruction codes in main memory 3,
4.5, the data is transferred to the main storage device 3.4.
5 or when writing data to the main memory devices 3, 4.5, a "0" signal is output to the extended address bus EAB. Therefore, the same main storage device is selected as when the memory management unit 2 is not used at all.

When a register stack save, subroutine call, or return instruction from a subroutine is executed, the instruction decoder 6 provided in the memory management unit 2 and decoding independently of the MPU 1 decodes the instruction. Instructions are stored in main memory 3, 4.5
It is confirmed from the control signal C8 that the instruction is taken in and executed by the MPUI, and it is recognized from the contents of the data bus DB that it is a processing instruction related to the stack. After that, the value of the stack pointer changes to address bus A.
The EAON signal output from the instruction decoder 6 to the selector 8 is switched from the normal high (Illgh) level to the low (Low) level at the timing of output to the selector 8. As a result, the previously set contents of the register 7 are outputted to the expanded address bus EAB through the selector 8, and a main memory having a different physical address is selected only when the stack is used. That is, the expanded memory address space can be accessed by the EAON signal output from the instruction decoder 6.

In the above case, the instruction to be decoded is a stack processing instruction, but by decoding the subroutine call instruction, an extended address signal is issued when the instruction is fetched from fetching the next instruction to decoding the return instruction. It is possible to choose another physical address.

In this way, the memory management unit 2
The instruction decoder 6 constantly monitors the signal output to the data bus DB and the control signal C8 for peripheral control of the MPUI, and decodes the instruction of the MPU 1, thereby executing an instruction to extend the address signal. In this case, the extended auxiliary address signal is output in synchronization with the timing at which the corresponding signal is output to the address bus AB.

Therefore, with the memory management unit 2 according to this embodiment, it is possible to expand the usable physical address space of MPUI. In order to monitor the program being executed and output extended address signals when necessary, the memory management unit 2 does not have any burden other than the minimum necessary initial settings.Moreover,
In the memory management unit 2 according to this embodiment, a considerable portion of the program memory area used for setting the conventional memory management unit can be deleted.

In addition, in this embodiment, the stack area and the data area can be allocated to the same logical address space, so the stack area can be programmed without special consideration in software (the data area can be expanded accordingly). By decoding the most suitable instructions for the MPU 1 in use, the physical address space can be further expanded and memory can be utilized effectively.

In the above embodiment, the instruction decoded by the memory management unit 2 is a stack processing instruction, and the timing at which the extended auxiliary address signal is output is when the value of the stack pointer is output to the address bus AB. However, it has a wide range of applications, such as decoding a branch instruction to a specific address and outputting an extended address at the timing when the next machine language instruction is fetched from the main memory.

[Effects of the Invention] As described above, according to the present invention, it is possible to expand the physical address space of a computer system and to reduce the burden on the processor due to the expansion of the physical address.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a microcomputer system using a memory management unit according to an embodiment of the present invention, and FIG. 2 is a block diagram showing the same memory management unit. DESCRIPTION OF SYMBOLS 1...MPU, 2...Program decoding type memory management unit, 3,4.5...Main storage device, 6...Instruction decoder, 7...Register, 8...
selector. Applicant's agent Mr. Sato

Claims (1)

[Scope of Claims] In a memory management unit using a fixed memory address space and an expanded extended memory address space in a computer, an instruction for decoding a program being executed by a processor installed in the computer independently of the processor. a decoder, a register that holds a predetermined extended address signal, and a selector that receives a signal from the instruction decoder and outputs the extended address signal held in the register, and outputs the extended address signal from the selector. A memory management unit that accesses the extended memory address space based on a signal.