JPH01170111A - Digital signal processor - Google Patents

Abstract

PURPOSE:To execute a pipeline processing without lowering the efficiencies of an ALU and a multiplier by dividing the operation of a digital filter corresponding to a delaying level and executing the pipeline processing in a sampling period unit. CONSTITUTION:A memory 1 to store plural multiplication results, a memory 2 to store plural addition results, a bus for the pipeline processing of an arithmetic operation of sum-of-products, and a bus for the pipeline processing of an arithmetic operation of product-of-sums are provided. The arithmetic operation of the digital filter is divided corresponding to the delaying level, and the pipeline processing is executed in the sampling period unit. Since the pipeline processing in the sampling period unit is executed with the pipeline processing in a man-machine cycle unit, the total processing time of a filter arithmetic operation is made minimum.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a digital filter and is patented.

A digital filter suitable for constructing a digital filter that shortens the time from data input to output.
Regarding signal processors.

[Conventional technology]

Conventional DSP (Digital Signal Processor) is used in a wide range of communication fields, and as shown in Figure 4, it is used for open-loop digital signal processing such as digital filters, fast Fourier transform, speech analysis, and speech synthesis. In order to shorten the total processing time with the minimum amount of hardware, the multiplier 4 and ALU 3 are operated in a pipeline as shown in Fig. 5, resulting in a product-sum type ALU. Therefore, when calculating the digital filter shown in FIG. 6, operation 1, operation 2, and operation 3 execute addition and multiplication in parallel, and the multiplication 203 of operation 1, the addition 102 of operation 2, and the multiplication 204 of operation 2 are performed in parallel. The product-sum operation shown in the addition 202 of operation 3 is pipelined and the total processing time is shortened.

In addition, related to this type of DSP is, for example, 81-9 of the 1986 Electronics and Communication Division National Conference Lecture Proceedings.
can be mentioned.

[Problem that the invention seeks to solve]

Since the above conventional technology is used in an open loop, it takes into account the reduction of the total processing time by increasing the sampling frequency. It wasn't taken into consideration.

This delay time does not cause any major problems in the case of an open loop, but it does in the case of a digital filter used in a servo system compensation circuit as shown in FIG.

Since it is used in a closed loop, there is a problem that the delay time of the digital filter reduces the phase margin of the entire servo system.
It is necessary to reduce the delay time of the digital filter.

An object of the present invention is to provide an SP configuration and control method that facilitates the configuration of a digital filter with a small delay time.

[Means for solving problems]

The above purpose is to provide a memory that can store multiple multiplication results, a memory that can store multiple addition results, a bus for pipeline processing of product-sum operations, and a bus for pipeline processing of sum-product operations, and to provide a memory that can store multiple results of one multiplication, a bus for pipeline processing of sum-of-product operations, and a bus for pipeline processing of sum-of-product operations. This is achieved by dividing the calculation of the digital filter and controlling the pipeline processing in units of sampling periods.

[Effect]

A memory capable of storing a plurality of addition results and a bus for pipeline processing of sum-product operations enable pipeline processing of sum-product operations. This pipeline process.

Since the memory can store a plurality of addition results, it is possible to perform multiplication on addition results from several cycles ago.

In addition, a memory capable of storing a plurality of results of one multiplication and a bus for pipeline processing of product-sum calculations enable pipeline processing of product-sum operations. This pipeline processing is possible because the memory can store multiple multiplication results.

Addition to multiplication results from multiple cycles ago is possible.

From this K, the pipeline processing of the digital filter calculation divided according to the delay level in units of sampling periods can be efficiently performed by pipeline processing in units of machine cycles. In particular, pipeline processing in sampling period units calculates the output value first and minimizes the delay time from data input to output. Furthermore, since pipeline processing in units of sampling periods is performed by pipeline processing in units of machine cycles, the total processing time for filter calculations can also be minimized.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. 1st
The figure is a block diagram of one DSP of the present invention, and two L
SR (Local Storage Register)
rs ) l m2 , an ALU 3 and a multiplier 4.

LSRI is an LSR for multipliers, and is composed of a selector and a 4-baud RAM (RAM with one input port and three output ports). I, 4 baud of SR1) RAM
As the write data, either the output data of the multiplier 4 or the data of the data bus 5 is selected by the selector, and is written to the position specified by the write address WAA6. The output of port A of the LSRI is connected to the input of the multiplier 40, and outputs the data at the position specified by the read address RAA8.

The output of port B of LSRI is connected to the input of ALUI, and outputs data at the position specified by read address RAB9. The output of port C of LSRI is connected to the input of ALUI and data bus 5, and outputs data at the position specified by read address RACIO.

LSR2 is an LSR for ALU, and is composed of a selector and a 4-baud RAM. As the write data of the 4-baud RAM of LSR2, either the output data of ALU3 or the data of data bus 5 is selected by the selector, and is written to the position specified by write address WAB7. The output of port D of LSR2 is.

Connected to the input of ALU3, read address RAD11
Outputs the data at the specified position. Poe of LSR2)
The output of E is connected to the multiplier 40 input.

Data at the position specified by read address RAE12 is output. Port F of LSR2 is connected to the input of ALU3 and data bus 5, and outputs data at the position specified by read address RAF13.

ALU4 performs an operation between one of the output data of port B of LSRI or the output data of port D of LSR2 and the output of port C of LSRI or one of the output data of port F of LSR2, and inputs the result to LSR2. .

Multiplier 4 outputs the output data of LSRI port A and LSR2.
Multiply the output data of port E.

Input the result to LSRI.

FIG. 2 is a diagram in which the data flow diagram of the digital filter is divided by delay level. Processing is Processing A Zoo
, processing B 200 , and processing C 300K. Process A consists of additions 101 and 102.

Execute at the time when output data Y is output. Processing B200
is composed of additions 201 and 202 and multiplications 203 and 204, and since the data is processed through the delay element 400, it is possible to process the data one cycle before outputting the output data Y. Processing C300 is 1 multiplication 303°304
Since the data is processed through the delay elements 400 and 500, it is possible to process the data two cycles before outputting the output data Y.

FIG. 3 is a timing diagram of pipeline processing in sampling period units of the processing divided in FIG. 2. Output Y( for data X(n)K input at time nt$
In case of n), processing B and processing C are processed before the data X(n) is input, and the output can be performed with only the delay time of processing A, so that a digital filter with a small delay time can be constructed.

Next, the processing of the pipeline operation shown in FIG. 3 in the DSP having the configuration shown in FIG. 1 will be described. tJl,
The two-stage pi-cut filter shown in Fig. 8 is converted into the DS shown in Fig. 1.
The operation when realized by P is the processing steps shown in FIG. 9, as shown in this figure.

ALU performs pipeline processing in sampling period units.

It can be seen that processing is performed without reducing the efficiency of the multiplier, and the total number of processing steps and the number of steps from inputting data to outputting data can be reduced. Therefore, the DSP shown in FIG. 1 can constitute a digital filter with a small delay time.

〔Effect of the invention〕

According to the present invention, pipeline processing in units of sampling periods can be performed without reducing the efficiency of the ALU and the multiplier, so it is possible to configure a digital filter with a small delay time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a processing division diagram of the present invention, FIG. 3 is a timing chart of the present invention, FIG. 4 is a block diagram of open loop processing, and FIG. 5 is a block diagram of an embodiment of the present invention. A block diagram of a sum-of-products ALU. FIG. 6 is a data flow diagram of a pie-cut filter. Figure 7 is a block diagram of the servo system, Figure 8 is a data flow diagram of a two-stage pie-cut filter, Figure 9 is a step diagram of the operation of the filter in Figure 8 using the hardware in Figure 1, and Figure 10 is a diagram of the operation of the filter in Figure 8. 9 is a memory map of the processing shown in FIG. 1.2...LSRl 3...ALU. 4... Multiplier, 5... Data bus, 6.7
...Light address. 400, 500...delay elements. 100... Processing A, 200... Processing B. 300... Processing C, 1000... Digital signal processing. 13...Register, 14...Akyemureta, 10
01...Compensation circuit, 1002...Controlled object. 1003...Sensor section. Try to start the second Akira 5th ts Near > Buri frltM tv: Filter side straight-nl 4th j Monthly dark blue 7th flash θ2 /fu 8th wo

Claims (1)

[Claims] 1. A digital signal processor in which a multiplier and an ALU are operated in a pipeline, characterized in that a memory capable of storing a plurality of calculation results of the ALU and a bus for inputting the output of the memory to the multiplier are provided. signal processor.