JPH01169938A - Examination method for semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To eliminate duplicated examination of identical items at the time of final test, and reduce the inspection time, by utilizing non volatile memory contained in IC, and making the memory store test items examined in chip test. CONSTITUTION:An LSI inspection equipment (not shown in figure) applies a power supply voltage to the terminals 4, 5 of an IC chip 1, and input a logic pattern for chip test to an input port 6 and an address port 8. Output appeared on a data port 9 is compared to a normal value, and unacceptable IC chips are eliminated. Test items examined in chip test are recorded on the EEPROM 3 of a normal chip 1. After an IC device is completed by assembling the chip 1 together with other elements, final test is executed. At this time, the same test items as ones recorded on the memory 3 are not subjected to inspection. Duplicated inspection is evaded, and inspection time can be reduced. The memory 3 is cleared after inspection, and it is used for its intrinsic purpose.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention is directed to a semiconductor integrated circuit (I
Regarding C) test and method.

<Conventional technology> In recent years, digital tuning methods have been adopted in television broadcasting, video tape recorders, etc. in which channel selection is performed manually with a single key touch. Devices with built-in memory have appeared. The memory built into such ICs used to be static RAM backed up by an external battery, but with recent improvements in semiconductor integration technology, it is being replaced by non-volatile memories such as EPROM and EEPROM.

By the way, the manufactured IC with the above-mentioned built-in nonvolatile memory
Conventionally, a chip test is carried out in the chip state, and a final test is carried out in the state assembled together with other elements, to examine whether or not the chip exhibits a predetermined function depending on the applicable model. The above-mentioned chip test and final test are conducted using dedicated test equipment, and the test items include human curry test, function test,
There are usually many items common to both tests, such as the current consumption test.

<Problems to be solved by the invention> However, in the conventional test method described above, the same test items are performed in both the chip test and the final test, which results in a lot of waste due to duplicate tests, and it is difficult to reduce test costs. Therefore, it is not possible to reduce the manufacturing cost of the IC device. Therefore, one possible method for reducing test costs is to delete individual test items in the chip test, uniformly perform the greatest common divisor test items, and then perform the deleted test items in the subsequent final test. However, with this method, defects due to variations in parameters such as VTH value, β value, channel length, etc. that can only be detected and eliminated by the deleted individual test items are overlooked, and the entire assembly is defective in the final test. There is a risk that this will occur, and there is a drawback that the loss in the process due to wasteful assembly using defective IC chips will be enormous.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to effectively utilize the non-volatile memory built into an IC to store test items performed in a chip test, and to perform a final test of a device assembled using an IC that has passed the chip test. By omitting the above test items, it is possible to avoid redundant tests, shorten test time and test costs, and ultimately reduce the unit manufacturing cost of IC devices. The objective is to provide a test method for

Means for Solving the Problems In order to achieve the above object, the semiconductor integrated circuit testing method of the present invention is implemented on a semiconductor integrated circuit chip having a non-volatile memory after the semiconductor integrated circuit is manufactured. In addition to writing the contents of the chip test into the nonvolatile memory of the semiconductor integrated circuit, when performing a final test on a device assembled using the chip of the semiconductor integrated circuit, the data written in the nonvolatile memory is read out and The present invention is characterized in that the final test is performed by omitting the test items without performing them again.

<Example> Hereinafter, the present invention will be explained in detail with reference to illustrated embodiments.

FIG. 1 is a schematic diagram showing an example of a semiconductor integrated circuit (IC) chip on which the test method of the present invention is carried out, and l is an IC chip.
A chip 2 is provided in this IC chip 1 and is a logic area for executing various controls and calculations; 3 is a logic area connected to this logic area 2 by a path and provided in the above IC chip 1, and is a program for control and calculations; Electrically rewritable ROM (EEPROM) as a non-volatile memory that stores constants and
, 4.5 is a terminal for applying the power supply voltage Vcc and ground level GND to the logic area 2 and EEPROM 3, respectively; 6 and 7 are input and output ports for inputting and outputting signals to the logic area 2; 8 is the above E
An address boat for inputting an address signal to the EPROM 3; 9 a data boat for inputting and outputting a data signal to the EEPROM 3;
For example, tuning data is stored in the EEPROM 3 and used as a digital tuner for a television.

A test method for the IC chip 1 having the above configuration will be described below.

The manufactured IC chip 1 is first set in an LSI test device (not shown) for chip testing.

The LSI test apparatus applies a power supply voltage necessary for testing between terminals 4 and 5 of the IC chip 1, and inputs a logic pattern for testing to the manual port and address port 8. The IC chip 1 performs signal processing according to the input logic pattern, and outputs the processing results to the output port door and data port 9. Then, the LSI test equipment
The processing results output from the C chip 1 are compared with normal logical values previously stored in the pattern memory, and the quality of the IC chip 1 is automatically determined. In this way, test items such as the input current test, function test, and current consumption test conducted in the above chip test are converted into digital data by the LSI test equipment and stored in the EEPROM 3 of the IC chip 1 from which defective products have been removed. 8
．． Written via data boat 9.

Next, when the tC chip (2) that has passed the chip test is assembled with other elements to complete an IC device, this IC device is subjected to a final test by another test device (not shown). That is, the above-mentioned test device is capable of testing IC chips of IC devices.
Address port 8. EEFR via data port 9
The above test item data stored in OM3 is read out, the read data is identified, the corresponding test item is automatically deleted from a pre-given series of test items to be tested, and the remaining test items are A final test will be conducted only for The results of the final test are then compared with normal standard data given in advance to automatically determine whether the IC device as a whole is good or bad, and defective products are removed. Finally, IC chip 1 of the IC device that passed the final test.
The test item data stored in EEPROM3 of
It is erased electrically to make effective use of memory.

As described above, according to the IC testing method of the present invention, instead of deleting all individual test items and uniformly performing the greatest common divisor test items as in the conventional method, the IC testing method of the present invention By implementing optimal individual test items that correspond to parameters such as varying VTH values, defects related to the above parameters can be reliably discovered, and the performed test items can be written to the non-volatile memory built into the IC and continued. In the final test of an assembly using this IC, the chip test items are read out and the final test is performed without performing them again.
It is possible to significantly shorten test time, reduce test costs, and ultimately reduce manufacturing costs of IC devices.

In the above embodiment, EEPROM 3, which can be electrically erased and rewritten more than 1000 times, is used as a nonvolatile memory, so there are few restrictions on writing chip test items, and after the test, the written data is erased to store the memory. It has the advantage of being able to be used effectively.

Note that the nonvolatile memory of the present invention is based on the EEPRO of the embodiment.
It is not limited to M3, but it is also possible to use EPROM or simple ROM. Further, the contents of the chip test written to the nonvolatile memory may include not only the chip test items but also the test results. Furthermore, it goes without saying that the testing method of the present invention can be applied to semiconductor integrated circuits equipped with non-volatile memories other than digital tuners.

<Effects of the Invention> As is clear from the above description, the method for testing a semiconductor integrated circuit (IC) of the present invention is based on the content of a chip test conducted on a chip of an IC after manufacturing an IC equipped with a non-volatile memory. along with writing it to its non-volatile memory,
During the final test of a device assembled using the above IC chip, the written data is read out and the final test is performed by omitting the chip test items without performing them again, unlike the conventional example. By carrying out optimal individual test items in chip tests that correspond to parameters that vary from chip to chip, defects related to the above parameters can be reliably discovered, and the test time for the subsequent final test can be significantly shortened, reducing test costs. In addition, I
The manufacturing cost of the C device can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram showing an example of a semiconductor integrated circuit (IC) chip on which the test method of the present invention is implemented. l...IC chip, 2...logic area, 3...
・EEPROMo

Claims (1)

[Claims] (1) After manufacturing a semiconductor integrated circuit equipped with a nonvolatile memory, the contents of a chip test conducted on a chip of this semiconductor integrated circuit are written into the nonvolatile memory of the semiconductor integrated circuit, and the chip of the semiconductor integrated circuit is used. When performing a final test on the device assembled, the data written in the non-volatile memory is read out and
A method for testing a semiconductor integrated circuit, characterized in that a final test is performed by omitting chip test items without performing them again.