JPH01168053A - Manufacture of bi-cmos element - Google Patents

Abstract

PURPOSE:To obtain a NMOS transistor having high performance and to improve the characteristics of a bipolar transistor by simultaneously forming the source, drain regions of a PMOS transistor and the base region of the bipolar transistor, and forming the emitter region of the bipolar transistor by impurity diffusion from an N-type impurity-doped polysilicon layer or a polyside layer. CONSTITUTION:N-type well regions 25, 26 are ion implanted, and annealed in an N2 atmosphere, thereby forming the P+ type base region 35 of an NPN bipolar transistor the region 25 and simultaneously the P<+> type source, drain regions 36 of a PMOS transistor in the region 26. Then, an interlayer insulating film 37 is formed on a whole surface, an opening 38 is formed at a predetermined part, a polysilicon layer 39 is grown in contact with part of the source, drain regions 32 of a memory cell and the region 35, annealed in a POCl3, doped with phosphorus, and diffused in the region 35, thereby forming the N<+> type emitter region 40 of the bipolar transistor.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention provides a dynamic RAM (Random A
The present invention relates to a method of manufacturing an i-CMOS device, which can be applied to memory devices such as access memory (access memory) and static RAM.

(Prior art) The 81-CMOS device (9 devices integrating bipolar transistors and CMOS Lanzosters), which has been developed for a long time, is an inexpensive but low-speed device that integrates an A/gate CMOS transistor and a bipolar transistor. , high-speed Sif-) CMOS transistors and bipolar transistors have been developed into integrated devices.

Here, CMOSMOS transistors are used for desotal signal processing by taking advantage of their high integration and low power consumption.
Nono Iborad 2 Nnostar has been used primarily for output circuits, taking advantage of its high speed and high output current characteristics.

This i-CMOS device has been formed by a process based on a bipolar process from the viewpoint of placing importance on the characteristics of a bipolar transistor. Therefore, there are steps such as stacking a Nu epitaxial layer on a P-type substrate, and forming a high-concentration N-type diffusion layer on a Pa substrate to reduce collector resistance before forming the epitaxial layer. Compared to CMO8 semiconductor devices, it required a longer and more complicated process flow.

On the other hand, memory elements, especially dynamic RAM and static RAM, which have been developed for the purpose of higher integration and larger capacity, are being implemented with CMOS peripheral circuits for the purpose of higher functionality, higher speed, and higher stability. In addition, consideration is being given to using bipolar transistors in part of the circuit for the purpose of further speeding up the process.

However, since the conventional Bi-CMOS device requires a complicated and long process flow as described above, it is difficult to apply it to a memory device where high yield and low cost are essential conditions.

As a result of intensive research, the Proceedings of the S.
Symposium of VLS I Technology
ogy) 1983-September.

A method for obtaining an at-cMO8s structure using a simple process flow as disclosed in pages 40 to 41 was developed, and an example of its application to static RAM is the IE
EEE Journal of 5olid-8tat
eCircuits) VOL, 5C-19, m
5, October 1984, P557-P563.

FIG. 5 shows a cross-sectional view of a Bi-CMOS device applied to the static RAM. The method for manufacturing this element is as follows.

■ Prepare a P-type substrate 1.

(2) Field isolation process is performed to form field oxide film 2.

(2) In the NPN bipolar transistor portion, an N-fel region 3 is formed to serve as the collector.

■ NMO8) Perform channel implantation 4 of run ν star, and at the same time perform P of /4 Ebora transistor.
- forming a pace area 5;

■ PMO8) Perform channel implantation of lansosta.

(f) Turning is performed to form the pole 6 of the PMOS transistor and the P-) of the NMOS transistor.

(2) NMO8) N+ source/drain regions 7 of the Lannostar, N+ emitter regions 8 of the NPN bipolar transistor, and N+ collector extraction regions 9 are formed by ion implantation.

(2) P+ source/drain regions 1O of the PMOS transistor and P+ paste extraction regions 11 of the NPN bipolar transistor are formed by the same ion implantation method.

■ Form an intermediate insulating film.

Form an O contact hole.

■ Form wiring.

0 Form a surface stabilizing film.

That's all.

(Problems to be Solved by the Invention) However, in the conventional Bi-CMOS device manufacturing method as described above, firstly, the channel implantation of the NMOS transistor and the base region formation of the non-polar transistor are performed at the same time. Since this is done by ion implantation, it has the following drawbacks. That is, the ion implantation at this time was performed at 100 KeV in order to prevent punch-through between the emitter and collector of the Pipo2 transistor.
, about 3 x 1012 cIfI-") #) It requires a deep and deep ion implantation. For this reason, (1) the NMOS transistor requires an even shallower channel implantation area.

■ NMO8) Lansostar has a large substrate effect even when using a low-concentration substrate due to dense and deep channel implantation. As a result, the phase transfer characteristics of the NMOS transistor used as the /# transistor are deteriorated. Further, in a dynamic RAM which is normally used by applying a negative potential to the substrate, the threshold voltage Vt of the NMO8) run source becomes large, which deteriorates the performance of the device.

(2) For the same reason as (2) above, the junction capacitance between the N+ source/drain region/P type substrate increases, and the increase in load capacitance deteriorates the performance of the circuit.

A problem arises.

Second K: In the conventional manufacturing method described above, since both the base and emitter regions of bipolar transistors are formed by ion implantation, defects caused by ion implantation may occur in the base and emitter regions.
There is a problem in that this tends to appear as an increase in inter-emitter leakage current.

This invention has been made in view of the above points, and aims to provide a method for manufacturing a Bi-CMO8 element that can eliminate the above conventional problems. , in a method for manufacturing a Bi-CMO8 element,
The source/drain region of the PMOS transistor and the base region of the bipolar transistor are formed simultaneously, and the emitter region of the bipolar transistor is formed by impurity diffusion from a polysilicon layer or a polycide layer doped with N-type impurities. Yes (Function) In the above method, the source-drain region of the PMO8) run source and the space region of the bipolar transistor are simultaneously formed.・The NMOS transistor is formed independently of the formation of the base-x region of the bipolar transistor. become. In addition, since the emitter region of a bipolar transistor is formed by impurity diffusion from a polysilicon layer doped with N-type impurities or a polycide layer, emitter regions caused by crystal defects caused by ion implantation are also avoided.
The increase in base-to-base leakage current is now limited to that which occurs during the formation of the pace region, and is less likely to occur.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

First, a first embodiment will be described with reference to FIG.

In the first embodiment, after forming the MOS transistor, the capacitor part of the memory cell is formed as a stacked capacitor with a three-layer structure of polysilicon, dielectric film, and polysilicon, and the peripheral A dynamic RAM employing eight at-CMO elements in its circuit is taken as an example.

In FIG. 1(a), 21 is a P-type silicon substrate;
It has a concentration of about 1 E14-1 E16 atoms/. ζop type silicon substrate 21 at 1000"C, 1
Oxidize the surface in an H110R atmosphere for about 20 minutes,
A silicon dioxide film (hereinafter abbreviated as oxide film) 22 with a thickness of about 6000^ is formed. Then, this oxide film 22 has
Windows 23 are opened at the portions where the pair of N-type well regions will be formed using a known photolin etching technique.

After that, on the surface of the substrate 21 exposed through the window 23,
By performing oxidation treatment at 1000° C. for about 50 minutes in an OT atmosphere, a thin oxide film 24 with a thickness of about 500λ is formed. After that, using the thick oxide film 22 as a mask, the window 23 is
Through, “P”, 200 KaV, 5E1
By performing ion implantation into the substrate 21 under the conditions of 2 tons/, -, and then performing an annealing-dry twin process at 1200° C. for about 240 minutes, the ions of the substrate 21 are implanted as shown in FIG. 1(b). The first part (corresponding to the window 231C) is shown in FIG. A second N-type well region 25° 26 is formed. This first. The second N-type well regions 25 and 26 are formed to have a surface concentration of about I E 16 atom”/cd t and a depth of about 3.5 μm.
The N-type well region 25 is the NPN bipolar transistor forming part C1, the second Nu well region 26 is the PMO8) LANSOSTER forming part, and the substrate regions other than these well regions are the NMOS) LANSOSTER forming part A, the memory cell forming part. It becomes B.

Thereafter, after removing all the oxide films 22 and 24 on the surface, a thick oxide film 11 of approximately 6000λ for isolation between elements is formed using the known LOGO8 technique as shown in FIG. 1(b).
G27 is formed, and furthermore, on the element region other than the oxide film forming part, 3 which becomes the r-to insulating film of the MOS transistor is formed.
An oxide film 28 having a thickness of 00λ is formed.

Next, a polysilicon layer for forming the r-) electrodes of the MOS),)nstar was deposited on the entire surface to a thickness of about 3,600 mm.
POCJ at 0℃! The polysilicon layer is doped with concentrated N by heating for 7 hours in an atmosphere. Here, the phosphorus concentration of the polysilicon layer is set to approximately 5 E 'l Q
I am using atoms7-. Then, by repeatedly turning this thick N-type polysilicon layer using a known photolithography and etching technique, as shown in FIG. Part 8. PMOSMOS transistor portion D(
On the second N-type well region 26, a Y-toe electrode 29 of a MOS transistor is formed. At this time, word line 30 is simultaneously formed of an N-type polysilicon layer.

Next, as shown in FIG. 1(d), the first and second N-type well regions 25 and 26 are covered with a photoresist/one turn 31 using a known photolithography technique. However, the collector extraction region forming portion of the first ONu well region 25 (bipolar transistor forming portion) is not covered with the photoresist pattern 31. Then, using the photoresist pattern 31 as a mask,? 3As”,
55KeV.

5E1510n8z-, ions are implanted into the substrate 21 as shown in FIG.
N at 900℃ for about 30 minutes to activate ions.
, by performing annealing in an atmosphere as shown in Figure 1(e).
As shown in FIG. 2, an N+ source 6 drain region 32 of an NMOS transistor is formed in the NMOS transistor forming portion A and the memory cell forming portion B of the substrate 21, and at the same time, a collector extraction region of the first Nu well region 25 is formed. An N+ reflector extraction region 33 of the partial KNPN/J-5 transistor is formed. Note that from FIG. 1(e) onwards, the N+ collector extraction region 33 is indicated by a broken line, and it is noted that since the N medium region is formed in the N type well region, the p-n
This is because no bonding occurs.

This time, as shown in FIG. 1(e), the substrate 21ONMO
8) Cover the runster forming portion A, the memory cell portion forming portion B, and the collector extraction region forming portion of the first N-type well region 25 with a photoresist pattern 34 using a known photolithography technique. Then, by making the photoresist pattern 34 wx, 'BF',
Ion implantation was performed into the first and second N-type well regions 25 and 26 under the conditions of 70 KeV and IE 1410"/di as shown in FIG. 800℃ above, 3
By annealing in N atmosphere for about 0 minutes,
As shown in FIG. 1(f), the first Nu well region 25
P+ base region 3 of the NPN spiral transistor inside
5 and at the same time in the second N-type well region 26.
P+ source/drain regions 36 of the OS transistor are formed. Note that the ion implantation when forming this P+ region is performed at a concentration of IE 14 tons/6I, which is about an order of magnitude lower than the normally used concentration for forming the P medium region. This is because the leakage current between the emitter and pace of the transistor was taken into consideration. However, as will be shown later, in this embodiment, the emitter formation method is a diffusion method from polysilicon (DOPO8 method; DOp
ed PO1ySilicon method),
It is also possible to increase the ion implantation concentration to the usual IE 15 j on 8 ion concentration.

Next, as shown in FIG. 1(f), an interlayer insulating film 37 is formed on the entire surface. The interlayer insulating film 37 is formed by CV D S using the APCVD method (atmospheric pressure CVD method).
An iOx film is formed to a thickness of 2000λ. After forming such an interlayer insulating film 37 over the entire surface, openings 38 are formed in predetermined portions of the glabellar insulating film 37 and the oxide film 28 below it, as shown in FIG. 1(f). Provided using photorin etching technology. Here, one of the openings 138 is provided above one of the source/drain regions 32 of the memory cell portion. The other one is provided above the base region 35 in the first N-type well region 25.

Once the opening 38 is formed in this way, as shown in FIG. The polysilicon layer 39 is in contact with the polysilicon layer 35.
KL is applied to the entire surface of the interlayer insulating film 37 using the PCVD method (low pressure CVD method).
D method) to a thickness of approximately 2000λ. Furthermore, in order to lower the resistance of the polysilicon layer 39, P
Oct! 7-E line vs. L atmosphere! j 7'k
The polysilicon layer 39 is doped with about 3E20 atoms/a11. At this time, the polysilicon layer 39
Further, phosphorus doped into the polysilicon layer 39 is diffused into the base region 35 through the opening 38, and the base region 35 contains the N0 emitter of the piebora transistor as shown in FIG. 1(h). 0 where region 40 is formed
Note that K in FIG. 1(h) also shows that the P+ base region 35 becomes deeper only in the N+ diffused portion due to the effect of the known double diffusion.

Thereafter, as shown in FIG. 1(h), the silicon layer 39 is patterned using a known photolithography and etching technique, thereby forming a lower electrode 41 (through one opening 38 of the memory cell) of the stacked middle capacitor of the memory cell. (connected to one of the source/drain regions 32 of the cell part);
Wires 42 (connected to the emitter region 40 of the NPN pieborad 2 insulator through the other opening 38) are each formed from the remaining polysilicon layer 39.

The subsequent steps are the same as those for a dynamic RAM using stacked capacitors as memory cells. That is, as shown in FIG. 1(i), an insulating film 43 of the stacked capacitor, in this case a thermal oxide film, is grown to a thickness of 100λ on the surface of the lower electrode 41 of the stacked capacitor made of polysilicon, and then this insulating film is grown. The upper electrode 44 of the capacitor is formed so as to cover the film 43 by forming - silicon on the entire surface;
Formed by phosphorescence and patterning. After this, as shown in FIG. 1(j), the entire surface K is coated as an intermediate insulating film.
A PSG film 45 is grown to a thickness of 7000° by the APCvD method and smoothed by annealing at 900°C. Furthermore, a contact hole 46 is opened, a wiring metal layer is grown, and this metal layer is etched using photolithography and etching technology. A metal wiring layer 47 is formed by turning. Note that as the wiring metal layer, AI! -1.0% S1 is formed to a thickness of 10,000^ by the Sudak method. As explained above, in the first embodiment, the source/drain region 36 of the PMO8) and the base region 35 of the bipolar transistor are was formed at the same time, N
The MOS transistor can be formed independently of the formation of the base region 35 of the No. 1 Ibora transistor. Therefore, the substrate bias effect of the NMOS transistor does not become large in connection with the formation of the base region of the 9-ipolar transistor, and even in devices such as dynamic RAM that are used with a negative bias applied to the substrate, the characteristics of the NMOS transistor do not change. No adverse effects.

Further, the junction capacitance between the N+ source/drain region/P type substrate does not increase, and the shallow channel inductance becomes inert.

In addition, in the first embodiment, since the emitter region 40 is formed by impurity diffusion from the polysilicon layer 39, it is possible to prevent the crystal defects caused by crystal defects caused by ion implantation between the emitter and the base of the spiral transistor. The increase in leakage current is limited to that which occurs when the base region 35 is formed, and is less likely to occur. Moreover, since the polysilicon layer 39 for forming the lower electrode 41 of the stacked capacitor can be used as the polysilicon layer 39 for forming the emitter region 40, there is no increase in the number of steps and the 81-CMOS dynamic RAM can be formed.

In the first embodiment as described above, when forming the emitter region, phosphorus was diffused into the polysilicon layer by annealing in POα atmosphere, but in the second embodiment,
It is also possible to dope phosphorus into the polysilicon layer by ion-implanting 31p+ (phosphorus). In that case, the specific conditions for ion implantation are "P", 30KaV,
The condition IE161onsz- is used. Then,
Phosphorus in the polysilicon layer peaks at 10”°1 ounces7
S10!, which has a concentration of about -, does not adversely affect the characteristics of the dynamic RAM portion, and is formed on the polysilicon layer by a thermal oxidation method. Membrane (cover/zeshita insulation)
This has the advantage of making it easier to control the film thickness. Furthermore, the ion implantation method has the great effect of reducing variations in the characteristics of bipolar transistors because it is easy to control the amount of impurities. Note that it is also possible to implant ions of 7δS+, and in that case, since the diffusion coefficient of A8 is smaller than that of phosphorus, the depth of the emitter region can be made shallower, making it easier for heat treatment in the post-process. This has the effect of reducing restrictions. In other words, punch-slip between the emitter and collector can be made less likely to occur.

In addition, impurity doping into the polysilicon layer by ion implantation is possible by controlling the implantation energy.
No crystal defects are caused in the mold silicon substrate 21 due to ion implantation. Therefore, as in the first embodiment, an increase in leakage current between the emitter and base is less likely to occur.

FIG. 2 shows a third embodiment of the present invention, in which a Brainer type capacitor is used for the dynamic RAM memory cell and a polycide structure is adopted for the bit line. In this third embodiment, As shown in FIGS. 2(a) and 2(b), a thick oxide film 27 for isolation between elements is placed at LOCO8.
The same steps as in the first embodiment shown in FIG. 1 are carried out until formation by the method. Therefore, up to that point, the same parts in the drawings will be given the same reference numerals and the explanation will be omitted.

Dynamic RAM using Brainer type memory cells (
In a dynamic RAM (based on the brainer type and a trench type memory cell that forms a gear/intermediate hole in the groove), the capacitor in the memory cell section is generally
MOS) Formed in a process before forming the MOS. After forming a thick oxide film 27 by the LOCO8 method, an oxide film 51 is formed on the element region as shown in FIG. 2(b).
is formed by thermal oxidation. Here, a thermal oxide film with a thickness of 100^ was formed as the oxide film 51. Next, a polysilicon layer 52t-LPCVD which will become the upper electrode of the capacitor 2I is formed.
The film was grown on the entire surface to a thickness of approximately 1500λ using the POα method.

By heating the layer in an atmosphere for 7 hours, a thick layer of N is deposited to form a silicon layer. Thereafter, this polysilicon layer 52 is turned by a known photolithography/etching technique, and the polysilicon layer 52 is left as shown in FIG. 2(b).
2 becomes the upper electrode of the cano I-shita. Subsequently, the oxide film 51 (capacitor insulating film) is removed from unnecessary portions. After that, as shown in FIG. 2(b), MOS is formed by thermal oxidation.
The oxide film 28, which will become the gate insulating film of the transistor, is
An oxide film 53 of about too much thickness is formed on a polysilicon layer 52 having a thickness of λ on the element region, and is doped with a deep N type at the same time.

^Make it thick.

Then, the second cause (c), (yu, (e), (f
), similarly to the first embodiment, the formation of the P-metal electrode z9 of the MOS transistor, the formation of the source/drain region 32 of the NMOS transistor and the collector extraction region 33 of the bipolar transistor, and the formation of the PMOS transistor
The transistor source-drain region 36 and the base region 35 of the bipolar transistor are formed simultaneously. At this time, of course, the photoresist A-turns 31 and 34 are used as masks for ion implantation.

Next, as shown in FIG. 2(f), an interlayer insulating film 54 is formed on the entire surface, and the film is coated with C'VDSiO by APCVD.
After forming the interlayer insulating film 54 to a thickness of 000λ, a desired region of the interlayer insulating film 54 and the oxide film 28 thereunder, here, a portion above one of the source/drain regions 32 of the memory cell portion connected to the bit line, and a bipolar film are formed. An opening 55 is formed above the base region 35 of the transistor by a known photolithography/etching technique.

Next, the source/drain region 32 and the base region 35 are contacted through the opening 55 as shown in FIG. 2(g).
As shown in , the W (tungsten)-polycide layer 56
is deposited on the interlayer insulating film 54. For details, please see LP
By growing 1500mm silicon using the CVD method and heat-treating it at 880°C in a PO atmosphere,
After doping to a high density Nff1, a W-polycide layer 56 is obtained by growing W-St (tungsten silicide) to a thickness of 2500λ using the 4-vine method. In the process of obtaining this W-polycide layer 56, an N-type impurity, here phosphorus, is diffused from the W-polycide layer 56 through the opening 55 into the space region 35 of the bipolar transistor, and as shown in FIG. ), an N+ emitter region 57 of a bipolar transistor is formed within the base region 35. After that, the W-polycide layer 56 is repeatedly turned by a known technique, and as shown in FIG. 58 and a wiring 59 connected to the emitter region 57 of the bipolar transistor are formed from the remaining W-polycide layer 56, respectively.

The subsequent steps are the same as those for forming a normal metal wiring layer. That is, as shown in FIG. 2 U), the intermediate insulating film 6
0, here P S G IN (PffiOe=20
WtX) is grown on the entire surface and smoothed by annealing at 900°C. After further drilling the contact hole 61,
AI! -1.0% 81 layers of 10,000λ stripes are formed and patterned to form a metal wiring layer 62.

It should be noted that the impurity dope produced by the ion implantation method shown in the second embodiment can also be fully applied to the W-, t21J side structure of this third embodiment, reducing the variation in characteristics of bipolar transistors. It never loses its effect. In particular, the W-polycide layer is
The sheet resistance ρ8 is 1 compared to the doped polysilicon layer.
Because of the small size, there is also the effect that the amount of N-type impurity to be doped is no longer limited by the resistance value.

Also in the third embodiment as described in detail above, the source/drain region 3 of the PMOS transistor is
6 and the base region 35 of the bipolar transistor are formed at the same time, it is clear that the NMOS transistor can be formed independently of the base region 35 of the bipolar transistor. Since the 1,000-mitter region 57 of the bipolar transistor is formed in this way, the same effect as in the first embodiment can be obtained. Moreover,
As the W-polycide layer 56 for forming the emitter region,
W- for forming a bit line essential to the memory cell part
Since the polycide layer 56 can be used, the third embodiment also has the effect of forming a Brainer type memory cell dynamic RAM without increasing the number of steps, as in the first embodiment.

FIG. 3 shows a fourth embodiment of the present invention, in which the manufacturing method of the present invention is applied to a static RAM that uses a resistive load type free-lag frog circuit 71 as a memory cell as shown in FIG. . The resistors R1 and R2 serving as the load are generally made of polysilicon and have a resistance of 1012 to 1013 tons.
A high resistance ion-implanted phosphorus of z- is used, and the PMO
Made after the formation of the S transistor.

In the fourth embodiment shown in FIG.
As shown in FIG.
The same steps as in the first embodiment shown in FIG. 1 are carried out until the simultaneous formation of . Therefore, up to this point, the same parts in the figures are denoted by the same reference numerals, and the description thereof will be omitted.

Next, as shown in FIG. 3(f), an interlayer insulating film s t (cvosio, film) is formed on the entire surface, and an opening 82 is opened in this and the oxide film 28 below it. This embodiment is basically the same as the first embodiment, and the opening 82 is formed above one of the source/drain regions 32 of the memory cell section and above the base region 35 of the bipolar transistor.

Subsequently, a polysilicon layer 83 is formed on the glabella insulating film 81 by LPCVD so as to contact one of the source/drain regions 32 and the space region 35 through the opening 82 as shown in FIG. 3(g). Here, since the polysilicon layer 83 is used as a high resistance load, the thickness is set to 1500 mm. Furthermore, for the purpose of improving and stabilizing the temperature dependence of the resistance value, phosphorus was changed to "P" at 30KeV.
, Ion implantation was performed under the conditions of 1E1310n+l/cI/I.

Next, by patterning the polysilicon layer 83 using a known technique, a high resistance load 84 is applied to the memory cell portion of the remaining polysilicon layer 83 as shown in FIG.
and the base region 3 of the bipolar transistor
A polysilicon layer 83 is left in the portion in contact with 5. The nine polysilicon layer 83 remaining in the portion in contact with this space region is particularly designated by the reference numeral 85.

Next, the area other than the polysilicon layer 85 is shown in FIG. 3 (1).
As shown in FIG. 3, it is covered with a resist pattern 86 using a known photolithography technique. Then, using the resist pattern 86 as a mask, 30
KeV t “P”, 1, 0E1510”/
Ion implantation is performed under the conditions of 'gd. This process is known as selective diffusion, and is a well-known technique commonly used in static RAMs using high resistance polysilicon loads.

After that, heat treatment is performed. Then, the Nu impurity doped into the polysilicon layer 85, in this case phosphorus, is diffused from the polysilicon layer 85 into the base region 35 of the bipolar transistor, and the base region 35 is doped with the material shown in FIG.
An N+ emitter region 87 is formed as shown in j).

After this, the wiring process is the same as in the first and third embodiments. First, as shown in FIG.
A SG film (PH11=20 wtX) is laminated. The reason why the intermediate insulating film 88 has a two-layer structure is to prevent impurities from diffusing into the polysilicon high-resistance load 84 from the intermediate insulating film (the upper PSG film).

After that, this intermediate insulating film 88 is smoothed by annealing at 900°C, and a contact hole 89 is formed, and then a metal wiring N90 is formed by turning a 10,000λ thick strip of M-1,0XSi. do.

Also in this fourth embodiment, since the source/drain region 36 of the PMO transistor and the space region 35 of the bipolar transistor are formed at the same time, it is clear that the NMOS transistor can be formed independently of the space region 35 of the bipolar transistor. Moreover, since the emitter region 87 of the bipolar transistor is formed by diffusion of impurities from the polysilicon layer 85, the first
The same effect as in the embodiment can be obtained. Moreover, since the polysilicon layer 83 for forming a high resistance load can be used as the polysilicon layer 85 for forming the emitter region, the B1-CMOS static RAM can be formed without increasing the number of steps.

In each of the above embodiments, the source/drain regions of the NMOS transistor and the collector lead-out region of the bipolar transistor were first formed, and then the source Φ drain region of the PMO8) and the space region of the bipolar transistor were formed. , the order can also be reversed.

(Effect of the invention) As explained in detail above, according to the method of this invention,
Because the source/drain regions of the PMOS transistor and the space region of the bipolar transistor were formed at the same time,
NMO8) The run source can be formed independently of the space region of the bipolar transistor, so the formation of the bipolar transistor does not adversely affect the characteristics of the NMOS transistor, and the capacitance between the N+ source/drain region and the P-type substrate can be reduced. High performance NM with no increase
O8) Lanzosta can be obtained, and the process is simplified because shallow channel in-plant silane is not required. In addition, since the emitter region of the bipolar transistor is formed by impurity diffusion from the polysilicon layer or the 4-Si layer, it is possible to prevent an increase in leakage current between the base and emitter of the bipolar transistor due to crystal defects caused by ion implantation. The characteristics of the pyra transistor can also be improved. Moreover,
The polysilicon layer and polycide layer for forming the emitter region can be used for dynamic RAM or static RAM.
In 81-CMO, a polysilicon layer for forming a lower electrode of a capacitor, a polycide layer for forming a pit line, or a polycide layer for forming a high resistance load can be used.
The present invention can be applied to S dynamic or static RAM manufacturing methods to form these RAMs without adding one step.

[Brief explanation of the drawing]

FIG. 1 is a process sectional view showing the first embodiment of the method for manufacturing a Bl-CMOS device of the present invention, and FIGS. 2 and 3 show the third and fourth embodiments of the present invention. 4 is a circuit diagram of a static RAM memory cell using a resistive load, and FIG. 5 is a sectional view of a Bl-CMOS device in which a resistive load is applied to a conventional static RAM. 21... P-type silicon substrate, 25... N-type well region of band 1, 26... second N-type well region, 28...
- Oxide film, 29... r-meter electrode, 31... photoresist pattern, 32... source/drain M region, 34
... Photoresist pattern, 35 ... P+ base region, 36 ... Source/drain region, 37, 54.8
1... Interlayer insulating film, 38, 55, 82... Opening part,
39°83.85...Polysilicon layer, 5 stones...W
- polycide layer, 40, 57.87...N+ emitter region.

Claims (2)

[Claims] (1) (a) forming a pair of N-type well regions in a P-type silicon substrate; (b) forming a PMOS transistor and an N-type well region on one surface of the N-type well region and the surface of the P-type silicon substrate region;
(c) After that, by performing ion implantation with the surface of the N-type well region covered with a mask, the source of the NMOS transistor is formed in the P-type silicon substrate region.・A step of forming a drain region; (d) Before or after this step, contrary to the above, ion implantation is performed with the surface of the P-type silicon substrate region covered with a mask, so that one of the N P in the type well area
Forming the source and drain regions of the MOS transistor,
At the same time, forming a P-type base region of a bipolar transistor in the other N-type well region; (f) forming a polysilicon layer or a polycide layer on the insulating film, the polysilicon layer or polycide layer partially contacting the surface of the base region through the opening; layer or polycide layer contains N.
and (g) forming an N-type emitter region of a bipolar transistor in the base region by diffusing N-type impurities from the polysilicon layer or polycide layer. B
A method for manufacturing an i-CMOS device. (2) The method for manufacturing a Bi-CMOS device according to claim 1, wherein the step of introducing N-type impurities into the polysilicon layer or polycide layer uses an ion implantation method.