JPH01167080U - - Google Patents
Info
- Publication number
- JPH01167080U JPH01167080U JP6213888U JP6213888U JPH01167080U JP H01167080 U JPH01167080 U JP H01167080U JP 6213888 U JP6213888 U JP 6213888U JP 6213888 U JP6213888 U JP 6213888U JP H01167080 U JPH01167080 U JP H01167080U
- Authority
- JP
- Japan
- Prior art keywords
- printed circuit
- board
- circuit board
- multilayer printed
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 1
Description
第１図は本考案にかかる多層プリント基板の一
部を示す斜視図、第２図は同じく基板ユニツトと
プリントフイルムに設けられた端子パターンの接
続を示す図、第３図は本考案の他の例を示す斜視
図、第４図は従来の多層プリント基板の一部を示
す斜視図である。
１０……多層プリント基板、１１……基板ユニ
ツト、１２……表面実装部品、１３……プリント
フイルム側端子パターン、１４……Ｉ／Ｏピン引
き出し用プリントフイルム、１５……基板ユニツ
ト側端子パターン、１６……コネクタ、１７……
スルーホール。
FIG. 1 is a perspective view showing a part of a multilayer printed circuit board according to the present invention, FIG. 2 is a diagram similarly showing the connection between the board unit and the terminal pattern provided on the printed film, and FIG. A perspective view showing an example. FIG. 4 is a perspective view showing a part of a conventional multilayer printed circuit board. 10... Multilayer printed circuit board, 11... Board unit, 12... Surface mount component, 13... Printed film side terminal pattern, 14... Printed film for drawing out I/O pins, 15... Board unit side terminal pattern, 16... Connector, 17...
Through hole.
Claims (1)
リント基板１０において、各基板ユニツト１１に
対する入出力端子を、一枚のＩ／Ｏピン引き出し
用プリントフイルム１４上にまとめて前記基板ユ
ニツト１１の層間に積層して接続し、その一部を
多層プリント基板１０の側方に露出させ、該露出
部分にコネクタ１６を接続することを特徴とする
入出力端子の構造。 In a multilayer printed circuit board 10 formed by stacking a plurality of board units 1, input/output terminals for each board unit 11 are placed together on a single printed film 14 for drawing out I/O pins, and placed between the layers of the board unit 11. An input/output terminal structure characterized in that they are stacked and connected, a part of which is exposed on the side of a multilayer printed circuit board 10, and a connector 16 is connected to the exposed part.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6213888U JPH01167080U (en) | 1988-05-13 | 1988-05-13 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6213888U JPH01167080U (en) | 1988-05-13 | 1988-05-13 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01167080U true JPH01167080U (en) | 1989-11-22 |
Family
ID=31287770
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6213888U Pending JPH01167080U (en) | 1988-05-13 | 1988-05-13 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01167080U (en) |
-
1988
- 1988-05-13 JP JP6213888U patent/JPH01167080U/ja active Pending
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