JPH01164127A - Compressing/expanding processing device - Google Patents

Abstract

PURPOSE:To prevent compressing/expanding processing speed from being restricted by the access time of a reference line buffer by performing both the write processing and the read processing of reference line data within one step according to a prescribed clock. CONSTITUTION:The title device consists of a compressing/expanding processing LSI 10, the reference line buffer SRAM 16A and a clock generator 21, and one machine cycle is realized by two clocks from the clock generator 21. In a first halt cycle, the compressing/expanding processing LSI 10 writes the image data of a compressing/expanding processed result in the SRAM 16A through a data bus 15A, and in a latter half cycle, it reads out the reference line data written in the SRAM 16A, and executes alternately the operations of write and read in one cycle. Thus, the compressing/expanding processing speed is never restricted by the access time of the reference line buffer.

Description

Detailed Description of the Invention [Objective of the Invention] (Industrial Application Field) The present invention relates to a compression/decompression processing device for binary data, and in particular, the present invention relates to a compression/decompression processing device for binary data, and in particular, the present invention relates to a compression/decompression processing device for binary data. The present invention relates to a compression/decompression processing device that is not limited by access time.

(Prior Art) In a conventional compression/decompression processing device that compresses and decompresses input binary data in a pipeline manner, it takes 11 steps to read reference line data from a reference line buffer. One step was required to write reference line data to the line buffer. For this reason,
The execution speed of the compression/expansion processing device for 21st straight data depends on the access time of the reference line buffer, and the processing speed is limited by this.

(Problems to be Solved by the Invention) The present invention has been made in view of the above circumstances, and its purpose is to ensure that the speed of compression/decompression processing is not limited by the access time of the reference line buffer that stores reference line data;
Static RAM 6 or FIFO according to your needs
It is an object of the present invention to provide a compression/decompression processing device to which a (7"-night first-in, first-out) memory can be connected.

[Structure of the Invention (Means for Solving Problems and Their Effects) A compression/expansion processing device according to the present invention includes a clock generation means, a reference line buffer means, and a compression/expansion processing means. The clock generating means generates a clock having a predetermined frequency. The compression/expansion processing means decompresses the input code data by referring to the reference line data read from the reference line buffer means in the decompression processing mode, using a clock having a frequency of a bar having a predetermined frequency as one step. , writes the decompressed image data as reference line data into the reference line buffer means, and in the compression processing mode writes the input image data as reference line data into the reference line buffer means, and reads it from the reference line buffer means. The input image data is compressed by referring to the reference line data. At this time, the process of loading the reference line data into the reference line buffer means and the process of reading the reference line data from the reference line buffer means are performed within one step according to the clock having the predetermined frequency.

When the reference line buffer means is a static RAM, the compression/expansion processing means includes a control means, an addressing means, and an input/output means. The control means generates a control signal for executing the write process and the read process, and the addressing means generates an address for the reference line buffer means in the write process and the read process.

Further, the input/output means inputs/outputs reference line data in the writing process and the reading process.

When the reference line buffer means is an F'IFO memory, the compression/expansion processing means includes a control means, an input means, and an output means.

The control means generates a control signal for executing the convolution process and the read process, and the output means outputs reference line data to the reference line buffer means in the write process.

Further, the input means inputs reference line data in the reading process.

A static RAM or an F'IFO memory can be connected to the compression/expansion processing means, and the control means performs the following according to the means of the reference line buffer connected to it.
1 for executing the convolution processing and the reading processing;
6 generates control signals. The data address output means outputs an address for the reference line/buffer means when a static RAM is connected as the reference line/buffer in the write process and the read process, and outputs an address for the reference line/buffer means,
When a memory is connected, reference line data is output to the reference line buffer means, and the r-data input/output means outputs static RA, 'il as the reference line buffer in the write process and the read process.
When PIF'O memory is connected as the reference line buffer, reference line data is input/output.When PIF'O memory is connected as the reference line buffer, reference line data is input.

(Example) A compression/expansion processing apparatus according to the present invention will be described in detail below with reference to the accompanying drawings.

First, the configuration of a first embodiment of a compression/expansion processing apparatus according to the present invention will be described with reference to FIG.

In the first embodiment, the compression/expansion processing device includes a compression/expansion processing LSI IO, a reference line buffer 16, and a clock generator 21. Compression/expansion processing LSI
10 is a control unit 20 that generates a control signal, a decoding generation processing unit 17 that compresses and expands input binary data,
It is comprised of a data address output section 19 that outputs data or addresses, and a data input/output section 18 that inputs or outputs data. Compression/expansion processing LS11
o receives clock 2CLK from clock generator 21.

An input path 11 and an output path 12 each having a width of 1 byte are connected to the compression/decompression processing LSI JO. In the decompression processing mode, code data is received from the input path 11, and decompressed image data is outputted to the output path 12. In the compression processing mode, image data is received from the input path 11, and compressed code data is outputted to the output path 12.

The role of the reference line buffer 161/2 is to hold reference line data. That is, the reference line data obtained through the decompression processing is held until the next line is processed, and the reference line data is sent to the compression/decompression processing LSI 10 in synchronization with the processing of the next line.

In the first embodiment, 1 is used as the reference line buffer Z5A.
Static RAIVI (SRAM) 16 A
This is an example in which the LSI 10 is connected to a compression/expansion processing LSI 10. S.R.
As AM16A, for example, T sold by Toshiba
0180 is used.

When an SRAM is used as the reference line buffer 16, the data address output section 19 functions as an addressing section. As shown in Figure 2, the compression/decompression processing LSI
The line memory address terminal Rkg-0 of Jo and the buffer area switching address terminal RAM are SRAM
16 1/2 address input terminals Al0-0. Line memory address RAIO is not connected. The read data terminal RD7-0 of LSI J o is the data input/output terminal L1-8 of SRAM 16 1/2.
It is connected to the. Also, the side of the memory write signal terminal of LSI 10 and the memory read terminal MRD are connected to SR.
AM 16 1/2 write enable terminal WE and out! , is connected to the toe enable terminal OE. S.R.A.
The chip select terminal C8 of M 16 1/2 is grounded. The control signal m and MRD correspond to the control signal 14k from the control section 20 in FIG.

Next, referring to FIG. 3, an explanation will be given of the operation in the case of the double-paper type, which uses one SRAM as a reference line buffer.

The decoding and generating processing unit 17 continuously decompresses the image at a rate of 1 byte per machine cycle, that is, per step, so in order to have a commensurate transfer rate of reference line data, it is necessary to decompress the image at a rate of 1 byte per machine cycle, that is, per step.

Both reading of the reference line data and looking at the reference line data resulting from decompression processing must be performed every thin cycle. For example, a 200 ns machine cycle is divided into 71-f cycles of 100 ns each, and the decompression processing result is written in the first half of the -7 cycles.
The reference line is read in the second half of the 7th cycle. This is shown in FIG.

In Figure 3, the 100 ns black of Rio and Ri2CLKIi.

It is. One machine cycle is realized by these two clocks. In the first half cycle, the memory write signal i is set to L, and the compression/expansion processing LSI 1 is activated.

transfers the image data resulting from decompression processing to data bus 1.
Read data terminal RD7-0 to SRAM via 5A
16 Superior to A. Furthermore, in the second half of cycles /1-7, the memory read signal MRD is set to L in order to read the reference line data already written in the SRAM J e A. In this way, two operations, write and read, are performed alternately in one cycle. SRA in Figure 1
The M 16 A is used in a line-by-line DAP/FA system, and the areas (upper half and lower half of the RAM address space) are switched and used for each line. Therefore, the reading of reference line data and the writing of the decompression processing result always target different areas. This is why the buffer area switching signal RAM is inverted between the first half and the second half of the cycle. H if the line changes
and L is reversed.

Next, the configuration of a second embodiment of the compression/expansion processor 4 using a FIFO (first-in-n-first-out) memory IJJ6B as a reference line buffer will be described with reference to FIG. F
For example, NECm's μPO4110 is an IFO memory.
1C is used. In this example, the clock from the clock generator 21 is also supplied to the FIFO memory 16B. Further, the data address output section 19 works as a data output section. Further, the data input/output section 18 functions as a data input section. Therefore, the address generation section (not shown) of the data address output section 19 becomes unnecessary. The reference line data is sent to the FIFO memory 16 via the data bus 13B in accordance with a control signal on the control line 14B from the control unit 20.
B and read from FIFO memory 16B via data bus 15B.

In FIG. 4, compression/expansion processing LSI J o is FI
Data bus (write only) 1 for FO memory 16B
Data is output via 3B, and data is read via data bus (read only) 15B. At this time, read/write, enable, etc. are instructed via a plurality of controls 2I/14B. The connection example of the PIF'O memory 16B shown in FIG. 4 shows a single buffer system.

FIG. 5 shows details of the connection state between the compression/expansion processing LSI Jo and the FIFO memory 16B. Compression/expansion processing LSI
The write data terminal WD 7-0 of the FIFO memory 16B is connected to the data input 9;a terminal DIN 7-0 of the FIFO memory 16B. Write data terminal WD7-0 is the same as RA7-0 when using SRAM. Read data terminal RD7-OFiFIFO It is connected to the data out terminal DOUT7-0 of the FIFO memory 16B. The memory write terminal line of the compression/expansion processing LSI Z o and the memory read terminal MRD are connected to the write enable terminal WE and the read enable terminal RE of the FIFO memory 16B, respectively. In addition, the memory reset terminal MR8T of the compression/decompression processing LSu0 is used as the readout terminal of the FIFO memory 16B.
It is connected to the write terminal R8TW and the reset lead terminal R8TH. This memory reset terminal MR3T is
When switching to a new line, the write address and read address are initialized and set to the address of the first image of the line.

The clock is connected to the clock terminal 2CLK of the compression/expansion processing LSI 1o and the clock terminal w of the FIFO memory 16B.
Supplied to CLK and RCLK. System @ Signal Corridor and MR
D and MR8T correspond to control signal 14B in FIG.

The operation of the second embodiment will be explained with reference to FIG. 4
By outputting the signal MWR, the reference line data is written to the FIgB via the data bus 13B, and by outputting the signal MRD, the reference line data is written to the data bus 15B. Through this, PIF'Pi'e B glares at him. In this way, during instep length processing, the reference line data resulting from the expansion processing is stored in the FIFO memory 16B.
The control signal 1 is used to write the reference line data to the FIFO memory 16B and to read the reference line data that has already been written to the FIFO memory 16B.
FIG. 6 shows that 4B is performed almost simultaneously in one cycle. In Figure 6, clock 2
CL Arashi has a clock of 100 ns. One machine cycle (200 ns) is realized by these two clocks. In the first half of the /S-cycle, the memory write signal read and the memory read signal MD are set to L, and the compression/expansion process qLsIlO is performed as follows.
The result of the decompression processing is stored in the FIFO memory 16B from the write data terminal WD 7-0 via the data bus 13B. Also, in the latter half of the 71st cycle, the reference line data that had already been written to the FIFO memory 16B is
'WL protrudes from read data terminal RD7-0 via tabus 15B. In this way, two operations, write and read, are performed almost simultaneously in one cycle. MR8
When moving to a new line, T initializes the write address and read address and sets them to the address of the first image of the line.

Next, F is used as a reference line buffer for the compression/expansion processing device.
IFO (first-in first-out data) memory 16C1 and 16
The configuration of a third embodiment in which C2 is used in a double buffer system will be described with reference to FIG. As the FIFO memory, for example, two μPD41101C manufactured by NECM are used. In this example, clock 2.
FIFO memories 16C1 and 16C2 are also supplied. Further, the data address output section 19 works as a data output section. Further, the data input/output section 18 works as a data input section. Therefore, in this case as well, the address generator (not shown) for the data address output 1li1519 is unnecessary, as in the second embodiment. The reference line data is transferred to the FIFO memory I)16C1 via the data node xsr,z; according to the control line/14C signal from the control Wr20.
The reference line data that has already been written is read out from the FIFO memory 16C2 via the data bus 15C. In this way, the control signal 14C is used to store the reference line data resulting from the decompression process into the FIFO memory 16C1 during the decompression process, and to read out the reference line data already written in the FIFO memory 16C2.
This is done almost simultaneously within one cycle. Furthermore, by using the FIFO memory in a double buffer system, image data for two lines can be held. That is, the FIFO memory 16CK stores reference line data, and the expanded image data is stored in the FIFO memory 16c2 as the reference line data. Therefore, it becomes possible to replace the line where the error occurred with the image data of the previous line. In addition, even when the number of pixels on the l line is doubled, the FIFo memory 16c1
Reference line data for one line can be stored in and 16C2.

Figure M8 shows details of the connection state between the compression/expansion LSI 10 and the F'lFO mailers 16c1 and 16C2. Write data terminal WD 7-0 of compression/expansion LS110 is FIFO
Data in terminal DIN 7 of memories 16C1 and 16C2
-0. Write data terminal WD 7-
This is the same as RA7-0 when oFiSRAM is used. Read data terminal RD717 is FIFO memory 16C1 and 1
It is connected to the data out terminal DOUT 7-0 of 602. The memory write terminal of the compression/expansion LSI 10 and the buffer area switching terminal RAH are connected to the write enable terminal WE of the reference line buffer 16C2. The logical sum of the signals obtained by logically inverting the memory write terminal and the buffer area switching terminal RAM is connected to the write enable terminal WE of the reference line buffer 160. Memory lead terminal MRD dopa.

The logical sum of the logically inverted signal of the 7A area switching terminal RAH is connected to the read enable terminal RE of the reference writer/per, 7716C2. The logical sum of the memory read signal MRD and the buffer area switching terminal RAHO is connected to the read enable terminal RE of the reference line buffer 16C1. In addition, the memory reset terminal MR8T of the compression/expansion LSI 10 is connected to the reset write terminal R8TW of the FIFO memories 160 and 1602 and the reset lead terminal R8.
Connected to TR. Clock is compression/expansion LSI J
Clock terminal 2CLK of O and FIFO memory 16C
1 and 16C2 are supplied to clock terminals WCLK and RCLK. Control signal reading and MRD.

MR8T and logic ff-) are the control signal 14C in FIG.
Corresponds to K.

The operation of the third embodiment will be explained with reference to FIG. When the memory reset signal MR8T is output, reference line data is written to PIFMCI via the data bus 13C by outputting the memory write signal read, and when the memory reset signal MR8T is output. , the reference line data is read from the PIF076Cj via the data bus 15C. In this way, at the time of decompression processing, reference line data as a result of decompression processing is written to the FIFO memory 16C1, and
Reading out the reference line data written in the FO memory 16C2 is performed almost simultaneously in one cycle by the control signal 14CI/C. Furthermore, when the processing of the l line is completed, the i FxFo memory that has been writing is read, and the FIFO memory that has been reading is written. This will be explained in relation to a using FIG. In FIG. 6, clock 2CLK is a 100 ns clock. One machine cycle is realized by these two clocks. In the first half cycle, when the memory write signal read, the memory read signal, and the buffer area switching signal RAI (are set to L at the same time), the compression/expansion LSI
z.

writes the result of the decompression process to the FIFO memory 160 from the write data terminal WD7-0 via the data bus 15C. Further, in the latter half cycle, the reference line data already written in the FIFO memory 16C2 is read out. In this way, two operations, write and read, are performed alternately in one cycle. 16 of FIFO memory
Switching between CI and 16C2 is done using the 77 area switching ID RAM.
carried out by. This is why the other control signals, including the bar, 77 area switching signal RAH, are combined by multiple logic gates. Therefore, the reading of reference line data and the writing of the decompression processing results are always performed in different FIFO memories.

Next K, S as a reference line buffer for the compression/decompression processing device
The groove bottom of a fourth embodiment in which two RAMs (static RAMs) are used in a double buffer system will be described with reference to FIG. For example, Toshiba's TMM is an example of SRAM.
2018D is used.

SRAM as reference line buffers 16D and 16D2
When the data address output section 19 is used, the data address output section 19 is set to 7 and the signal section is used. The line memory address terminal RAIO of the compression/expansion LSI J o shown in FIG.
-0 is connected to the address terminal 110-0 of SRAMI 601, 16D2. The buffer area switching address terminal RAH is logically inverted and connected to the chip select terminal C8 of the SRAM 16D1, and is connected to the chip select terminal C8 of the SRAM 16D2 by If connection. L
Read data terminal RD7-0 of SIZO is SRAM
J601, 16D2 data input/output terminal I101-
8 is connected. The memory write signal terminal MWR and memory read terminal MRD of LSI J o are respectively S
It is connected to the write enable terminal WE and output enable terminal OE of RAMI 601 and 16D2. Iii'II control signal line, MRD and buffer area switching signal RAM are the control signal 14 from the control section 20 in FIG.
Corresponds to D.

The operation of the fourth embodiment will be explained with reference to FIGS. 3 and 12.

In the case of the fourth actual flow example, two SRAMs are connected as shown in FIG. 12, and the SRAMs are switched for each line.

In this case, compared to the case where one SRAM is used by switching the area for each line as in the first embodiment, it is possible to process lines twice the length.

In FIG. 3, clock 2 CLK is a 100 ns clock. One machine cycle is realized by these two clocks. Memory write signal MW in the first half cycle
When R is set to L, the compression/decompression processing LSI IO transfers the image data resulting from the decompression processing from the read data terminal RD7-0 to the SRAM I via the data bus 15D.
6 Write to D2. Furthermore, in order to read the reference line data already written in the SRAM 16 D 1 in the latter half cycle, the memory read signal image is set to L. In this way, two operations, write and read, are performed alternately in one cycle. SRAM16D1 in Figure 11
The 16D2 and 16D2 are used in a line-by-line double-paragraph system, and the SRAM is switched and used for each line. Therefore, the reading of reference line data and the loading of the decompression processing results are always performed in different SRAMs. Buffer area switching signal RAH is SRAM 16
Chip select terminal C of each of Dz and 16D2
This is why one side is connected to 8 with the logic inverted. If the line changes, H(!:L will be reversed.

With reference to FIGS. 1, 4, 7, 12, and 13, the data address output unit 19 of the compression/expansion LSI to
The operation of the data input/output unit 18 will now be explained.

100 is 1 cycle (200ns) when using SRAM as a reference line buffer in a double buffer method.
The control unit 20 outputs a signal FR8THF that separates the signal into the first half (100n, s) and the second half (100ns).

Reference numeral 101 is a signal FBUFA for switching the buffer for each line of the image, and is output from the control section 20. Committee → is No. 18 FR8THF 700 and signal F”
This is an exclusive-or-dirt circuit that generates a buffer area switching signal by performing exclusive ura-filling with BUFAlol. The output from the circuit 22 is used as a total 77 area switching value for the SRAM. 23 is SRaM's pa.

Register R for latching the far area switching signal 102
It is ADRH. 103 is a buffer area switching signal RADRH latched by the register RADRH23. Reference numeral 24 denotes a selector for selecting the signal output from the control section 2o and the far region switching signal. 104 is selector 2
This is the buffer area switching signal RAM selected by 4. When using the PIF'O memory as a reference line buffer in the double-balance method, the signal FBUFA
J OJ is selectively output. When SRAM is used, RADRH 103 is selectively output. Reference numeral 105 indicates address information sent from an address generation section (not shown) of the data address output section 19. This is address information when SRAM is used as a reference line buffer.

25 is SRAM address information 10 sent from the address generation section (not shown) of the data address output section 19.
This is a friend register RADR that latches 5. 10
6 is address information RADR of 5RAk latched in register RADR. 111 is FIFO memory write data from the data input/output unit 18; 107 is the control unit 20
This is the FIFO memory reset signal DMR8T from.

The selector 26 selects output data from the data 11 from the data input/output section 18 according to the control signal from the control section 2o, the memory reset signal DMR3T107 from the control@1 section 20, and the SRAM address information RADR106,
Output to reference line/buffer. When SRAM is used as a reference line buffer, selector 26 selects S
Select RAM 7 and RADR 106 and output.

When using FIFO memory, use the FIFO memory write team j' XLRD 111 and CDMR8T.
Select I07 and output. 108 is the SRAM address information selectively output by the selector 26 or the FI
This is the write data of the FO memory. When using the SRAM as a reference line buffer, the output 108 of the selector 26 and the output 104 of the selector 24 are output to the SRAM. Also, when the FIFO memory is conveniently used, they are output to the FIFO memory.

However, when using a FIFO memory with a single buffer, the buffer switching signal RAH104 is not necessary.

109 is image data ROI)T generated by #reading the code in the wl reading generation process 17.

Reference numeral 110 denotes image data RDTI which is the same as the image data obtained via the input path 11 for encoding in the decoding and generating processing section 12 . Reference numeral 27 indicates image data 109 and image data 110 according to the controller number from the control unit 20.
Select output data from and output. The selector 27 selects RDTI 110 when compressing, and selects RODT when decompressing.
Select ios. 111 is image data selected and output by the selector 27; The output image data is outputted as XLRD by the data address output section 1.
9 and data bus 15, and is output to interface transceiver XCVR 28 with 15B, 15C, and 150.

However, the output to the data address output section 19 is useful only when the FIFO memory is used as a reference line buffer. When using SRAM as a reference line buffer, image data is input and output. When using FIFO as a reference line buffer, read the image booter. 112 is image data read out from the reference line buffer via the transceiver XCVRl8't- which interfaces with the data bus. This image data is sent to the decoding and generation processing unit 17, and is used as a reference line image during two-dimensional encoding or to replace the previous line during error processing. 113 is a reference liner.

Image data read from the F, or LSI
This is image data output from 10.

Transceiver XCVR2! Control of i is performed by a signal from the control section 20.

[Effects of the Invention] According to the compression/decompression processing device of the present invention, the compression/decompression processing speed is not limited by the access time of the reference line buffer that stores reference line data, and the compression/decompression processing speed is not limited to static RAM (SRAM) or FIFO (data storage) according to needs. (first-in, first-out) memory can be connected.

Also, when using one FIFO memory, it can only be used in single buffer mode, but if you use two FIFO memories and switch the FIFO memory used for each line, you can use the previous line when processing an error. It becomes possible to replace Even in this case, according to the present invention, the processing speed is not limited.

Furthermore, by using a plurality of memories as reference line memories, it is possible to be freed from limitations imposed by the size of one line of image data.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration when one SRAM is used as a reference line buffer. FIG. 2 is a diagram showing details of connections in the configuration shown in FIG. 1. FIG. 3 is a timing chart showing the operation of the configuration shown in FIGS. 1 and 12. FIG. 4 is a block diagram showing a configuration when using a FIFO memory as a reference line buffer. FIG. 5 is a diagram showing details of connections in the configuration shown in FIG. 4. 6th
This figure is a timing chart showing the operation of the configuration shown in FIGS. 4 and 7. FIG. 8 is a block diagram showing four configurations when FIFO memory is used in a double buffer method. FIG. Figure 10 is a reference value for each symbol on the timing chart when using FIFO memory as the reference line buffer shown in Figure 6.See Figure 11. This is a block diagram showing the configuration when two SRAMs are used as line buffers. FIG. 12 is a diagram showing details of the connection of the configuration shown in FIG. 11. FIG. 13 is a diagram showing the configuration shown in FIG. It is a diagram showing in detail a part of the data input/output section 18 and data address output section 19 of the compression/expansion LSI J o shown in FIGS. 4 and 7. 10... Compression/expansion LSI, 16A, 16B, 16C1
゜16c2, 1601.1602... Reference line buffer, 21... Clock generator. Applicant's Representative Patent Attorney Takehiko Tsurie Director General of the Japan Patent Office Yoshi Yoshi 1) Takeshi Moon 1, Indication of Case Patent Application No. 63-126506 2, Title of Invention Compression/Expansion Processing Device 3, Person Making Amendment Relationship with Case Patent Applicant ( 307) Toshiba Corporation 4, Agent 3-7-2 Kasumigaseki, Chiyoda-ku, Tokyo January 24, 1989 7 Contents of amendment (1) “Figure 8” on page 30, line 16 of the specification "7th
"Fig." is corrected. (2) Similarly, on page 30, line 18, "It is a diagram." is corrected to "It is a diagram. Figure 8 is a diagram showing details of the connection of the configuration shown in Figure 7." .

Claims (5)

[Claims] (1) Clock generation means for generating a clock having a predetermined frequency, reference line buffer means for storing reference line data for two lines, and one clock having a frequency of 1/2 of the predetermined frequency. As a step, in the decompression processing mode, the input code data is decompressed by referring to the reference line data read from the reference line buffer means, and the decompressed image data is sent to the reference line buffer means as reference line data. In the write/compression processing mode, the input image data is written as reference line data into the reference line buffer means, and the input image data is compressed by referring to the reference line data read from the reference line buffer means. compression/expansion processing means, wherein the processing of writing reference line data into the reference line buffer means and the processing of reading reference line data from the reference line buffer means are performed according to the clock having the predetermined frequency. , in one step. (2) The reference line buffer means is a static RA
M, the memory area is divided into two parts corresponding to the lines, and the compression/expansion processing means performs the processing of writing the reference line data into one of the memory areas and the writing of the reference line data from the other memory area. control means for generating a control signal for executing a read process; and addressing means for generating an address for the static RAM in the write process and the read process, the control signal being switched line by line; The compression/expansion processing apparatus according to claim 1, further comprising: input/output means for inputting and outputting reference line data in the writing process and the reading process. (3) The reference line buffer means is a FIFO memory, and the compression/expansion processing means includes: a control means for generating a control signal for executing the writing process and the reading process; , an output means for outputting reference line data to the FIFO memory, and an input means for inputting the reference line data in the reading process. Decompression processing device. (4) The compression/expansion processing means includes: a control means for generating a control signal for executing the writing process and the reading process according to the connected reference line buffer; In the read process, when a static RAM is connected as the reference line buffer, an address for the reference line buffer means is output, and when a FIFO memory is connected as the reference line buffer, the address is output as a reference to the reference line buffer means. data address output means for outputting line data; and when a static RAM is connected as the reference line buffer in the writing process and the reading process, inputting and outputting reference line data; 2. The compression/expansion processing apparatus according to claim 1, further comprising data input/output means for inputting reference line data when a FIFO memory is connected as a buffer. (5) The reference line buffer means includes two memory means, and the compression/expansion processing means performs the processing of writing reference line data into one of the memory means and writing the reference line data from the other memory means. A control means for generating a control signal for executing the read process and a memory means to be subjected to the write process are switched for each line, and in the write process and the read process, Compression according to claim 1, characterized in that it comprises addressing means for generating an address, and input/output means for inputting and outputting reference line data in the writing process and the reading process. Decompression processing device.