JPH01163794A - Binary display panel picture display - Google Patents

Abstract

PURPOSE: To adjust the contrast of a binary display element as a pixel by varying weight assigned previously to the respective bits constituting (n)-bit image data. CONSTITUTION: A video signal is inputted to a terminal 1, a processing circuit 2 generates a primary-color image signal, and an A/D converter 3 stores it in a memory 4, bit by bit, as an (n)-bit PCM signal. A control circuit 12 sends various control signals synchronized with the input signal 1. Pulse generating circuits 5 and 6 and drivers 8 and 9 send vertical and horizontal pulses to apply a display panel 11 with write pulses including signals by the bits of the memory synchronized with the control signals. A generating circuit 7 sends maintaining pulses matching the weight of the write pulses by the circuit 6. At this time, a contrast adjusting circuit 14 limits the number of the maintaining pulses generated by the generating circuit 7 and further reduces the amplitude of the input signal to the A/D converter 3 through the processing circuit 2 at need. With this constitution, the contrast can be adjusted with high precision over a wide range.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention emits light when a sustaining pulse sufficient to maintain light emission is applied, and enters a non-emission state when not applied, and is capable of emitting light or non-emitting light. The present invention relates to a binary display panel image display device whose screen is a binary display panel constructed by arranging binary display elements such as a plasma display as pixels in a matrix, which selectively takes on the above state; Specifically, it is possible to display an image in gradation at a predetermined number of gradations on the screen, and then adjust the contrast, which is the ratio of the minimum luminous intensity to the maximum luminous intensity on the screen, without impairing the predetermined number of gradations. The present invention relates to such a binary display panel image display device equipped with means for enabling.

[Conventional technology]

A plasma display is a display that uses a light emitting phenomenon caused by gas discharge, similar to a neon sign. That is, flat plate electrodes are sealed at both ends of a long and thin glass tube,
An inert gas such as Ne is sealed and a voltage is applied to emit light. When the applied voltage exceeds the discharge starting voltage, a discharge occurs, and when the applied voltage is lowered below the minimum discharge sustaining voltage, the discharge stops.

Such a plasma display is an example of a binary display element, and a binary display panel is constituted by a collection of binary display elements. In other words, a binary display panel has a specific width and height of two
In response to the periodic sustaining pulse input, black and white or light and dark two
A panel that only displays values. For example, “display element/
AC type FD described on pages 161 to 165 of ``New Equipment Technology 1985 Edition'' (edited by the same editorial committee, Sogo Gijutsu Publishing)
P (plasma display panel) is a typical binary display panel, and most other DC type FDPs and ferroelectric liquid crystal display panels also belong to binary display panels.

Display pixels are arranged in a matrix on these display panels, and images are reproduced on the display panels by writing video information while addressing the rows and columns of each display pixel. Even if these display panels are binary display panels, if the length of the bright (dark) display period or the intensity of the bright (dark) display of each display pixel is controlled according to the amplitude of the image signal, multi-level display can be achieved. It is possible to display in gradation (gradation).

For example, Japanese Unexamined Patent Publication No. 57-97584 describes a method for performing multi-gradation display by controlling the number of pulses applied to display pixels according to the amplitude of an image signal. In addition, “Display element/device technology” 85 (edited by the same editorial committee)
Sogo Gijutsu Shuppan) pages 193 to 194 show how to properly combine write pulses and erase pulses according to the amplitude of the video signal,
A method for performing multi-gradation display by performing field time-division scanning and controlling the number of times each display pixel emits light is described.

In this way, generally by driving a binary display panel with pulse number modulation or pulse width/pulse height modulation,
Multi-gradation images such as television images can be displayed on a binary display panel.

[Problem that the invention seeks to solve]

In the above-mentioned conventional technology, a multi-gradation image can be displayed on a binary display panel, but no consideration has been given to providing a sufficient function as a screen of a television receiver in the sense described below.

For example, when viewing a TV screen, the TV receiver has a function that adjusts the screen's minimum brightness (black level) and the ratio of maximum brightness to minimum brightness (contrast ratio), taking into account the surrounding conditions. .

In current television receivers, the former black level adjustment is performed by changing the DC level of the video signal to be displayed.
The latter contrast adjustment is performed by changing the amplitude of the video signal. In this way, black level adjustment (bright adjustment) and contrast diurnal adjustment were conventionally performed by adjusting the DC level and amplitude of the video signal.

However, when driving a binary display panel with multi-gradation display,
When DC level adjustment and amplitude adjustment of a video signal is performed, a problem arises in that the effective number of gradations is lost due to the adjustment.

For example, consider a case where multi-gradation display is performed by pulse number modulation. In order to perform this pulse number modulation, the video signal is normally converted to PCM (Pulse-Code Motion) using an A/D converter (AnaLog-DtgitaL converter).
duLaLion) signal. This A/D
Adjusting the DC level and amplitude of the human input video signal of the converter results in the following.

Generally, it is considered that the image quality is sufficient if the reproduced image displayed on the television screen has 256 gradations (requiring 8 bits as a digital code), so the A/D converter used will be described as having an 8-bit output.

When the input dynamic range of this A/D converter is fully utilized from the minimum level to the maximum level, the 8-bit LSB (Least -S 1gn1fican
t-Bit; least significant bit) to M S B CMo
It is possible to obtain a valid PCM signal up to the most significant bit.
256 gradation display becomes possible. If we change the DC level of the video signal from this optimal state, that is, the state where the amplitude range of the video signal is set to the input dynamic range of the A/D converter, the video signal will deviate from the input dynamic range. , a problem arises in that a normal screen cannot be reproduced.

Also, even if you increase the amplitude of the video signal, the video signal will deviate from the input dynamic range, and conversely, if you narrow down the amplitude, the video signal's amplitude range will be smaller than the input dynamic range. The number of gradations will be reduced.

As a solution to the above problem, in the conventional technology, a margin corresponding to the DC level adjustment range and amplitude adjustment range of the video signal is
In order to accommodate the input dynamic range of the converter, a high bit count A/D converter such as 10 bits or 12 bits was used. However, increasing the number of bits in an A/D converter not only makes the A/D converter more expensive, but also increases the complexity of the signal processing circuit and increases power consumption. This causes another problem.

The object of the present invention is to
Adjust the contrast of the playback screen over a wide range beyond the adjustment range limited by the input dynamic range of the A/D converter without impairing the number of image gradations (for example, 256 gradations) determined by the number of bits of the M signal as much as possible. An object of the present invention is to provide a two-display panel image display device capable of displaying images.

[Means for solving problems]

In pulse number modulation, sustain pulses (
In pulse width modulation, the pulse width of the sustain pulse is controlled according to the amplitude of the video signal, and the length of the lighting period of the binary display is changed to Performs gradation display (multi-gradation display). Such pulse number modulation1. In general, to drive a binary display panel including pulse width modulation, a video signal is converted into a digital signal represented by a PCM signal, and this digital signal (hereinafter referred to as PCM signal) is converted into a digital signal represented by a PCM signal.
CM signal) and the number or width of sustain pulses.

A height modulation method is used.

Specifically, the number, width, and height of sustain pulses are weighted for each bit of the PCM signal, and the video signal data of the A/D converter output (for example, 8 bits of 0,
1; that is, the PCM signal), calculate the sum of all bits (8 bits) of the number of pulses, width, and height corresponding to each bit that becomes 1, and calculate the number or width equivalent to this sum. A height sustaining pulse is applied to the display pixels.

The purpose of effectively performing the above contrast adjustment is to
The number or width of sustain pulses assigned to each bit of this A/D converter output PCM signal.

This is achieved by providing a circuit to adjust the height.

Additionally, the number or width of sustain pulses assigned to each bit of the PCM signal as described above.

Contrast adjustment performed by changing the height is a rougher adjustment than conventional methods, but as a method for more delicate adjustment, in addition to the circuit that adjusts the sustain pulse as described above,
A circuit for varying the amplitude of the video signal input to the A/D converter or a digital circuit for performing arithmetic processing equivalent to varying the amplitude on the output data of the A/D converter is provided.

[Effect]

8 bits) When performing pulse number modulation with the PCM signal output from the A/D converter, for example, 80 pulses (ao≧
1. integer), and assign a sustain pulse for the next upper pitch)(b
85 (at≧ao+integer) sustain pulses are assigned to l), and this is repeated, and 31 sustain pulses are assigned to MBS (the most significant bit, which is defined as b7). Then, according to the state of 0.1 of each bit of the output data b0 to b of the A/D converter, the total number of sustain pulses assigned to each bit is calculated, and the number of sustain pulses equal to this total is maintained. A pulse is applied to a predetermined display pixel.

Although not directly related to contrast adjustment according to the present invention,
As the thing that determines the black level of the playback screen, there are always a pieces (a≧0 integer) regardless of the output data of the above A/D converter.
It is assumed that a sustain pulse of 1 is applied to each display pixel. At this time, the total number N of sustain pulses applied to each display pixel is N=Σ a , b 1 + a −
”(1) llO.

Assuming that the brightness of the display pixel when one sustain pulse is applied is k, the brightness l of the display pixel when the sustain pulse of the above equation (1) is applied is f=kN = Σ a 1 b , + k a
"-" (2). The minimum luminous intensity (minimum brightness) of the display pixel given by equation (2) above! ! , ffi! Wato maximum luminous intensity (maximum brightness) i,,,1. X is respectively, and the contrast ratio C, I is 1- ramx /-
If defined in emia, C1I = j2□x / j2 l, 1ta = Σa, /a
+1...(4).

In equation (4) above, if Σ ayu is changed, the maximum weight -
0 It can be seen that the contrast ratio C11 changes. A/D
Considering the linearity of brightness i with respect to the output of the converter, a is a direct = 2'm (m: integer)...
(5). At this time, the above equation (4) is the function c* of m
(m) and CR(m) = 255 ・+ 1 −−(6
). For simplicity, if a=8, then C, I(m
) = 31.8 m+ 1...-
(6A), and the contrast ratio C8 is c, (i)-3
It changes as follows: 3°C* (2)-65,... In the above equation (6), since m is an integer, the maximum contrast ratio CR(m 2 ) varies intermittently. m
The amount of change in C R (m) for a change of ±1 is C* (
m) 255m+a, and if m is 100 or more, the contrast ratio C11 can be changed by a change amount of about 1%, which seems to pose no problem in practice.

Where m is small, ΔCR is approximately several tens of percent.

If you need a finer contrast adjustment instead of an adjustment with a large amount of change like this, you can change the way a4 is given separately from 2'm, or change the amplitude of the video signal input to the A/D converter to match the change in m. You can change them in parallel. If you change the way al is given, the linearity of the change in luminance l with respect to the change in the output of the A/D converter of the display pixel will change slightly, and if you change the amplitude of the video signal, the number of effective gradations will change, but the Compared to conventional methods that only change the amplitude, the number of gradations changes less.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. This embodiment is an example in which the present invention is applied to a display circuit of a binary display panel in which pulse number modulation is typically performed by intra-field time-division scanning (hereinafter referred to as field time-division scanning).

In FIG. 1, the display circuit includes a video signal input terminal 1, a video signal processing circuit 2, an A/D converter 3, a memo U 4, a vertical scanning pulse generation circuit 5, a horizontal scanning pulse generation circuit 6, and a sustaining pulse generation circuit 7. , vertical driver 8, horizontal driver 9,
Sustaining pulse application driver 10. Bi-value display panel 11
, a control circuit 12 for controlling the operation of each circuit.
, and a contrast adjustment circuit 14. Furthermore, the pulse generation circuits 5 to 7, drivers 8 to 10, and display panel 11 are collectively defined as a display section 13.

The configuration of the display section 13 largely depends on the type of display panel 11 used. For example, if a ferroelectric liquid crystal panel is used, the vertical scanning pulse generation circuit 5, driver 8. The display panel is driven by a horizontal scanning pulse generation circuit 6 and a driver 9, and the sustain pulse generated by the sustain pulse generation circuit 7 is combined with, for example, a horizontal scanning pulse and applied to the display panel 11 via the horizontal driver 9. In this case, driver 10
becomes unnecessary. However, to drive the binary display panel 11, basically three pulses are required: a vertical scanning pulse, a horizontal scanning pulse, and a sustaining pulse.

In the block diagram shown in FIG. 1, the vertical scanning pulse.

In order to clearly distinguish between horizontal scanning pulses and sustaining pulses, pulse generation circuits 5 to 7. Drivers 8 to 10 are shown divided into three parts. The operation of the block diagram shown in FIG. 1 is as follows.

A video signal is input to input terminal 1. The video signal processing circuit 2 processes R and G based on the input video signal.

An image signal such as a B primary color signal is formed. The formed image signal is converted into a PCM signal with the required number of bits by the A/D converter 3, and is stored in the memory 4 bit by bit.

The control circuit 12 forms various control signals synchronized with the input video signal and supplies them to each circuit.

The vertical scanning pulse generation circuit 5 generates a vertical scanning pulse for the display panel 11 based on the control signal from the control circuit 12, and generates a pulse for vertical scanning of the display panel 11 via the vertical driver 8.
Scan 1. The horizontal scanning pulse generation circuit 6 takes in the image signal for each bit of the memory 4 in synchronization with the control signal from the control circuit 12, and forms write (start) pulses to the display pixels arranged in the horizontal direction. This write pulse is applied to the display panel 11 via the horizontal driver 9 in synchronization with the timing of vertical scanning. The sustain pulse generation circuit 7 generates a number of sustain pulses that match the "weight" of the write pulse generated by the horizontal scanning pulse generation circuit 6, and applies them to the display panel 11 via the driver 10.

That is, in the block diagram shown in FIG. 1, display pixels are addressed by a vertical scanning pulse generation circuit 5 and a horizontal scanning pulse generation circuit 6, and the addressed display pixels are turned on by a sustain pulse from a sustain pulse generation circuit 7. . In this embodiment of the invention, a contrast adjustment circuit 14 is provided to control the number of sustain pulses generated by the sustain pulse generation circuit 7 under normal conditions. Further, the contrast adjustment circuit 14 acts on the video signal processing circuit 2 to reduce the amplitude of the video signal input to the A/D converter 3 when fine contrast adjustment is required. Of course, there are other methods of isometrically changing the amplitude of the video signal, but FIG. 1 shows a typical example.

FIG. 2 is a schematic diagram showing the relationship between scanning lines and scanning times in a field period to explain field time-division scanning in more detail. The vertical axis shows the scanning line number, and the horizontal axis shows the scanning time. A normal television signal is scanned along the solid line L0 shown in FIG.

Because of the hour wheel, it is assumed that the A/D converter converts the image signal into an n=4-bit PCM signal. At this time, one field is scanned in time division into n+1=5 as shown in Figure 2 (if only for gradation display, L0 to
Although n=4 divisional scanning shown in L3 is sufficient, in this embodiment, scanning for determining the minimum luminance is also performed for explanation). In other words, the image signal is A/Ded with 4 bits.
Convert and represent the 4 bits from LSB to MSB as bo, bl+bz, b3, respectively, and each b O+ b +
A solid line L O+ L l +L2 . Scan along L3. Furthermore, scanning along the solid line is performed separately from the image signal data b0 to b3. As can be seen from Figure 2, on a normal television screen, one field of image is displayed in one scan, whereas in Figure 2, one field is divided into five temporally and scanned within a field. Image display is performed by time-division scanning.

FIG. 3 shows that when the display panel 11 is driven by the field time-division scanning shown in FIG. Sustain electrodes A1 to A3. Horizontal scanning electrode 3
It shows an example of the timing of pulses applied to S1 to S4.

In FIG. 3, a sufficient number of scanning electrodes are selected and shown to drive a display portion of three pixels in the vertical direction and four pixels in the horizontal direction arranged on the display panel 11.

For example, time 0.1 is set on the vertical scanning electrode. (1+115)H
, (3+215)H, (7+315)H, (15+41
5) In H, each symbol k 6+ k ++ k 2+
A pulse represented by k is applied to ff+. 2°K3 to the vertical scanning electrode has the same waveform as the pulse applied to K1, and the pulse applied to K1 to LH, respectively.

A pulse delayed by 2H (represented by ++...k to ko+ with the same symbol as the pulse applied to Kl) is applied. Here H
represents one horizontal scanning period.

The sustain electrode A1 has a pulse ko+ applied to K1,
3. Different numbers of sustain pulses a O+ a ++ a ++ a 31 a are applied at the time of . Sustain electrode A2. A3 has a pulse ko+kl+... which is applied to each 2°K3.
At time k, the waveform is the same as that of the pulse applied to A1, but the pulse applied to A1 is IH12.
H delayed pulse (symbol a similar to the pulse applied to Al
o+al+...represented by a) is applied.

The horizontal scanning electrodes S1 or 82 to S4 include the vertical scanning electrodes Kl and 2. A pulse that matches the timing of any one of the pulses ko and +...k applied to 3 is applied to .

Which pulse from 0 to 3, excluding pulse k, should be applied at the same timing can be determined by converting the image signal into an A/D
Determined by the converted data. That is, k corresponding to the LSB to MSB of the A/D conversion data. ,...
...Apply pulses with matching timing to k3. However, a pulse whose timing matches the pulse k applied to 1 to 3 is applied to all electrodes 81 to S4.

That is, as shown in FIG. 3, 0 to 3 are pulses for scanning bit by bit, and k is a pulse for scanning regardless of the data of the image signal. Each ko, ni+
, kz, and 3+ do not necessarily have to be the intervals shown in FIG.

However, if the interval is made an integral multiple of H using the scanning method shown in FIG. 2, for example, bo, tz+bz, b3 . Since the scans of b overlap, as an example, H/(1+n) −
H/0.0 for only 5 pitches. The interval between kI and 2 to 2 is shifted from an integral multiple of H.

FIG. 4 is a schematic diagram schematically showing an arrangement of display pixels driven by the pulses shown in FIG. 3. K1-3 is a vertical scanning electrode, 81 to S4 are horizontal scanning electrodes, and A1 to A3 are sustaining electrodes. Display pixels are scan electrodes K in the vertical (row) direction.
It is specified by the number i of i and the number j of the scanning electrode Sj in the horizontal (column) direction, and is expressed by d ij. For example, display pixel dZ3 has scanning electrodes 2 and 33 selected.

Looking at the timing of the pulses applied to the electrodes Ki and Sj shown in Figure 3, the pulse applied to Sl is 1, 2, 2, 0 and 2. The timing matches the pulses applied to 1 and 3 at 0 and 1. At this time, kO+k I+ k z, k !
+ k pulses, respectively ao=L a+
=2+ az=4. a3=8. Assume that a=8 sustain pulses are applied. As a result, from the timing of the pulses applied to K1 and 51, the display pixel dll has a total of a
Light emission is performed using o + az + a 3 + a = 21 sustain pulses. If a brightness of 1 can be obtained for one sustain pulse, the display pixel d1
1's brightness 42+1 becomes f++=21.

In general, the brightness 2 of a certain display pixel can be expressed as follows by setting 1 in the above equation (2). However, b+ (t=0 to n-1)
is the data of each bit when the video signal is A/D converted into an n-bit PCM signal, bo is the LSB, b is the next high-order bit, and bfl-1 is the MSB value. be. ai is the number of sustain pulses given to each bit b1. a is the number of sustain pulses that are always applied to the display pixels.

In this embodiment, for the sake of simplicity, n=4 is used for explanation.

FIG. 5 shows the relationship between the A/D conversion output data (bo=bi) of the video signal and the luminance 2 when the number of sustain pulses applied to the display pixel dll is changed, for example.

That is, in FIG. 5(a), vertical scanning pulses 0 to 1 and corresponding sustain pulses a0 to a are set A, A',
A'', and FIG. 5(b) shows the output b0 of the A/D converter in each sustain pulse set A, A', A'.
It shows how the relationship between ~b3 and brightness °C changes. In the graph, since the output of the A/D converter is n=4 bits, the change in luminance E is 2'=16 gradations.

In FIG. 5(a), a set of sustain pulses (ao+
a++az+ai; a), A is (1,2°4.
8i8), A' is (2,4,8,16;8).

A" is (3, 6, 12, 24; 8).

At this time, the relationship between the outputs b0 to b of the A/D converter and the luminance l is shown by the solid line A shown in FIG. 5(b).

A', A''. That is, (1) the sustain pulse set (ao+al+a2+a3; a) is (1,2
, 4, 8; 8), the brightness 2 varies from the minimum brightness f, , , = 8 to the maximum brightness [m,
, = 15, with the number of gradations N=16. The contrast ratio C++ at this time is C11=1 from the above formula (4).
．． It is 875.

(2) Change the set of sustain pulses from (1, 2, 4, 8; 8) → (2
, 4, 8, 16; 8), the luminance l becomes as shown in Fig. 5 (b
), the brightness changes from the minimum brightness f, . . . = 8 to the maximum brightness f', . The contrast ratio at this time is C,=4.75.

(3) Change the set of sustain pulses from (1, 2, 4, 8; 8) → (3
, 6, 12, 24; 8), the luminance 2 becomes as shown in Fig. 5 (
As shown by the solid line A'' shown in b), the brightness changes from the minimum brightness f-t-=8 to the maximum brightness 2#, 1.8=53 with the number of gradations N=16.The contrast ratio at this time is Cm=6 .62
It is 5.

In this way, when the number a1 of sustain pulses is changed, the number of gradations N
The contrast ratio can be changed while keeping the contrast constant. An example of the above A, A', A'' is a.

= 21 m, and m is changed to 1 and 2.3, respectively. It can be seen from FIG. 5(b) that when a 1=2'm is set in this way, the change in luminance l has the most reasonable linearity. It is also possible to give ai in another way, but this will be explained in detail later.

FIG. 6 shows a specific example of a circuit configuration corresponding to the sustain pulse generating circuit 7 shown in FIG. 1, for performing the contrast adjustment shown in FIG. 5.

FIG. 6 shows the ROM (Read -0nly -Mer
nory) 62, address counter 61 for ROM62,
Counter 67, monostable multi-bi break 68, counters 69, 72, decoder 70, comparator 71, D-
FF (D type-Flip FLop) 73.0R7
4, 75, AND circuit 76, IH delay circuits 78a to 78
11 address counter 61 clock input terminal 60, R
Output terminal 63 of OM 62, preset terminal 64 of counter 69, oscillation cycle adjustment terminal 65 of monostable multi-bi break 68, input terminal 66 of basic sustain pulse, output terminal 82 of control sustain pulse, sustain pulse output terminals 79a to 79
j and a switching signal detection terminal 100 for performing fine contrast adjustment.

Here, the portion indicated by a dotted line frame 81 in FIG. 6 is a sustain pulse control circuit, and the dotted line frames 80 and 81 together correspond to the sustain pulse generation circuit 7 shown in FIG. Address counter 61 and ROM 62 constitute a part of control circuit 12 shown in FIG.

However, this FIG. 6 shows an example of the circuit configuration, and other specific circuit configurations for performing the adjustment as shown in FIG. 5 can be considered.

FIG. 7 shows a timing chart for explaining the operation of the circuit shown in FIG. 6. The address counter 61 synchronizes with the clock input from the control circuit 12 to the input terminal 60 at a constant cycle (in this embodiment, 115H cycle).
Count the addresses of.

According to the address of the address counter 61, the ROM 62 outputs the pulse K shown in FIG. 6, which corresponds to the pulse 1 applied to the vertical scanning electrodes shown in FIG. In FIG. 6, the pulse has time to=0.

t,=(1+115)H, t2=(3+215)H.

Five pulses rise at t, = (7 + 315) H, t, = (15 + 415) H, and to' = after 115 H, respectively.
115H,tl'=(1+215)H,t,,'=(3
+315)H, t3'=(7+415)H,j4'==
It falls at 16H.

This pulse is divided into two signals, one at terminal 63.
The signal is outputted from the signal generator and becomes an input signal to the vertical scanning pulse generation circuit 5 and the horizontal scanning pulse generation circuit 6.

The other is an n+1 counter 67, m as shown in FIG.
Bit counter 69. D-FF73 (7) clock and! This serves as a reset signal for the bit counter 72. Here, n is the number of bits of the PCM signal obtained by A/D conversion of the video signal, and 2m is the number of bits large enough to represent the number of pulses in one field in binary. In this embodiment, the explanation is given with n=4.

In FIG. 6, the n+1 counter 67 is reset by, for example, a vertical synchronizing signal or the like before time t0 when field scanning is started, and counts the number of pulses after time t0. In FIG. 7, when pulse K is counted 5 times, pulse A synchronized with the falling edge of pulse K at time t, l.
Output. Furthermore, although not shown in FIG. 7, it is assumed that the counter 67 is reset by, for example, a vertical synchronizing signal immediately before the start of the next field scan, and at the same time, the pulse A falls.

The monostable multivibrator 68 outputs a pulse B that is synchronized with the falling edge of the pulse. Pulse B is determined by the oscillation time constant adjustment terminal 65 of the monostable multivibrator (this terminal 65 is connected to the contrast adjustment circuit 14, but is used for brightness adjustment, not contrast adjustment). It falls.

The counter 69 counts up in binary using the pulse K as a clock, and outputs m-bit signals QI' to Q, /. However, the counter 69 is reset by, for example, a vertical synchronizing signal or the like before field scanning start time t0, and the initial values of Qa' to Q, / at the start of counting are determined by the adjustment terminal 64 (this terminal 64 is connected to the contrast adjustment circuit 14). (used for contrast adjustment) can be preset according to the data applied to it.

The decoder 70 outputs binary outputs Q, -Qu based on the outputs Q1' -Q, 1 of the counter 69. Figure 7 shows Q,
~Q, waveforms are shown.

Counter 72! It is a bit binary counter and counts the basic sustain pulse T input from the control circuit 12 to the terminal 66. However, it is assumed that the counter 72 is reset by the output pulse of the ROM 62 and starts counting at the falling edge of the output pulse.

Comparator 71 compares the outputs of decoder 70 and counter 72, and outputs one pulse at the time when both coincide. For example, t=t for the pulse.

The output of the counter 69 for the first rising pulse is Q
,'=1. Q,'==Q,'=・・・・・・=Q,'=
If O, then the output of the decoder 70 will also be Q,=1. QZ=Q3
=...=Qu=O. Therefore, when the counter 72 counts one sustain pulse T, the comparator 71 outputs a pulse. Similarly, the pulse has 2
The counter 72 counts two sustain pulses for each of the 3rd, 3rd, and 4th inputs.

When the count reaches 4 and 8, the comparator 71 outputs a pulse.

The output pulse of this comparator 71 and the output pulse of the n+1 counter 67 are input to 0R74, and their sum is D
- Use as a reset pulse for FF73. D-FF73 rises in synchronization with the falling edge of the pulse t0' to t4L, and becomes 0R.
It is assumed that a pulse C that falls in synchronization with the rise of the output of 74 is output. The output of 0R74 is n+1 counter 67
is the sum of the output A of and the output of the comparator 71,
Since the D-FF 73 is first set by the output of the comparator 71, the pulse C rises at time jO'+I'1 t@', t3', and the sustain pulses are respectively set as 1.2.4. It falls at the time of 8 counts. Although the pulse C rises at time t4', the D-FF 73 is reset at time t, I by the output A of the counter 67 at the same time as the rise, so that virtually no pulse is generated.

The output C of this D-FF 73 and the output B of the monostable multipipe rake 68 are added together using 0R75 to form a pulse D, and the pulse D shown here is applied to one input terminal of the AND76.

AND76 gates a specific number of basic sustain pulses T using pulse D as a strobe signal, and generates sustain pulse S.
Output. As can be seen from the above description, the pulse S has falling times t o' and t +'.

j! Number of sustain pulses ao=1+3.Synchronized with '+j3'. =2. az=4. Output only ai=8. For a pulse that falls at time t4', the number a of pulses S is determined at time t4' at which pulse B falls, which is determined by the time constant of the monostable multivibrator 68. In FIG. 7, a=8.

From the explanation of FIGS. 6 and 7, if the count start data of the counter 69 is adjusted according to the preset data applied to the terminal 64, the number of sustain pulses S is a++az+a**
A4 can be adjusted. Therefore, the terminal 64 has the role of a sustain pulse control terminal.

FIG. 8 shows an example of a timing chart of the circuit shown in FIG. 6 when the count start data of the counter 69 is adjusted by the preset data applied to the terminal 64. That is, by presetting, the starting data of the counter 69 is set to Q,'=1. Qz'=Q3'=...Q,'=0
Then, the output of the counter 69 for the pulse that first rises at t=t0 is Q+=O, Q2'
= 1, Q3' = Q4' =...=Q
,,,'=O, and at this time the output of the decoder 70 is Q
1=O, Qz=1. Qs=Q4=...=QQ=
It becomes 0. Therefore, the counter 72 increases the sustain pulse T by 2.
When counted, the comparator 71 outputs a pulse. Similarly, the time L = t when the second pulse rises
+, the output of the counter 69 is (L' = Qz'
= L, Qx' = Q4' =・・・・・・=
Q, = O, and the output of the decoder 70 is Q l = Q z
= O, Q! =1, Q==Qs""...=
Q,=O.

Therefore, when the counter 72 counts 22=4 sustaining pulses T, the comparator 71 outputs a pulse. For the third and fourth inputs to the pulse below, the counter 72
When the sustain pulses count 8 and 16, respectively, the comparator 71 outputs a pulse.

The output pulse of this comparator 71 and the output pulse of the n+1 counter 67 are input to 0R74, and their sum is D-
A pulse C is formed as a reset pulse for the FF 73.

Pulse C and pulse B are added by 0R75 to form pulse D, which is used as a strobe input to AND76. Here, the pulse C shown in FIG. 8 has a pulse width twice that of the pulse C shown in FIG. 7, and the pulse B is the same in FIGS.

Therefore, the pulse S shown in FIG. 8 is ao+al+a! compared to the pulse S shown in FIG. The number of +a3 is doubled and the number of a is unchanged.

The timing chart shown in FIG. 7 corresponds to the case of forming the sustain pulse train A shown in FIG. 5, and the timing chart of FIG. 8 corresponds to the case of forming the sustain pulse train A'.

In relation to the above equation (5), FIG. 7 corresponds to the case where m=1, and FIG. 8 corresponds to the case where m=2. It is clear from the above description that even a case where m is even larger can be easily realized by simply changing the preset data applied to the terminal 64.

The sustain pulse S obtained in this way is delayed by IH by the delay circuit 78 shown in the dotted line frame 80 in FIG. A3). This sustaining pulse S is applied to each display pixel, but whether each display pixel lights up or not depends on the display panel 1 as explained in FIG.
This depends on the timing of the scanning pulses applied to the vertical scanning electrodes 1 and horizontal scanning electrodes (1 to 3 and 3l-34 in FIG. 4, respectively). At this time, even if the same scanning pulse is applied, when the sustain pulse S shown in FIG. 8 is applied, the luminance of the display pixel is higher than that shown in FIG. 7, and the contrast ratio is also higher. The effect on this adjustment is as explained in FIG.

FIG. 9 shows the relationship between the brightness 2 of the display pixel and the video signal input to the A/D converter. For simplicity, the stepwise change in luminance l as shown in FIG. 5 has been omitted.

The dynamic range of the A/D converter is O-v, , 1
・In the input 1 setting, the upper limit (white peak) V□8 and lower limit (black level) VIIin of the video signal are set to A.
It is normal to use it by matching the dynamic range of the /D converter.

Under this setting condition of human power 1, as shown in Figs. 7 and 8, a! If a sustain pulse set such as =2' or a8-2.2. is formed and applied to the display panel 11,
The maximum brightness signal from the minimum brightness signal I Mi shown by the solid line A, respectively! , , brightness characteristics that vary up to 8 or solid line A
'The minimum brightness is 1 mi, and the maximum brightness is 1 'IIm.
A brightness characteristic that varies up to X can be obtained. Here, the solid line A# corresponds to the sustain pulse set a,=3·2i.

As explained in FIG. 5, the sustain pulse set is a.

= 2im, the brightness characteristic becomes a straight line, but when m is changed, the maximum contrast changes intermittently. In FIG. 9, when m=1 is changed to 2, the brightness characteristic changes from solid line A to solid line A', and the contrast ratio also changes to CR==Affi.
1X/i! , ff1i, , C11' = f'
Changes to m@M/J2'raLn. At this rate, CR
There is no contrast ratio between and CR', but in the brightness characteristic of the solid line A', by narrowing down the amplitude of the video signal input to the A/D converter, the white peak v'@ax of the A/I) converter By setting the input so that the dynamic range upper limit vdy is smaller, an intermediate contrast ratio can be obtained.

In other words, if V'□,<Vdyn is set as in the setting of input 2, the video signal changes only between V,%,7 and v',X, so the brightness is A+ on the solid line A'. *i+
The brightness at point C changes within the range ffi″l*lIX from s to point C (l″lI□<f′5−x). The contrast ratio at this time is C* ” = 12 '□X/!'.
<C, I'. Of course, the number of gradations is reduced by narrowing down the input amplitude of the A/D converter, but the present invention has a wider range of contrast adjustment than the conventional method and is less likely to lose the number of gradations.

This is because in the conventional technology, for example, the brightness characteristic is fixed to the solid line A', and the contrast is adjusted only by the input signal amplitude, and the adjustment range is 1 to 1+' mmx/
It was limited to l + mi. Also, 08'=1'
In order to obtain a contrast ratio that is half of maw / f @i yl, conventionally the input signal amplitude of the A/D converter must be halved and the number of gradations must be halved accordingly, but in the present invention, the luminance By setting the characteristics as shown by the solid line A, a contrast ratio that is half the contrast ratio obtained by the solid line A' can be achieved, and the number of gradations does not change.

In FIG. 9, it has been described that contrast adjustment is performed by adjusting the number of sustain pulses ai and adjusting the input signal amplitude of the A/D converter. Examples of contrast adjustment circuits in this method are shown in FIGS. 10-12.

Figure 10 shows the video signal input terminal 1 and the video signal processing circuit 2.
, A/D converter 3, A/D converter output terminal 102, sustain pulse control circuit 81, switching signal detection terminal 100, switching control circuit 101, amplitude control circuit 104, amplitude adjustment terminal 10
3, a sustain pulse adjustment terminal 64, and a control sustain pulse output terminal 82.

Among these, the video signal input terminal I, the video signal processing circuit 2, and the A/D converter 3 have the same configuration as shown in FIG.

The sustain pulse control circuit 81 in FIG. 10 is the same as the sustain pulse control circuit 81 shown in the dotted line frame in FIG. 6, but detailed input/output terminals are omitted in FIG. A dotted line frame 201 composed of the sustain pulse control circuit 81, the switching control circuit 101, and the amplitude control circuit 104 is the contrast adjustment circuit 201, which corresponds to the contrast adjustment circuit 14 shown in FIG.

Normally, contrast adjustment is performed by controlling the number of sustain pulses in the sustain pulse control circuit 81.

This control is performed using the adjustment terminal 64. When performing adjustment to obtain an intermediate value of the contrast ratio that can be controlled by the number of sustain pulses, the state of the sustain pulses is detected by the switching detection terminal 100, and the switching control circuit 101 is operated. The amplitude control circuit 104 operates according to the command from the switching control circuit 101,
The amplitude of the output video signal of the video signal processing circuit 2 is changed in conjunction with the amplitude adjustment terminal 103. Note that the terminal 64 and the terminal 10
If the control in step 3 is voltage control, it can be configured to allow continuous adjustment with one adjustable variable resistor, for example by using an appropriate electronic circuit such as a 4-terminal variable resistor with a center tap and a diode clip circuit. .

FIG. 11 shows the video signal input terminal 1 and the video signal processing circuit 2.
, A/D converter 3, A/D converter output terminal 102, sustain pulse control circuit 81, switching signal detection terminal 100. Switching control circuit 101, reference voltage control circuit 103, reference voltage adjustment terminal 105, sustain pulse adjustment terminal 6
4. Consisting of a control sustaining pulse output terminal 82.

The configuration of Figure 11 is almost the same as Figure 10, but
The difference is that the amplitude control circuit 104 constituting the contrast adjustment circuit 201 in the figure is replaced with a reference voltage control circuit 103 in FIG.

Normally, the sustain pulse control circuit 81 controls the number of sustain pulses to adjust the contrast, but when changing the input amplitude, the switching control circuit 101 operates the reference voltage control circuit 103 to adjust the contrast. A/D
The input reference voltage of the converter 3 and the input video signal voltage are in a relative relationship, and by changing the input reference voltage, the amplitude of the input video signal can be relatively changed. Therefore, FIG. 11 provides the same effect as FIG. 10.

FIG. 12 shows a video signal input terminal 1, a video signal processing circuit 2,
A/D converter 3, A/D converter output terminal 102, sustain pulse control circuit 81, switching signal detection terminal 100, switching control circuit 101, calculation circuit 106, calculation adjustment terminal 103,
Sustain pulse adjustment terminal 64, control sustain pulse output terminal 82
, further, the arithmetic circuit 106 includes a coefficient setting circuit 301 that determines a coefficient by which the output of the A/D converter 3 is multiplied, a multiplication circuit 302,
It is composed of a circuit 303 for converting multiplication output into an integer.

The configuration in FIG. 12 differs from the configurations in FIGS. 10 and 11 in that the arithmetic circuit 106 is used to change the output data of the A/D converter 3. Another video signal processing circuit 2,
Regarding the configurations of the A/D converter 3, switching control circuit 101, sustaining pulse control circuit 81, etc., FIG. 12 is similar to FIG.
Same as Figure 1.

Normally, the sustain pulse control circuit 81 controls the number of sustain pulses to adjust the brightness, but when obtaining an intermediate contrast, the switching control circuit 101 operates the arithmetic circuit 106 to adjust the contrast. Multiplying (or dividing) the output data of the A/D converter 3 is equivalent to changing the amplitude of the input video signal to the A/D converter. Therefore, it can be seen that FIG. 12 provides the same effect as FIGS. 10 and 11.

Here, the arithmetic circuit 106 shown in FIG. 12 is configured so that input and output are integers. For example, if the output of the A/D converter is represented by 4 bits (boblbZb,), and the amplitude is reduced, the output of the coefficient setting circuit 301 is a decimal number less than or equal to 1, and the decimal part is represented by 4 bits (be'b+'bz).
'bi'). Multiplying these two numbers is, for example, a 4-bit x 4-bit multiplication IC5N74L3285 (
This can be easily done using the TI Corporation, and the output is usually 8 bits. This multiplication output can easily be converted into an integer by taking the upper 4 bits and rounding down the lower 4 bits.

The above is a case where the number of sustain pulses is controlled under the condition that a6=2'm as a sustain pulse train. Although the linearity of the luminance characteristic changes slightly, the number a of sustaining pulses assigned to each bit of the AD-converted video signal is not limited to 2'm (contrast adjustment is also possible using other sets of pulse numbers).

There is no necessity to set any special rules in the way of giving a, but
When displaying gradation using the output of the A/D converter as it is, it is necessary to satisfy at least the following. For example, the output of a 4-pitch A/D converter for a video signal with amplitudes represented by 3 and 4 is:
(1100) and (00) in the order of (bob+bzb:+)
10). At this time, the sum of sustain pulses ai assigned to each bit is a 6 + a for a signal with an amplitude of 3
r ten a t, and for a signal with amplitude 4, it is a3. It is abnormal for gradation display that it is darker when a signal with amplitude 4 is input than when a signal with amplitude 3 is input, so a, ≧a 6
+ a 1 + a 2 and the above equation (9) is established.

FIG. 13 shows the characteristics of the luminance value when the way of giving the sustain pulse a is changed in a manner different from 2'm according to the above equation (9). That is, in FIG. 13(a), a set of vertical scanning pulses 0 to 1 and a corresponding sustain pulse (ao+a+
+at+as; Indicates the case where a) is changed. A is (1,
2, 4, 8i8), A' is (1, 2, 4, 9i8), A
“is (1,2,5°10;8), A” is (1,3,6,
12;8). And Figure 13(b)
is the brightness 2 for each sustain pulse set A-A''.
It shows the characteristics of

In sustain pulse set A, each bit b0 to b of the output data
The assignment of sustain pulses to 3 is according to a=21, which is the same as in FIG.

The brightness l is as shown by the thick solid line A in Fig. 13(b).
1 from ff1in! , □1 while maintaining linearity up to 8.
Changes in 6 gradations.

In the sustain pulse set A', only the assignment a3 to the MSB bit of the output data is 23→2'3+2
Change it to 0. At this time, the luminance l is as shown by the thick dotted line A' in FIG. 13(b)! 1. From n to j! 'mmx up to 1
Changes in 6 gradations. Although a difference in brightness occurs where the MSB bit of the output data changes, the brightness characteristic is approximately linear.

For sustain pulse set A'', b is the MSB of the output data.
Assignment a3+8 to the 3rd bit and the next lower bit bz
2 as ai=2'+2'+2', a2=2z→22+
Change to 2°. At this time, the luminance deficiency is 1 from 42 w, in to l#, □, as shown by the solid line A# in Fig. 13(b).
Changes in 6 gradations. Although a difference in brightness occurs where bx and bt of the output data change, the brightness characteristic is approximately linear.

In sustain pulse set A#, b is the MSB of the output data.
Assignment a 3+ a 2 . to the 3 bits and the next lower bits b , , b . a 3 = 23 → 2
3+2”.

az=2"42"+2',a+=2-+2'+2°
Change it to At this time, the brightness l is the solid line A in FIG. 13(b).
As shown in ``, the brightness changes in 16 gradations from j211.in to 2#□8.Although there are steps in brightness where the bi, bz, and bt of the output data change, the brightness characteristics are approximately linear.

The set A", which has a higher contrast than the sustain pulse set A", is a3=23-+23+23=2.2'.

at””2”→2”+2”=2・22.
..., ao"'1→1+2°, which is the same as the solid line A' shown in FIG. 5. In FIG. Dotted line A with
However, since it is not related to Figure 13 (a),
The symbol “#” is shown enclosed in parentheses.

As can be seen from Fig. 13(b), when adjusting the brightness by changing m when al = 2''m, the thick solid line A (m = 1
) to the dotted line A'' (m=2) marked with an Although there are steps in brightness changes, finer contrast adjustment is possible without compromising the number of gradations.

The way to give the sustain pulse ai shown in FIG. 13 is generally given by considering an n-bit PCM signal, and fine adjustment of the contrast can be made in n-1 steps while keeping m fixed by j in the second term of the above equation 00. becomes.

It is obvious that when j=m, the adjustment is the same as that shown in FIG.

There are other ways to allocate the number of sustain pulses ai other than the above. There are countless circuits that can implement any allocation method. An example is shown below.

FIG. 14 is a block diagram showing an example of a circuit for allocating an arbitrary number of sustain pulses a. FIG. 14 shows the address counter 61, ROM 62, CPU 300, AND76,
IH delay circuits 78a to 781, clock input terminal 60 of counter 61, output terminal 63 of ROM 62, CPU 3
00 control terminal 64, basic sustain pulse input terminal 66,
and sustain pulse output terminals 79a to 79j.

The operation in FIG. 14 is almost the same as in FIG. 6, but the terminal 66
The pulse D for gating the basic sustain pulse T input to the CPU (CentraL-P
The difference is that it is formed in a processing unit (central processing unit). In other words, the counter 61 counts addresses according to the clock input to the terminal 60,
Pulse K is output from ROM 62 according to the count value. In synchronization with this pulse, terminal 64
The CPU 300 generates a pulse D with a pulse width that meets the adjustment conditions of
Output from. and 38 depending on the pulse width of pulse D
The basic sustain pulses T are gated by an AND 76, and a desired number of sets of sustain pulses are output from output terminals 79a to 79j. The effect of contrast adjustment by controlling the number of sustain pulses is exactly the same as described above.

In the above example, the number of sustain pulses applied to the sustain pulse applying electrodes is changed. If the number of sustain pulses is kept constant and the number of bits in the A/D converter 3 is limited, the amplitude of the input signal to the A/D converter cannot exceed the input dynamic range. /D converter 3 is limited by the number of bits. However, A
By performing calculations on the output of the /D converter 3, the A/D
The contrast can be adjusted beyond the maximum contrast determined by the converter 3, and fine adjustment is easy.

FIG. 15 shows changes in brightness characteristics in an embodiment in which the output of the A/D converter 3 is multiplied. For simplicity, the A/D converter 3 has 4-bit output b0 to b, and the input signal is A.
The amplitude is optimally matched to the dynamic range of the /D converter 3.

The value by which the output of the A/D converter 3 is multiplied is 2, that is, the maximum variable range of the contrast ratio is 2 times.

Even in a normal CTV, there is a contrast adjustment range of ±6 dB with respect to the optimum design value, and this embodiment will be explained with the same variable range given. At this time, the image data obtained by performing the calculation on the output of the A/D converter 3 is divided into b0 to b by adding 1 bit b'.
, b' are sufficient.

The number of bits of the image data after this calculation is 5, and 1 bit b for determining the minimum brightness, total b0~b3°b', b
The display panel 11 displays gradations using 6 bits. The number of time divisions for field time division scanning is set to 6 according to this number of bits.
The pulses corresponding to b0 to b'b applied to the vertical scanning electrodes of the panel 11 during each scan are shown in FIG. 15(a) as 0 to 2', respectively. Each bit b0 to b3
．． For simplicity, the number of sustain pulses al assigned to b' and b is, for example, ao for bo = Lb+ at = 2. bz has a z =4 r b3 has a, =8. b
For ', a' = 16°; for b, a = 8. Of course ai
This is not the only way to give it.

When the output of A/D converter 3 is multiplied by coefficient 1, the first
As shown by the solid line A in Figure 5 (b), the minimum brightness! , i7 to the maximum luminance f , , ax. This characteristic is represented by the solid line A and the 13th line shown in Figure 5(b).
This is the same as the solid line A shown in Figure (b).

As an example of the calculation, the output data after the calculation is shown in FIG. 15(C) when the output data of the A/D converter 3 is multiplied by a coefficient of 1.5 and converted into an integer (rounding down to the nearest whole number). The brightness characteristic for this data is the minimum brightness f! as shown by the dotted line A' in FIG. 15(b). , 1, to the maximum brightness f'max in 16 gradations. This characteristic is the first
This is the same as the solid line A# shown in FIG. 3(b).

When the coefficient is set to 1 or less, the number of gradations of the luminance characteristic for the output data after this calculation decreases. For example, in the case of a coefficient of 0.5, the brightness characteristic is shown by the dotted line A'' in FIG. 15(b).

If the brightness and contrast are low, no deterioration in image quality will be observed even if the number of gradations is small. Therefore, in general, in the direction of narrowing down the contrast, a reduction in the number of gradations does not seem to be a big problem.

Any method can be used to prevent the number of gradations from changing even if the contrast is reduced from the optimum level by combining the control of the number of sustain pulses to be allocated and an arithmetic circuit.

By arbitrarily changing the multiplication coefficient, the slope of the luminance characteristic can be finely changed, and therefore the maximum contrast ratio can be finely adjusted. The circuit that implements this multiplication has exactly the same configuration as the arithmetic circuit 106 shown in FIG.

Furthermore, if the necessary coefficients are set by the coefficient setting circuit 301 using the adjustment terminal 103, there is no necessity for the sustain pulse control circuit 81 to control the number of sustain pulses assigned to each bit. In other words, it is sufficient to adjust the allocation of sustain pulses to each bit during circuit design.
From the outside of the TV, it is possible to make adjustments of ±6 dB to the optimum design using only the terminal 103, for example.

In the embodiment shown in FIG. 15, the output of the A/D converter is 4 bits, and the image data after calculation is 5 bits, but it is also possible to further increase the image data to 6 bits or 7 bits. The effects of the present invention are clear in this case as well.
An even wider adjustment range is possible.

Also, the number ai of sustain pulses for each bit is the 15th
It does not have to be the value shown in Figure (a). It is sufficient to provide an arithmetic circuit 106 that performs appropriate calculations for appropriate combinations of ai. For example, the number of sustain pulses a' shown in FIG. 15(a) may be set to 10. In this case, the output data of the A/D converter 3 is subjected to calculations so that the luminance characteristics become approximately linear. b.

~bzb' data is set.

Further, in the embodiment shown in FIG. 15, the amplitude of the video signal input to the A/D converter 3 is set to match the input dynamic range of the A/D converter. If the settings deviate, if the coefficients set by the coefficient setting circuit 301 are corrected according to the amount of deviation, even if the DC level of the input signal at the A/D converter 3 changes, the panel The slope of the brightness characteristics does not change. As a method for correcting this coefficient, for example, in FIG. 12, the amount of deviation from the black level of the video signal at the time of optimal design is applied to the terminal 103 as a reference.

In the embodiments described above, the vertical scanning pulse generating circuit 5 and the horizontal scanning pulse generating circuit 6 address the display pixels of the display panel 11, and apply the required number of sustain pulses necessary for light emission. In the above embodiment, the contrast is adjusted by adjusting the number of sustain pulses, but the same effect can be obtained by adjusting the number of times of light emission by the sustain pulse by using other pulses without changing the number of sustain pulses. This example will be shown below.

As a typical example, FIG. 16 shows a block diagram of a display circuit of a binary display panel in the case of pulse number modulation using field time division scanning.

The display circuit includes a video signal input terminal 1, a video signal processing circuit 2, an A/D converter 3, a memory 4, a vertical scanning pulse generation circuit 5', a horizontal scanning pulse generation circuit 6, and a sustaining pulse generation circuit 7, as shown in FIG. ', vertical driver 8, horizontal driver 9, driver 10' for applying sustain pulses, binary display panel 1
1, a control circuit 12 and a contrast adjustment circuit 14', and a display section 13' has the same definition as in FIG.

However, the contrast adjustment circuit 14' is connected to the vertical scanning pulse generation circuit 5', and accordingly, the vertical scanning pulse generation circuit 5', the sustain pulse generation circuit 7', and the contrast adjustment circuit 14' are connected to the vertical scanning pulse generation circuit 5', as shown in FIG. It is different from each circuit shown in .

In the display panel 11 shown in FIG. 16, display pixels are addressed by a vertical scanning pulse generation circuit 5' and a horizontal scanning pulse generation circuit 6, and emit light by a sustain pulse from a sustain pulse generation circuit 7'. Then, the light emission caused by the sustain pulse is stopped by applying a light emission stop pulse (erase pulse) to the vertical scanning electrode. For example, as such a display panel, there is an FDP in which a vertical scanning electrode is used as a discharge cathode, and in such an FDP, the start and stop of light emission can be controlled by controlling the cathode voltage.

FIG. 17 shows vertical scanning electrodes 1 to 3, sustain electrodes A1 to A3, and horizontal scanning ILMS 1 to which voltage is applied to the display panel 11.
-34 shows the timing of the pulse applied. Similar to the timing chart shown in FIG. 3, FIG. 16 shows a sufficient number of scanning electrodes selected to display a display area of 3 pixels vertically and 4 pixels horizontally arranged on the display panel 11. .

For example, time 0.1 is set on the vertical scanning electrode. (1+115))
i, (3+215)H, (7+315)H.

(15+415)H respectively k O+ k I
+ k 2+, , pulses and each , , , , 2+
: Time T0. from the falling edge of the pulse to l+, respectively. T
,,T2. T3. Pulse Co, CI+C rising after T
Apply Z, C3+C.

2 on the vertical scanning electrode. 3, C0 to C are applied to pulses 0 to 3, which have the same waveform as the pulse applied to K1, but are delayed by IH and 2H from K1, respectively. Sustain electrode A1
A continuous sustain pulse is applied to ~A3. The horizontal scanning electrodes 31 to s4 have pulses applied to the vertical scanning electrodes 1 to 3 according to the A/D conversion data of the image signal.
Apply a pulse whose timing matches one of the two. However, all pulses whose timing matches the pulse k applied to K1-3 are applied to 31 to S4.

In FIG. 17, each display element applies voltage to sustain electrodes A1 to A3 at times that match the pulses applied to vertical scan electrodes 1 to 3 and the pulses applied to horizontal scan electrodes 31 to S4. The sustain pulse starts emitting light. Then, pulses 0 to 3 are applied to the vertical scanning electrodes.
Each light emission is stopped by 0 to C. 1 to vertical scanning electrode
The time difference T between the pulses applied to 3 and the pulses 00 to C. -T determines the time from the start of light emission to the stop of light emission, that is, the number of times of light emission by the sustain pulse. Therefore, in FIG. 17, the sustain pulse is applied to each electrode A1.
It is only necessary to apply continuously 3 to 3.

In the embodiments shown in FIGS. 16 and 17, the contrast of the display panel 11 is adjusted by adjusting the time difference T (1xTs -t-) between 0~ and 00~C3 to the pulses applied to the vertical scanning electrodes. Adjustment is possible.This time difference T0 to T is equal to the pulse width of the pulse D that rises from t0 to t3 in the timing chart shown in FIG. 7.Therefore, the circuit that forms the pulse D shown in FIG. (A part of the circuit shown in FIG. 6 or FIG. 14) can be used to easily realize this embodiment.

The present invention has been described above in detail using pulse number modulation.

Furthermore, the effect of the present invention is pulse width modulation.

The same applies to pulse height modulation. For example, the contrast can be adjusted by A/D converting the image signal and changing the pulse width of the sustain pulse assigned to each bit of the PCM signal.

A similar explanation holds true for pulse height modulation.

In the embodiment of the present invention, panel scanning is performed by field time division, but the present invention is not limited to field time division scanning. Depending on the scanning method, the above (1) can be achieved in one scan.
It is also possible to display on the screen by applying sustain pulses of the number, width, and height expressed by a formula similar to the formula to the display pixels. Even in this case, it is the same as the embodiment of the present invention to provide a circuit for adjusting the number of sustain pulses or the assignment of width and height to each bit of the A/D converted image signal, and the present invention described above gives the same effect as the embodiment.

Depending on the structure of the panel and the scanning method, it may appear that images are displayed using only vertical scanning pulses and horizontal scanning pulses, and the sustain pulses and their application circuits may not be clear. For example, this is the case when driving by superimposing a sustain pulse on a horizontal scanning pulse or a vertical scanning pulse. However, in this case as well, there are address pulses and sustain pulses that contribute to light emission, and providing a circuit to adjust the number, width, and height of these sustain pulses is the same as in the embodiment of the present invention, and is the same as above. give effect.

Note that the display panels used in the examples of the present invention are monochrome,
Any color is fine. Even if the display panel is a color panel, according to the present invention, the contrast can be adjusted without changing the white balance.

〔Effect of the invention〕

According to the present invention, by adjusting the number of sustain pulses assigned to each bit of a digital signal obtained by A/D converting an image signal, it is possible to change the brightness characteristics of display pixels with respect to an input video signal. Therefore, it is possible to adjust the contrast of the display panel without impairing the number of image gradations determined by the number of bits of the digital signal, and if necessary, it is also possible to finely adjust the contrast by adjusting the number of sustain pulses mentioned above. This has the effect of enabling contrast adjustment over a wider range and with higher performance than conventional contrast adjustment.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is an explanatory diagram of the relationship between scanning lines and scanning time to explain field time division scanning, and FIG. 3 is a diagram showing the scanning method shown in FIG. 2. FIG. 4 is a timing chart of signals applied to the scanning electrodes of the display panel. FIG. 4 is a pixel arrangement diagram of a part of the display panel. FIG. 5 is an explanatory diagram showing changes in brightness of display pixels in response to A/D conversion output. A specific circuit configuration diagram of the sustaining pulse generation circuit in one embodiment of the present invention, FIG. 7 is a timing chart of main pulses for explaining the operation of the circuit shown in FIG. 6, and FIG. 8 is shown in FIG. Fig. 9 is a timing chart of main pulses when changing the setting state in the circuit; Fig. 9 is a characteristic diagram of input signal versus luminance to explain the relationship between the video signal input to the A/D converter and luminance; Fig. 10 , Fig. 11, 1st
2 is a block diagram showing an example of the configuration of a brightness adjustment circuit for explaining contrast adjustment in the present invention, and FIG. 13 shows a case where the number of sustain pulses assigned to each bit is different from the assignment shown in FIG. 5. In order to explain the present invention in detail, FIG. 14 is a characteristic diagram showing a change in luminance of a display pixel with respect to an A/D conversion output, and FIG. 14 is an example of a circuit configuration for realizing the sustain pulse allocation method shown in FIG. 13. FIG. 15 is an explanatory diagram showing changes in brightness of display pixels with respect to A/D conversion output, for explaining an embodiment in which contrast is adjusted by performing calculations on image data of an A/D converter. FIG. 16 is a block diagram showing an embodiment with scanning different from that in FIG. 1, and FIG. 17 is a timing chart of drive signals applied to the display panel for explaining the operation of the embodiment shown in FIG. 16. Explanation of symbols 1...Video signal input terminal, 2...Video signal processing circuit, 3...A/D converter, 4...Memory, 5...Vertical scanning pulse generation circuit, 6...・Horizontal scanning pulse generation circuit, 7... Sustaining pulse generation circuit, 8, 9.10...
Driver, 11...Display panel, 12...Control circuit, 14...Contrast adjustment circuit Representative Patent Attorney Akio Namiki! ! 121111 a 4 Prisoner 5 ■ (α) Tomi 6 diagram IT Figure 118 Figure M9 diagram (san, level)
(White peak) Figure 10 @ 11 Figure 12 Figure 13 @ Lightning 14 Figure 79, i Atmosphere 15 Figure 161!1

Claims (1)

[Claims] 1. A binary device that emits light when a sustain pulse sufficient to maintain light emission is applied, and enters a non-emission state when not applied, and selectively takes either the light-emission or non-light-emission state. A screen consisting of a binary display panel configured by arranging display elements as pixels in a matrix; a video signal processing circuit that processes input video signals and outputs image signals such as R, G, and B three primary color signals; The image signal from the processing circuit is input and analog/digital conversion (A
/D conversion) and n bits per pixel (however, n is an integer)
an A/D converter that outputs image data as image data; a scanning circuit that scans the screen vertically and horizontally; and a scanning circuit that scans the screen and calculates the weight that has been assigned in advance to each bit constituting the n bits. a sustain pulse generating circuit that totals sustain pulses of corresponding intensities for n bits and applies the sum to the binary display element as a pixel at a scanning position, and Displaying an image in shading with a predetermined number of gradations 2
In a value display panel image display device, by varying the weight assigned in advance to each bit constituting the n bits, the contrast, which is the ratio of the minimum luminous intensity to the maximum luminous intensity of the binary display element as a pixel, can be adjusted. 2 characterized by comprising a contrast adjustment means for adjusting the
Value display panel image display device. 2. In the binary display panel image display device according to claim 1, the scanning circuit scans the screen n times per screen period in a time-sharing manner corresponding to the n bits. The sustaining pulse generating circuit generates a sustaining pulse having an intensity corresponding to a weight assigned in advance to each bit constituting the n bits at a scanning position for each time-divisional scanning corresponding to each bit. 2, characterized in that it consists of a sustaining pulse generation circuit that applies to a binary display element.
Value display panel image display device. 3. In the binary display panel image display device according to claim 1 or 2, the intensity according to the weight assigned in advance to each bit constituting the n bits is
The contrast adjustment means comprises means for adjusting the number of sustain pulses, the pulse width, or the pulse height as a weight. A binary display panel image display device characterized by: 4. In the binary display panel image display device according to claim 1 or 2, means for changing the amplitude of the input video signal on the input side of the A/D converter;
Means for changing the input reference voltage of the D converter, or means for equivalently changing the amplitude of the video signal at the input side of the A/D converter by performing arithmetic processing on the digital signal that is the output of the A/D converter. A binary display panel image display device comprising: controlling the intensity of a sustain pulse applied to each display pixel to adjust contrast, which is the ratio of the minimum emission intensity to the maximum emission intensity of each display pixel. . 5. In the binary display panel image display device according to claim 1 or 2, the binary display panel emits light by applying a sustain pulse and stops emitting light by applying an erase pulse. The contrast adjusting means comprises means for equivalently varying the weights assigned in advance to each bit constituting the n bits by controlling the application timing of the erasing pulse. Binary display panel image display device. 6. In the binary display panel image display device according to claim 5, means for changing the amplitude of the input video signal on the input side of the A/D converter, or means for changing the input reference voltage of the A/D converter. or means for equivalently changing the amplitude of the video signal at the input side of the A/D converter by performing arithmetic processing on the digital signal that is the output of the A/D converter, and thereby changing the amplitude of the video signal at the input side of the A/D converter. A binary display panel image display device, characterized in that the contrast adjustment means comprises means for controlling the timing of an applied erase pulse to adjust the contrast, which is the ratio of the minimum emission intensity to the maximum emission intensity of each pixel.