JPH01162980U

JPH01162980U -

Info

Publication number: JPH01162980U
Application number: JP4214089U
Authority: JP
Priority date: 1989-04-11
Filing date: 1989-04-11
Publication date: 1989-11-14
Anticipated expiration: 2003-02-15
Also published as: JPH055745Y2

Description

[Brief explanation of the drawing]

第１図は本考案装置の一実施例を示す構成図、
第２図ａ，ｂは本考案でいう帯域圧縮の基本原理
を説明するための図、第３図ａ，ｂは帯域圧縮手
法を説明するための図、第４図ａ，ｂはＶＴＲの
録画パターンを説明するための図、第５図は本考
案装置の主要部を具体的に示すブロツク図である
。１……メモリ回路、２，１１……Ｄ／Ａコンバ
ータ、３……高密度ＴＶ、４……クロツク発振器
、５……帯域圧縮回路、６……ＶＴＲ、７……ビ
デオ、アドレス再生回路、８Ａ，８Ｂ……サブメ
モリ回路、９，１０，１７……セレクタ、１２…
…増幅器、１３，２１……Ｘアドレスカウンタ、
１４……フレームカウンタ、１５……並列／直列
変換回路、１６……サンプリング用ゲート回路、
１８……ビダオ同期信号分離回路、１９……Ａ／
Ｄコンバータ、２０……分周回路、２２……垂直
・水平同期分離回路、２３……データサンプリン
グ回路、２４……直列／並列変換回路、２５……
Ｙアドレスカウンタ、２６，２７，２８……ゲー
ト回路。 FIG. 1 is a configuration diagram showing an embodiment of the device of the present invention;
Figures 2a and b are diagrams to explain the basic principle of band compression in this invention, Figures 3a and b are diagrams to explain the band compression method, and Figures 4a and b are VTR recordings. FIG. 5, which is a diagram for explaining the pattern, is a block diagram specifically showing the main parts of the device of the present invention. 1...Memory circuit, 2, 11...D/A converter, 3...High density TV, 4...Clock oscillator, 5...Band compression circuit, 6...VTR, 7...Video, address reproduction circuit, 8A, 8B...Sub memory circuit, 9, 10, 17...Selector, 12...
...Amplifier, 13,21...X address counter,
14...Frame counter, 15...Parallel/serial conversion circuit, 16...Sampling gate circuit,
18...Vidao synchronization signal separation circuit, 19...A/
D converter, 20... Frequency dividing circuit, 22... Vertical/horizontal synchronization separation circuit, 23... Data sampling circuit, 24... Serial/parallel conversion circuit, 25...
Y address counter, 26, 27, 28...gate circuit.

Claims

[Scope of utility model registration request]

A memory circuit having a memory element corresponding to a picture element of a TV screen, a high-density TV in which the repetitive frame period of the TV screen is about the same as that of a commercial TV and the number of horizontal scanning lines is almost twice, and two sub-memory circuits that alternately write m/n dots obtained by dividing a picture element m dot into n equal parts or m/n dots obtained by taking out one dot every time n dots advance, and the memory; a clock oscillator that generates a clock for reading from a circuit and writing to the sub-memory circuit; a means for obtaining a 1/n clock of the clock and an address for reading from the sub-memory circuit; and a frame for counting vertical synchronization signals. a frame counter that generates a number and the high density T
2 at the 1/n clock during the horizontal scanning time of V.
means for alternately reading from the sub-memory circuits;
A circuit for D/A converting the read digital video signal, a circuit for converting the frame number into parallel/serial, and amplifying the D/A converted video signal and reading out the parallel/serial converted signal from the memory circuit. an output amplifier for outputting the horizontal synchronizing signal and the vertical synchronizing signal together with the analog video signal, the horizontal synchronizing signal, and the vertical synchronizing signal; an A/D converter that converts the analog video signal into a digital video signal and outputs it to the memory circuit; a data sampling circuit that extracts a serial frame number from the reproduced vertical synchronization signal; means for converting and outputting it as part of the X address; means for generating and outputting an X address signal for the memory circuit; and means for generating and outputting a Y address signal for the memory circuit from the reproduced horizontal synchronization signal. What is claimed is: 1. A recording and reproducing device characterized in that it is configured to enable recording and reproducing of images displayed on a high-density TV on a commercial TV VTR.