JPH01161841A - Gaas schottky barrier field effect transistor - Google Patents

Gaas schottky barrier field effect transistor

Info

Publication number
JPH01161841A
JPH01161841A JP62320513A JP32051387A JPH01161841A JP H01161841 A JPH01161841 A JP H01161841A JP 62320513 A JP62320513 A JP 62320513A JP 32051387 A JP32051387 A JP 32051387A JP H01161841 A JPH01161841 A JP H01161841A
Authority
JP
Japan
Prior art keywords
bonding pad
bonding
wire
effect transistor
field effect
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62320513A
Other languages
Japanese (ja)
Other versions
JPH0618224B2 (en
Inventor
Yasushi Ose
小瀬　泰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62320513A priority Critical patent/JPH0618224B2/en
Publication of JPH01161841A publication Critical patent/JPH01161841A/en
Publication of JPH0618224B2 publication Critical patent/JPH0618224B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48095—Kinked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01031—Gallium [Ga]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/10329—Gallium arsenide [GaAs]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H01L2924/12032—Schottky diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To prevent the deterioration in characteristics caused by wire bonding by a method wherein at least one of a gate bonding pads and drain bonding pads is constructed in thickness sufficiently thicker than that of the electrode pattern located on the circumference of one bonding pad. CONSTITUTION:A chip 2 and an input circuit substrate 3 are mounted on a package mounting part 1, and a bonding pad 11 is formed in the thickness markedly thicker than that of the bonding pad which was manufactured before so that the upper surface of the circuit electrode pattern 13 of the input circuit substrate 3 becomes the height same as the upper surface of the bonding pad 11 provided at the end part of a gate electrode lead-out part 4. As a result, a bonding wire 21 can be bonded horizontally.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は超高周波帯で動作するＧａＡｓショットキ障壁
電界効果トランジスタ（ＧａＡｓＭＥＳＦＥＴ）に関す
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a GaAs Schottky barrier field effect transistor (GaAs MESFET) that operates in an ultra-high frequency band.

〔従来の技術〕[Conventional technology]

従来のＧａＡｓＭＥＳＦＥＴでは、ゲート側ボンディン
グパッドもしくはドレイン側のボンディングパッドの厚
さは周囲の電極パターンの厚さと同一であった。In conventional GaAs MESFETs, the thickness of the bonding pad on the gate side or the bonding pad on the drain side is the same as the thickness of the surrounding electrode pattern.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

第２図に、従来構造（７）　Ｇ　ａ　Ａ　ｓ　Ｍ　Ｅ　
Ｓ　Ｆ　Ｅ　Ｔの一部断面図を示す、ｌはパッケージマ
ウント部で、チップ２と入力回路基板３が搭載されてい
る。チップ２の端部までゲート電極引出し部４が延在し
、その端部にボンディングパッドｌＯが形成されている
。そして入力回路基板３の回路電極パターン１３とポン
ディングワイヤ２２で結合されている。Figure 2 shows the conventional structure (7)
A partial cross-sectional view of SFET is shown, l is a package mount part, on which a chip 2 and an input circuit board 3 are mounted. A gate electrode extension portion 4 extends to the end of the chip 2, and a bonding pad IO is formed at the end. Then, it is connected to the circuit electrode pattern 13 of the input circuit board 3 by a bonding wire 22.

図において、ボンディングパッドｌＯの厚さは周辺電極
部１２との高さが同じになる厚さになっている。このた
めポンディングワイヤ２２は周辺電極部１２と接触しな
いように′高く張らせるので、線長が長くなり２０ＧＨ
１帯以上のミリ波帯では高いインピーダンスをもつこと
になり、インピーダンス不整合による特性低下の原因と
なっている。In the figure, the thickness of the bonding pad IO is such that it is at the same height as the peripheral electrode portion 12. For this reason, the bonding wire 22 is stretched high so as not to contact the peripheral electrode part 12, so the wire length is increased to 20GH.
It has a high impedance in one or more millimeter wave bands, which causes characteristic deterioration due to impedance mismatch.

またボンディングパッド１０のワイヤの圧痕が周囲の周
辺電極部１２に触れないように、パッド面積を充分に大
きくし、離れた位置でポンディングする必要がある。し
かしこれは寄生容量の増大になる欠点をもつ、また、特
に２０ＧＨｚ帯以上０’）　Ｇ　ａ　Ａ　ｓ　Ｍ　Ｅ　
Ｓ　Ｆ　Ｅ　Ｔにおいては、チップ内各セル間の動作バ
ランスを維持するためチップの横幅を短くして位相差を
減らす設計が必要となるが、ゲートのボンディングパッ
ドが大きいとこれらの設計の障害となる。Furthermore, it is necessary to make the pad area sufficiently large and to perform bonding at a distant position so that the impression of the wire on the bonding pad 10 does not touch the surrounding peripheral electrode section 12. However, this has the disadvantage of increasing parasitic capacitance, and especially in the 20 GHz band and above.
In SFET, a design is required to reduce the phase difference by shortening the chip width in order to maintain the operational balance between each cell within the chip, but if the gate bonding pad is large, this design will be hindered. Become.

本発明の目的は、上記の欠点を除去し、ボンディングパ
ッドの構造を改良し、ポンディングワイヤのポンディン
グに起因する特性低下のないＧａＡｓＭＥＳＦＥＴを提
供することにある。An object of the present invention is to eliminate the above-mentioned drawbacks, improve the structure of the bonding pad, and provide a GaAs MESFET that does not suffer from deterioration in characteristics due to bonding of the bonding wire.

〔問題点を解決するための手段〕[Means for solving problems]

本発明のＧ　ａ　Ａ　ｓ　Ｍ　Ｅ　Ｓ　Ｆ　Ｅ　Ｔは、
ゲートボンディングパッドおよびドレインボンディング
パッドの少なくとも一方がボンディングパッドの周囲に
位置する電極パターンより充分厚い構造としたものであ
る。The G a As M E S F E T of the present invention is
The structure is such that at least one of the gate bonding pad and the drain bonding pad is sufficiently thicker than the electrode pattern located around the bonding pad.

〔作用〕 ゲートもしくはドレインのボンディングパッドの厚さを
充分厚くして、入（出）カ回路基板の電極パターンと両
者の高さが同じになるようにすれば、ポンディングワイ
ヤを屈曲せず水平位置で両者にポンディングできる。し
たがってワイヤ線長は最短となる。また周辺電極部より
、ボンディングパッドが高くなり、ワイヤの圧痕の接触
はないから、パッド面積を拡大する必要がなく、高周波
最適設計に支障を与えない。[Operation] If the thickness of the gate or drain bonding pad is made sufficiently thick so that the height of both is the same as the electrode pattern of the input (output) circuit board, the bonding wire can be kept horizontal without bending. Can pound both in position. Therefore, the wire length becomes the shortest. Furthermore, since the bonding pad is higher than the peripheral electrode portion and there is no contact with the indentation of the wire, there is no need to expand the pad area and there is no problem with the high frequency optimum design.

〔実施例〕〔Example〕

以下、図面を参照して、本発明の一実施例につき説明す
る。第１図は実施例の断面図であって、パッケージマウ
ント部１上にチップ２．入力回路基板３を搭載している
。この実施例はゲート電極引出し側について本発明を適
用したものであるが、ドレイン電極引出し側（出力側）
でも全く同様に適用できる０図に示すように入力回路基
板３の回路電極パターン１３の上面が丁度ゲート電極引
出し部４の端部に設けたボンディングパッド１１の上面
と同じ高さになるように、ボンディングパッド１１の厚
さを従来例より格段と高くしである。これによって、水
平にポンディングワイヤ２１をポンディングすることが
できる０周辺電極部１２はその高さが低いので、上記ポ
ンディングに何ら障害を与えない。Hereinafter, one embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view of the embodiment, in which a chip 2 is mounted on a package mount section 1. It is equipped with an input circuit board 3. In this example, the present invention is applied to the gate electrode extraction side, but the drain electrode extraction side (output side)
However, as shown in FIG. The thickness of the bonding pad 11 is made much higher than that of the conventional example. As a result, the zero peripheral electrode portion 12, which allows the bonding wire 21 to be horizontally bonded, has a low height, so that it does not pose any hindrance to the above-mentioned bonding.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、ＧａＡｓＭＥＳＦＥＴにおいて、
ゲートもしくはドレインもしくは両者のボンディングパ
ッドの厚さを充分厚くすることで、周辺電極部に何られ
ずられされず、入出力回路基板の回路電極パターンと、
略水平の位置でポンディングワイヤを張ることが可能に
なる。したがって、ワイヤ線長は最短のものとなり、ま
たボンディングパッドの面積はワイヤ圧痕を考慮せず高
周波特性上最適にきめることができる。このことから２
０　Ｇ　Ｈｚ以上の高周波デバイスとして特に優れた特
性をうることができる。As explained above, in GaAs MESFET,
By making the thickness of the bonding pad for the gate, drain, or both sufficiently thick, it will not be shifted by the peripheral electrode part, and the circuit electrode pattern of the input/output circuit board,
It becomes possible to stretch the bonding wire in a substantially horizontal position. Therefore, the wire length becomes the shortest, and the area of the bonding pad can be determined optimally from the viewpoint of high frequency characteristics without considering wire impressions. From this, 2
Particularly excellent characteristics can be obtained as a high frequency device of 0 GHz or higher.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例、第２図は従来例のそれぞれ
の断面図である。 ２・・・チップ（ＧａＡｓショットＦＥＴ）、３・・・
入力回路基板。 ４・・・ゲート電極引出し部、 １１・・・ボンディングパッド、 １２・・・周辺電極部、 １３・・・回路電極パターン、 ２１・・・ポンディングワイヤ。 特許出願人　　日本電気株式会社FIG. 1 is a sectional view of one embodiment of the present invention, and FIG. 2 is a sectional view of a conventional example. 2... Chip (GaAs shot FET), 3...
Input circuit board. 4... Gate electrode extension portion, 11... Bonding pad, 12... Peripheral electrode portion, 13... Circuit electrode pattern, 21... Bonding wire. Patent applicant: NEC Corporation

Claims (1)

【特許請求の範囲】[Claims] 　ゲートボンディングパッドおよびドレインボンディン
グパッドの少なくとも一方がボンディングパッドの周囲
に位置する電極パターンより充分厚い構造となっている
ことを特徴とするＧａＡｓショットキ障壁電界効果トラ
ンジスタ。A GaAs Schottky barrier field effect transistor characterized in that at least one of a gate bonding pad and a drain bonding pad has a structure that is sufficiently thicker than an electrode pattern located around the bonding pad.
JP62320513A 1987-12-18 1987-12-18 GaAs shutter barrier field effect transistor Expired - Fee Related JPH0618224B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62320513A JPH0618224B2 (en) 1987-12-18 1987-12-18 GaAs shutter barrier field effect transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62320513A JPH0618224B2 (en) 1987-12-18 1987-12-18 GaAs shutter barrier field effect transistor

Publications (2)

Publication Number Publication Date
JPH01161841A true JPH01161841A (en) 1989-06-26
JPH0618224B2 JPH0618224B2 (en) 1994-03-09

Family

ID=18122286

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62320513A Expired - Fee Related JPH0618224B2 (en) 1987-12-18 1987-12-18 GaAs shutter barrier field effect transistor

Country Status (1)

Country Link
JP (1) JPH0618224B2 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5521184A (en) * 1978-08-03 1980-02-15 Mitsubishi Electric Corp Method of manufacturing schottky barrier-gate type electric field effect transistor
JPS57176877A (en) * 1981-04-23 1982-10-30 Matsushita Graphic Commun Syst Inc Light scanning reader

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5521184A (en) * 1978-08-03 1980-02-15 Mitsubishi Electric Corp Method of manufacturing schottky barrier-gate type electric field effect transistor
JPS57176877A (en) * 1981-04-23 1982-10-30 Matsushita Graphic Commun Syst Inc Light scanning reader

Also Published As

Publication number Publication date
JPH0618224B2 (en) 1994-03-09

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