JPH01161549A - Expansion memory circuit - Google Patents

Abstract

PURPOSE:To attain the expansion of a memory which has no relation with the capacity of an expansion unit and does not require DIP switches at every unit by providing a converter which makes the 1st and 2nd registers and the content of the 1st register to correspond to a space to be mapped. CONSTITUTION:Among the 24-bit addresses from a CPU 1, the high-order four bits are inputted to a decoder 5. On the other hand, registers 2 are the registers which exists at every expansion unit of memories and which address space is to be mapped in written by the CPU 1. Moreover, output results of an AND /OR circuit 6 are written in a register 3 at every access of the CPU 1. Each converter exists at every expansion unit of the memories and their input/output relations are different from each other in accordance with their capacities. The circuit 6 inputs the outputs of the converters 4 and decoders 5 and outputs their AND/OR results by one piece. The circuit 6 exists at every expansion unit of the memories and their outputs are inputted to the register 3 after wired-OR. Thus the expansion of memories are realized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory circuit for a computer system, and particularly to an expansion memory circuit.

[Conventional technology]

An example of a conventional expansion memory system is shown in FIG. 6 and will be described.

In the figure, "21 is the expansion unit of the expansion memory, 22 is the D
The IP switch 23 is a mesori map of the computer system. For example, with this type of expansion memory, as shown in FIG. 6, the user sets which address on the memory map 23 the memory to be expanded should be mapped to for each expansion unit 21 using the DIP switch 22. Ta.

[Problem that the invention seeks to solve]

In the conventional expansion memory method described above, DI is set for each expansion unit.
Since it is necessary to set the P switch, there are problems such as: 1) it is time-consuming; 2) the user's setting ζ is dependent on the user's settings; there is a possibility that the intended expansion will not be carried out.

[Means for solving problems]

The expansion memory circuit of the present invention includes a first register that determines mapping between address spaces of the central processing unit, and a second register that stores information that the expansion unit itself has been accessed from the central processing unit. and a converter for making the contents of the first register correspond to the space to be mapped according to the memory capacity of the expansion unit.

[Effect]

In the present invention, regardless of the capacity of the expansion unit,
I) Memory expansion is performed without setting switches such as IP switches for each expansion unit.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 1 is a block diagram showing an embodiment of an additional memory circuit according to the present invention.

In the figure, 1 is a central processing unit (hereinafter abbreviated as CPU), 2 is a register that determines whether to map to or from the address space of this CP'UI, and 3 is a register that the expansion unit itself is accessed from the CPUUI. 4 is a converter that makes the contents of register 2 correspond to the mapping space according to the memory capacity of the expansion unit;
5 is a decoder, and 6 is an AND-OR circuit which receives the output of the converter 4 and the output of the decoder 5 as inputs.

Next, the operation of the embodiment shown in FIG. 1 will be explained.First, of the 24-bit address output from the CPUI, the upper 4 bits are input to the decoder 5. On the other hand, it has a register 2 and a register 3 that can be accessed from the CPUI, and this register 2 is a register that exists for each memory expansion unit, and the CPUIK writes in which ζ in the address space it is mapped to. Also,
Register 3 is the output result of AND/OR circuit 6 to the CPU
It is assumed that the data is written every time the file is accessed.

Now, the output of register 2 is input to converter 4.

There is one converter 4 for each expansion unit,
The input/output relationship differs depending on the capacity. Table 1 below shows the input/output relationship of this converter 4.
Table 1 is an example of a case where the address space has a capacity for 4 out of 16 divisions of the total address space.Input OutputIn this Table 1, all of the characters other than l in the output are 0.

Next, the AND-OR circuit 6 inputs the output of the converter 4 and the output of the decoder 5, and outputs one result of the AND-OR. The details are as shown in FIG. 2. In FIG. 2, 11 is an AND gate, and 12 is an OR gate.

One AND-OR circuit 6 exists for each expansion unit, and its output is wired-ORed and input to the register 3.

FIG. 3 is a diagram showing the address space of the CPUI in FIG. 1, that is, the memory space that can be accessed by the CPU 1, and the shaded area shows the memory space of the memory that is installed as standard. And numbers 1 to 1 in Figure 3
6 is a number that divides the entire address space into 16 parts and assigns them to each part in order from the lowest address. 2 in this figure 3
It is assumed that the additional memory is mapped to 16 memory spaces. The expansion unit is an integral multiple of 16 divisions of the total memory space.

Table 2 shows the relationship between the input and output of the decoder 50 in FIG.

Table 2 Input Output Note that in Table 2, all blank fields in the output section are O's.

FIG. 4 is a flowchart of the processing to be performed by the CPUI when using the present invention. In this FIG. 4, k is an additional memory number (k=1 to k
mm! ), n is the additional memory area (n-2 to 1
6) is shown. In FIG. 4, the parameters and kmaX are the number and maximum number of extension units determined by the tool for each extension unit, respectively. Further, n is a number indicating each of the 16 divided memory spaces in FIG.

If the process is performed according to the 70-chart in Fig. 4, the additional memory will be sequentially moved from the lowest address to C.
0 that can be mapped into the PUI address space
The results are shown in Fig. 5.0 In this Fig. 5, k wax
w 3.

〔Effect of the invention〕

As explained above, the present invention has the advantage that memory can be expanded regardless of the capacity of each expansion unit and without setting switches such as K DIP switches for each expansion unit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the expansion memory circuit according to the present invention, FIG. 2 is a block diagram showing details of the AND/OR circuit in FIG. 1, and FIG. 3 is a block diagram showing the details of the AND/OR circuit in FIG. 4 is a flowchart of the processing to be performed by the central processing unit when using the present invention, and FIG. 5 is a diagram showing the result of mapping the additional memory according to the flowchart in FIG. 4. , FIG. 6 is a block diagram showing an example of a conventional expansion memory system. 1. Work: central processing unit, 2, 3: register, 4
...Converter, 5...Lin decoder, 6...-AN
D・OR circuit. Patent applicant: NEC Corporation

Claims (1)

[Claims] a first register that determines whether to map to an address space within the address space of the central processing unit; a second register that stores information that the extension unit itself has been accessed from the central processing unit; An expansion memory circuit comprising: a converter for making the contents of the first register correspond to a space to be mapped according to a memory capacity.