JPH01160231A - Clock selecting circuit - Google Patents

Abstract

PURPOSE:To reduce a circuit scale and simultaneously, to facilitate the change of a selecting order, etc., by making the combination of a system selecting order, the input condition of the clock of n-system and the selecting condition of a selecting means into an address, writing corresponding selection information into a selection information storing means, thereafter, designating the system selecting order from an external part and reading the selection information. CONSTITUTION:The address of a ROM 21 is indicated by the 3 combinations of the system selecting order, input clock interruption information and the present selecting condition of a selector. The combination of the states of the three items is made into the address of the ROM 21, and the selection information related to what kind of selecting action the selector is made to execute is written corresponding to the address. Next, the selection information is read by a CPU, and it is given to a selector 31. The selector 31 selects the corresponding system, and a selected clock is given to a phase synchronizing circuit 14. Namely, since the control of the selector is executed in a soft-like way by using the CPU and ROM, the change of the system selecting order and the change of the number of systems can be easily dealt with, and simultaneously, the circuit scale can be made small by using the ROM.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a clock selection circuit that selects one of n input clock sequences, which can easily deal with changes in the sequence selection order, changes in the number of sequences, etc., and can reduce the circuit scale. In a clock selection circuit that selects one series of clocks from among inputted n series of clocks for the purpose of reduction, one series of clocks is selected from among the n series of clocks in response to the output of the selection information storage means. selection means for controlling the selection means is provided, selection information for controlling the selection means is written in the selection information storage means, and selection information for controlling the selection means is provided, and selection information for controlling the selection means is provided, and selection information corresponding to the input state of the n-series clock 1 selection means and the set sequence selection order is provided. The configuration is configured so that the selection information to be selected is read out.

[Industrial application field]

The present invention relates to a clock selection circuit that selects one of n input clock sequences.

In recent years, for example 64.192.384.768.1536
．． Computer communication, high-speed data transmission and 2 image transmission using a digital dedicated line with a transmission speed of 6144Kb.

Transmission based primarily on telephone calls and a combination of these transmissions tend to be widely used.

Now, FIG. 3 shows an explanatory diagram of an example of a system to which the present invention is applied. In the figure, for example, a multimedia multiplex device is connected to digital networks-1 to digital networks-n via transmission path interfaces NPI to NPfl and corresponding digital dedicated lines, and communicates with the other parties.

At this time, the multimedia multiplexer extracts n series of clocks from the data input to each transmission line interface and applies them to the clock selection circuit 1. Then, this circuit selects one series of clocks, generates an internal clock synchronized with the selected clock, and operates the internal circuit of the multimedia multiplexing device using this internal clock.

At this time, it is necessary for the clock selection circuit to be able to easily cope with changes in sequence selection order and reduction in the number of sequences, and to reduce the circuit scale.

[Conventional technology]

FIG. 4 shows a block diagram of a conventional example.

In the figure, if the two input clock series, namely clock-1 and clock-2 (hereinafter abbreviated to C as -1 and CK-2), are both normal, the CK-1 disconnection detector 11゜CK- 2 The disconnection detection output is not sent from the disconnection detector 12, and the output of the reset cent flip-flop (hereinafter abbreviated as R5-FF) 13 is 1. For example, the selector 14 selects CK-1 as shown by the solid line, so the CK -1 is phase locked circuit 1
Enter 5.

The phase synchronization circuit 15 generates an internal clock synchronized with the input GK-1 and transfers it to a necessary location within the device.

Next, when CK-1 is disconnected, the disconnection detection output from the disconnection detection circuit 11 is applied to R3-FF, so R5-F
The output state of F changes and the selector 14 becomes as shown by the dotted line, and -2 is selected for C and added to the 9-phase synchronization circuit 15, so that the internal clock synchronized with CK-2 is transferred.

[Problem that the invention seeks to solve]

Here, if there are few clock series to switch, 1
For example, it is not necessary to say in what order the series are selected.

However, as networking has progressed recently, there are now multiple clock sequences to switch to, as shown in Figure 3. For example, it is necessary to predetermine the selection order of the sequences and manage the selected light according to this order. It has become.

On the other hand, in recent years, there has been a trend toward smaller devices, so the clock selection circuit has to be made smaller in size and also be able to easily deal with changes in the selection order mentioned above. be.

[Means for solving problems]

FIG. 1 shows a block diagram of the principle of the present invention.

In the figure, 3 is a selection means for selecting one series of clocks from among n series of clocks in response to the output of the selection information storage means, and 2 is a selection means in which selection information for controlling the selection means is written, and selection information for controlling the selection means is written. The selection information storage means reads out selection information corresponding to the input state of the clock, the selection state of the selection means, and the set sequence selection order.

[Effect]

The present invention is based on the series selection order, the input state of the clock of n series 9
After writing the corresponding selection information into the selection information storage means 2 using the combination of selection states of the selection means as an address, the sequence selection order is specified from the outside, and the corresponding selection is made from the current clock input state and the selection state of the selection means 3. The information is read out, and one series of clocks out of the n series of clocks to be input is selected using this selection information.

Here, by using a storage means of a large-scale integrated circuit as the selection information storage means 2, the circuit scale can be reduced and changes in the selection order can be easily dealt with.

〔Example〕

FIG. 2 is a block diagram of an embodiment of the invention.

Here, ROM 21. The flip-flop 22 is a component of the selection information storage means 2, and the selector 31 is a component of the selection means 3.
The constituent parts of are shown. Note that the same reference numerals indicate the same objects throughout the figures. The operation of the diagram will be described below assuming that four series of clocks are input.

First, the address of the ROM 21 is indicated by three combinations: (1) sequence selection order, (2) major clock failure information, and (2) current selection state of the selector.

Regarding item (2), the order is given when selecting the four series of clocks. For example, selecting sequences in the order of sequence l - sequence 2, sequence 3, and sequence 4 means that if all the sequences are normal, sequence 1 will be selected, but if a failure occurs in sequence 1, sequence 2 will be selected.
If it is normal, select series 2. Also, if a failure occurs in sequence 1.2, the normal sequence 3 is selected, but sequence 1.2.3
This indicates that if a failure occurs in sequence 4, the normal sequence 4 will be selected.

Regarding term (2), find all possible disconnection states of the four clock series.

Regarding item (2), we will find the select states that the selector can take.In addition to selecting the four clock systems, the select states include five states in which no clock is input to the phase synchronization circuit 14, and the circuit is in a free-running state. Suppose there is a state.

Then, the combination of these states from ■ to ■ is RO
The address becomes the address M21, and select information indicating what kind of select operation is to be performed by the selector is written corresponding to this address.

Next, the selection information is read out as follows.

That is, the CPU (not shown) sets the sequence selection order of item (2) and inputs it to the ROM 21. For items ■ and ■, the current state is 1, for example, always in ROM.
It has been added to 21.

Then, the selection information corresponding to this address is read out and applied to the selector 31 via the flip-flop 22. The selector 31 selects the corresponding series,
The selected clock is applied to the phase synchronization circuit 14.

That is, since the selector is controlled by software using the CPU and ROM, it is possible to easily deal with changes in the sequence selection order, the number of sequences, etc., and the use of the ROM reduces the circuit scale.

〔Effect of the invention〕

As described above in detail, the present invention has the advantage of reducing the circuit scale and easily dealing with changes in the selection order.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram of an embodiment of the present invention, Fig. 3 is an explanatory diagram of an example of a system to which the present invention is applied, and Fig. 4 is a block diagram of a conventional example. show. In the figure, 2 indicates selection information storage means, and 3 indicates selection means. Books and 5g permissible 0 cool chips ¥7'mouth"・17 bibrooms 1 A2 Diagram

Claims (1)

[Claims] One of n series of input clocks (n is a positive integer)
In a clock selection circuit for selecting a series of clocks, a selection means (3) is provided for selecting one series of clocks from among the n series of clocks in response to the output of the selection information storage means (2), and the selection information is Selection information for controlling the selection means is written in the storage means (2), and corresponding selection information is read out from the input state of the clock of the n series, the selection state of the selection means, and the set sequence selection order. A clock selection circuit characterized in that: