JPS6338346A - Communication control equipment - Google Patents

Abstract

PURPOSE:To attain the acquisition and return of buffers as well as information on buffer addresses between two CPUs by using a hardware using two FIFO memories in place of a software to control buffers. CONSTITUTION:A means is provided to secure an interface between CPUs1 and 2 taking charge of adjacent layers by means of a common buffer together with a means to manage the address of the buffer via the hardware of types of two FIFO memories 3 and 4. Then plural buffer addresses are stored in both memories 3 and 4 and then delivered successively with the instructions of both CPUs1 and 2. These addresses are sent back to the CPUs1 and 2 and therefore the buffer is acquired. In addition, both CPUs1 and 2 can perform processes independently and in parallel with each other just with a hardware means and without distributing the same buffer control programs to both CPUs1 and 2. Thus the transfer of control is attained and the overhead of the buffer management due to the software is reduced. Thus, the protocol processing speed is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a communication control device that executes parallel processing of communication control protocols 1 to 1 through multiple CPUs.

Conventional technology FIG. 2 shows a configuration diagram of a conventional communication control device.

In FIG. 2, 2] and 22 are C11Us, each connected to the arbiter 23. A shared memory 24 is connected to the arbiter 23.

Next, the operation of the prior art example 1- will be explained. In FIG. 2, both CPtJ2] and 22 have the same value.
A program is implemented to manage the common buffer provided in 4. One C11TJ 21 issues a command to acquire a buffer through the arbiter 2:l, acquires a buffer from the memory 24 with "1:", and confirms the response. The other CPU 22 learns the address of this buffer by the interrupt notification, accesses the buffer through the arbiter 2:j, and returns it.

In the arbiter 23, there are two CP[J2], J(
It mediates conflicts in access to memory 24. .

In this way, even in the conventional communication control bag Ft, by placing 1 gram of buffer management capacity in each of the CPUs 21 and 22, buffers can be acquired and returned in the shared memory 24.

Problems to be Solved by the Invention However, in the conventional communication control device described above, a buffer input/output program must be placed in all of the CIs U21 and 22 used, and management of the buffer in the shared memory 24-1- is required. was done on a shared management table, so
If a conflict occurs when accessing a buffer, one CP
U goes into a waiting state, there is a complicated buffer management procedure in rough 1~ware, 71~responses of the acquired buffer must be managed until the buffer is returned, and the other party's C
There were problems such as the need to notify the PU of the address of the acquisition buffer.

The present invention solves these conventional problems,
It is an object of the present invention to provide an excellent communication control device that can transfer control between two CP TJs using hardware without buffer management using a program.

Means for Solving the Problems In order to solve the problems described in the present invention, the buffer management that was previously done by software is managed by software using two FLL/0 memories. The buffer address is acquired and returned, and the buffer address is notified between both CPUs.

Operation With the above configuration, a buffer can be acquired by inputting and storing multiple buffer addresses in the FIF○ memory, outputting the buffer addresses one by one according to the instructions of the CPU, and returning them to the CPU. FIF
Input into O memory. The other CPU can know the buffer used by the other CPU by outputting the buffer address from its FIFO memory and referring to it as necessary. By returning the address of the buffer for which processing has been completed to the original FIFO memory, return of the buffer is completed and the buffer can be used endlessly like a ring buffer. This allows two CPs in charge of adjacent layers to
Without placing the same buffer management program in U, both CIs can perform parallel processing independently using only hardware means, and control can be passed and received.
This has the effect of reducing the overhead of software buffer management and speeding up protocol processing.

Embodiment One embodiment of the present invention will be described based on the drawings. 1 FIG. 1 shows a configuration diagram of an embodiment of the present invention. In FIG. 1, CPU 1 is connected to port 5, and from port 5 passes through pulse generator 14 to SIFT IN of FIFO memory 4, and passes through pulse generator 15 to SIFT IN of FIFO memory 4.
Connected to 5IFT/OtJT of IFO memory 3. The CPU 2 is connected to the boat 6, and further passes from the boat 6 through the pulse generator 16 to the FII? O memory 3 5I
to FT/IN, and also to FiFO through pulse generator 17.
It is connected to SI I'''I''・OUT of memory 4. The data selector 7 inputs data to the FIFO memory 3 through the input of CI) tJL, further inputs the data to the I-'T''0 memory 4 through the latch circuit 11, and returns to the data selector 7 through the latch circuit 12.Decoder 8 receives input from the CPU 2 and latch circuit 11, and decoder 9 receives input from CPU 2 and latch circuit 12.
In response to the input, the shared memory 13 is accessed through the arbiter 10.

Next, the operation of the above embodiment will be explained. At initialization, the CPUI becomes the master, and the data selector 7
Connect PUI and FIFO memory 3,
Enter the full address of the buffer in . Thereafter, the data selector 7 separates the CI) U 1 from the FIFO memory 3. When receiving and passing an event from the CPUI to the CPT and J2, a clock is generated from the pulse generator 15 at 5IFT-OUT of the FIFO memory 3, and this is done manually. FI
The buffer address output from the FO memory 3 is latched by the latch circuit 11. The addresses output from the FIFO memory 3 are only the upper addresses of the buffer, which are managed by the decoder 8. Therefore, when the CPU 1 accesses the shared memory 13, it can only access a specific address. After writing an event to the buffer, in order to notify the buffer address to cpu2, the pulse generator 14 generates a pulse and inputs it to 5TFT IN of the FIFO memory 4, thereby writing the buffer output from the FIFO memory 3. Load the upper address into the FIFO memory 4. After that, C.P.
U1 connects CPU U2 via soft command from port 5.
An interrupt is generated and control is transferred to the CPU 2. C.I.
)
A pulse from the pulse generator 17 is input to IFT-OUT to output the upper address of the buffer in which the event is stored, and the latch circuit 12 latches it. This address can access the buffer in the shared memory 13 by the action of the decoder 9.

When the processing is completed, the CPU 2 generates a pulse from the pulse generator I6, sends it to 5IFT•IN of the FIFO memory 3, and takes in the buffer address after the processing completed returned from the FIFO memory 4 into the FIF◯ memory 3. Also, F
The OUT/EIA of the IFO memory 4 notifies the CPU 2 that the buffer address has become empty and monitors the address.

In this way, according to the above embodiment, the FIFO memory notifies the CPU of the buffer address as necessary, so both CPUs can access the shared memory without worrying about the buffer address at all. has advantages.

Effects of the Invention According to the present invention, when control is transferred between adjacent CPUs using a common buffer, the buffers on the shared memory are not managed by software as in the past, but by hardware. Since this can be done using hardware, each CPU can execute processing independently without having to be aware of complicated buffer management.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram of a communication control device showing an embodiment of the present invention, and FIG. 2 is a schematic block diagram of a conventional communication control device. 1.2...CPU, 3,4...FIFO memory, 5
゜6...I/O port, 7...Data selector, 8,9
...decoder, 10...arbiter, 11, +-
2... Latch circuit, 13... Shared memory, 14, 15
, 16.17...Pulse generator representative Yoshi Morimoto Hirohito Toyo

Claims (1)

[Claims] 1. A communication processing device that executes parallel processing of communication control protocols using multiple CPUs, which includes means for interfacing between CPUs in charge of adjacent layers using a common buffer, and buffer addresses in two FIFO memory formats. A means for managing the buffer with hardware, a means for acquiring a buffer from a common buffer when an event occurs, a means for notifying the CPU in charge of an adjacent layer of the occurrence of an event, and a means for reusing this buffer after protocol processing in the adjacent layer is completed. a communication control device having means for returning to a common buffer;