JPH01158822A - Digital-analog conversion method and its circuit - Google Patents

Abstract

PURPOSE:To realize a high speed and highly accurate D-A converter by the monolithic circuit integration technology by repeating a prescribed operation. CONSTITUTION:A binary input digital signal (b) in n-bit is fetched in a shift register 5, the signal is converted into an analog voltage according to equations I, II (the inverse of bi represents NOT of bi), obtained voltages Vr(i), Va(i) are held in sample-and-hold circuits 31, 32 and then held in sample-and-hold circuits 33, 34. Then the next digit of the digital signal (b) is outputted from the shift register 5 and converted into an analog voltage to obtain Vr(i+1) and Va(i+1). The conversion is finished by repeating the procedure above till the least significant digit of the digital signal (b). Thus, the output analog voltage Va(n) is obtained at a high speed with high accuracy.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a conversion algorithm for converting a one-digit m-ary digital signal into an analog signal.

[Summary of the invention]

When converting a signal having a 1-digit m-adic digital value into an analog signal, the present invention sets the value of the i-th digit from the most significant digit of the 0-digit digital value to bi and i
is 1, and the first voltage is Va(i) and the second voltage is Vr(i), then Va(i+1) −(V
r(i) −Va(i)) +Va(i), and repeat the operation (c) in sequence until i becomes equal to n from 1. It provides:

[Conventional technology]

The digital-to-analog (hereinafter abbreviated as DA) conversion method that is currently commonly used is, when the input is a binary signal, n
A serial type that converts a bit-by-bit digital signal into an analog voltage starting from the least significant digit and adds the results in a weighted manner (
(circulating type) and a voltage divider consisting of 2″-1 equal resistor,
It is roughly divided into a binary loaded constant current source and a parallel type using an R-2R resistance ladder.

The above series type can be configured with a small number of elements, but the current method starts conversion from the least significant bit, making it difficult to increase speed by pipeline connection, and converting digital data from the most significant bit. Successive approximation type analog-digital (hereinafter A-
(abbreviated as D) is not suitable for converters. For this reason, the above-mentioned parallel type is used as the -A converter necessary for the successive approximation type A-D converter, and this becomes a factor in increasing the cost.

Among the parallel D-A converters, the method using the R-2R resistor ladder uses a small number of elements and is suitable for high-speed conversion, but since the on-resistance of the switch affects conversion accuracy, it It is difficult to achieve high conversion accuracy.

The present invention has been made to solve these problems, and provides a D-A conversion method and its circuit that can realize a high-speed and high-precision D-A converter using monolithic integration technology. The purpose is to

[Means for solving problems]

In the present invention, (a) the first voltage is set to the first reference voltage in the initial state, and the second voltage is set to the second reference voltage; (b) the n-digit input digital value is The value of the i-th digit from the most significant digit is bi, and i is first set to 1. (c) At this time, the first voltage is Va(i), and the second voltage is Vr.
(i), then Va(i+1) is Va(i+1) =
-(Vr(i) -Va(i))+Va(i), and repeat the operation (c) in sequence until Vr(i+1) is equal to (d)i from 1 to n. .

[Effect]

By the above means, the output analog voltage Va (n) can be obtained at high speed and with high accuracy for an input digital value of n-digit m-ary number.

〔Example〕

FIG. 2 is a block diagram of a DA converter in which the input digital signal is 1 bit, illustrating the principle of the DA conversion method of the present invention. In the figure, 1.2 is the reference voltage input terminal, 3.4 is the output terminal, 11 and n2 are resistors with equal resistance value R, and 21.23 is the input terminal when the bit value bi of the human input digital signal is "1". Switch turned on, 2
2.24 is a switch that is turned on when the above bi of the input digital signal is "0", 31.32 is a sample and hold circuit which is an example of voltage holding means, and the analog voltage corresponding to the input bit value bi is held in this sample and hold circuit. circuit 32
The signal is output from output terminal 4.

The input/output characteristics of the DA converter regarding n-bit binary signals are expressed by the following equation.

Here, b=b, ,b,----
--- bA is an n-bit binary number with bl as the most significant digit and b, , as the least significant digit, Vr is the reference voltage, and Va (n) is the analog voltage obtained by conversion. To perform this n-bit DA conversion one bit at a time starting from the most significant digit, the following operations are required.

Va(i) = Va(i-1) +2-'biVr
−−−−−−(2) (i=1.2.−−−1−・−−
-----------n) Here, Va (i-1) is the analog voltage obtained by bit conversion from the most significant digit to the i-1st digit, and Va (i) is the i-th bit b
It is an analog voltage obtained by converting i, and is Va (0
)=O. Now, in the i-1st operation, Vr(
i-1)-Va(i-1) = 2- ('-”Vr-
−−−−−−−−−Voltage Vr that satisfies the relationship (3)
(i-1) shall be obtained.

From equation (3), substituting this equation (4) into equation (2), we get Va(i-
1) −(bi+bi) Va(i−1) −−1−−−−−−(6), so we can convert this (6) 2 to the
5) By substituting into the equation, we get: Substituting this equation (7) into equation (3), and Vr(i)−Va(i) −2−′Vr −−−−−
-----------Using the relationship (8), we can obtain. However, Vr (0) - Vr.

Equations (7) and (9) show the DA conversion algorithm of the present invention, and a block diagram of a circuit that executes this algorithm is shown in FIG. 2 mentioned above.

For D-A conversion, connect terminal 1 in Figure 2 to the reference voltage and ground terminal 2 to perform Vr (0) =
Initialize Vr, Va (0) −〇 and convert the most significant digit. For the second and subsequent bit conversions, either connect the unit configurations shown in Figure 2 in cascade to terminals 3 and 4 to form a pipeline type, or input the output voltage of terminals 3 and 4 again to terminals 1 and 2, respectively. This is done in a circular manner.

FIG. 1 shows a first embodiment of the present invention, in which the D
The above-mentioned circulating type I)-A converter using the -A conversion method is shown.

In FIG. 1, 31 to 34 are sample and hold circuits;
4 is a reference voltage source, 5 is a shift register that holds the input digital signal, and 62 and 63 are control signals that open the switches 21 to 24 based on each bit value bi of the input digital signal and the two-phase clock signals φ and T. 7 is an inverter, L (Load) is a digital control signal for loading the input digital signal into the shift register 5, C0nv is a digital control signal indicating the conversion state, 61
is an AN that outputs a shift pulse S that opens and closes the switches 25 and 26 based on the signal Conv and the clock signal φ.
In the D circuit, 27 and 28 are switches that are closed by the latch pulse L.

Next, the conversion operation with the above configuration will be explained.

In the load L state, the input digital signal is taken into the shift register 5, and at the same time, the switch 27 is closed to supply the reference voltage 4 to the sample and hold circuit 33, and the switch 28 is closed and the input terminal of the sample and hold circuit 34 is input. Set the initial state by grounding. Conversion (conv)
In this state, the most significant digit of the digital signal is converted into an analog voltage according to equations (7) and (9) during the period of the first clock signal, and the resulting voltage Vr
(1) and Va (1) in the sample and hold circuit 31.
32 respectively, and the next clock signal φ
Hold for the period of . Sample hold circuit 33.3
4 samples these voltages Vr (1) and Va (1), respectively, and holds them during the period of the next clock signal 7. During the period of this clock signal 7, the next digit b2 of the digital signal is output from the shift register 5 and converted to an analog voltage, thereby Vr (2), Va (2
) is obtained. The cyclic DA converter completes the conversion by repeating the above conversion procedure up to the least significant digit of the digital signal.

The procedure described above is summarized as follows.

(a) If the most significant digit of the input digital signal is 11,
The reference voltage ■r is input to the sample and hold circuit 31, and the voltage of 1/2 of the reference voltage Vr divided by the resistors 11 and n2 is input and held to the sample and hold circuit 32, and the most significant digit is "0". In this case, a voltage 1/2 of the reference voltage is input to the sample hold circuit 31, and a voltage O is input to the sample hold circuit 32 and held.

(b) The output voltage of the sample and hold circuit 31 is input to the sample and hold circuit 33, and the output voltage of the sample and hold circuit 34 is
The output voltage of the sample hold 32 is held respectively.

(c) If the next digit after the most significant digit is "1", the output voltage of the sample hold circuit 33 is sent to the sample hold circuit 31, and the sum of the output voltages of the sample hold circuits 33 and 34 is sent to the sample hold circuit 32. Input and hold each voltage of 172, and if the next digit after the above-mentioned highest digit is 10,
The sample and hold circuit 31 receives a voltage that is 1/2 of the sum of the output voltages of the sample and hold circuits 33 and 34, and the sample and hold circuit 32 receives a voltage that is 1/2 of the sum of the output voltages of the sample and hold circuits 33 and 34.
Input and hold the respective output voltages.

(d) Repeat the steps (b) and (c) above until the lowest digit of the human-powered digital signal.

FIG. 3 is a second embodiment, showing a successive approximation type AD converter using the DA conversion method according to the present invention.

In FIG. 3, 31.32 is a unity gain amplifier 311.
321 and capacitors 312 and 322, 4 is a reference voltage source, 9 is a shift register that stores the binary number of the conversion result, and 6 is a conversion status signal (co
AN0 circuit that generates an open/close control signal for the switch 24 from nv) and a two-phase lock signal φ, 7 is an inverter that outputs an open/close control signal for the switches 22 and 25, 8 is a sampled input analog signal and a resistor 11, n2 30 is a capacitor having the same capacitance value as capacitors 312 and 322,
L (Latch) is a control signal for outputting the conversion result from the shift register 9.

In the above configuration, in the latched state, the capacitor 312
is charged to the reference voltage Vr, and the capacitor 322 is grounded and discharged. Therefore, the threshold voltage Vt(0) of the comparator 8 is V r /2. In the first sampling cycle of the conversion state, the input analog voltage Va is compared with the threshold voltage Vt(0) in the comparator 8, and Va>
If Vt (0), then rlJ, Va<Vt (
0), bl is determined to be "0". During the period of the next clock signal, if bl=rlJ, the capacitor 30 forming part of the voltage holding means is charged to the reference voltage, and is connected in parallel to the capacitor 322 during the period of the clock signal φ of the next cycle. This causes capacitor 322 to be at V
charged to r/2. Therefore, Vr (1) −V
r, Va (1) −Vr/2, Vt(1)=' (3
/4) Vr. On the other hand, b+=r.

”, V r (1) − V r /2, Va
(1)=0, Vt (1)=(1/4)Vr. During the next clock signal period, the input analog voltage Va is compared with the threshold voltage vt (1) by the comparator 8, and V
If a > v t (1), bz = Ill, Va <
If Vt(1), bz-rOJ is determined. In the next cycle, Vt (2) is determined by b2, and this vt
b3 is determined by comparing (2) with Va. Thereafter, the above procedure is repeated a desired number of times to complete the conversion and return to the lunch state.

When the present invention is applied to a sequential type AD converter, the analog output from the DA converter can be modified in various ways as shown in FIGS. 3, 8, and 9.

FIG. 4 shows a third embodiment, in which 1 bit D-A of FIG.
This figure shows an n-bit pipeline type D-A converter in which converters are connected in cascade in n stages, and the second stage circuit 10□ to the n-1 stage circuit 10. ,-.

Up to this point, the configuration is the same as that of the first stage circuit 10+.

First stage circuit 10. is the most significant digit b1.The second stage circuit 10° is the next digit b2, and thereafter, the final stage circuit 10° is the least significant digit b
Perform 9 conversions. The final stage circuit 10° has resistances nil, n
12. Switch n2 closed at bit value s, , b.
3, n24 is configured as shown in the figure. Each bit is connected to each stage of the circuit 10° to 10. By inputting the signals simultaneously, this configuration becomes an n-bit parallel D-A converter.

Although the case where the input digital signal is an n-bit binary number has been described above, the present invention can be applied to a human-powered digital signal having a digital value of a 0-digit m-ary number. In that case, the algorithm is Va(n) −VLo+Σbim −′ (VHOV
LO)-----------11-----(10)
is used.

FIG. 5 is a fourth embodiment of the present invention, and shows a D-A converter applicable to an n-digit m-adic digital signal.

DA conversion in this circuit is performed as follows.

(a) The first reference voltage V is applied to the sample hold circuit 33.
Ho and the second reference voltage VLO are held in the sample and hold circuit 34, and (b), if the value of the i-th digit from the most significant digit of the one-digit digital value to be converted is bi, then i is First, as 1, (c), the outputs of the sample and hold circuit 33 and the sample and hold circuit 34 are Va (i) and Vr (i
), then the sample bold circuit 31 holds a voltage equivalent to (Vr(i)-Va(i)) +Va(i), and the sample hold circuit 32 holds a voltage equivalent to W m , (d) , Next, the output of the sample and hold circuit 31 is held in the sample and hold circuit 33, and the output of the sample and hold circuit 32 is held in the sample and hold circuit 34, and then i is increased by 1, and (e), i (c), (d
) are repeated in sequence, and (f), D- is output as the sample and hold circuit 34.
An A-converted analog voltage Va (n) is obtained.

Next, fifth to ninth embodiments of the present invention will be schematically described with reference to FIGS. 6 to 10.

FIG. 6 shows a quaternary D/A converter according to the fifth embodiment. In the figure, A1A, □, A2Az2 are unity gain amplifiers, S, S1□, S2I, S2□, S3゜, S
3 pieces/S32~333/340/S, 1% S42
indicates a switch, CI I, CI2, C2, and C2□ indicates a capacitor. In addition, two reference power supplies VLO, Vl (
. is provided.

In FIG. 6, for example, vto=ov, Voo=6.4
■, quaternary number “123” (binary number “011011”)
, which corresponds to the decimal number "27") to an analog signal, (a) At the same time as the signal for loading digital data,
(b) Load digital data into the shift register (c) b, -i, so switches 331 and 341 are closed. , to capacitors C1□, C2□ (□ (6,4
-0) + O) = 3.2 V and (-(6,4-0)
+O) = 1.6 V is held, (d) switch SI2, Sol is closed, capacitor C1
1% Cal was maintained at 3.2■ and 1.6■, respectively, (
e) Shift the shift register, (f) Since b2=2, switches S3□ and S4□ are closed, and capacitors C+Z and C2□ become (-(3,2-1,6)+1.6
) =2.8V.

(-□ (3,2-1,6) +1.6 > =
(g) Close switch 312, S21, and capacitor C
11% Cz+ is held at 2.8V and 2.4V respectively,
(h) Shift the shift register, (t) bs=3
Therefore, switches S33, S4. When l is closed, capacitors C1゜ and C2□ are (□ (2, 81, 4> +
2.4 > =2.8 V, (-(2,8-2,4)
+2.4) held at -2.7v, (j) close switches SI2, S21 and capacitor C
I and C21 are held at 2.8■ and 2.7■, respectively,
(k) A conversion output of 2.7V can be obtained from Va.

FIG. 7 shows a sixth embodiment, which is a binary D/A converter consisting of three sample and hold circuits S/H1-3/H3.

In FIG. 7, SI, S2, and S3 are switches R+
, Rz indicate resistances of equal value.

Next, the operation will be explained.

(a) At the same time as the signal to load the digital data, switch 320% S1O is closed and the reference voltage is held in the sample and hold circuits S/H+ and S/H2, (b) The digital data is transferred to the shift register by the signal. (c) By closing switch S3, the arithmetic mean of the output voltages of sample and hold recesses PrS/HI and S/H2 is held in sample and hold circuit S/H3, (d) When bi=1, switch SI The output of the sample and hold circuit S/H3 is input to the sample and hold circuit s/Hl and its voltage is held by closing the switch S2. Input the output of S/H3 to the sample hold circuit S/Hz and hold the voltage, (e) Input shift pulse φ to the shift register to shift the data, (f) Above (c) (d) Repeat (e) once, and
Obtain analog output from a.

In each of the above embodiments, the sample and hold circuit used as the voltage holding means is not limited to a simple combination of a capacitor and a buffer amplifier;
A similar effect can be obtained by using various improved sample and hold circuits designed to improve the accuracy of the holding potential of the sample and hold circuit.

FIG. 8 (a>(b) shows an example of a sequential A/D converter using the D/A converter shown in FIG. 2 in the seventh embodiment. This circuit also allows A/D conversion similar to that of the second embodiment shown in FIG. 3 described above is possible.

FIG. 9 is an eighth embodiment, which shows an embodiment of a sequential A/D converter using the quaternary D/A converter shown in FIG. The conversion method is basically the same as in the second embodiment 4, but by using comparators C+, C2, and C3, it is possible to convert 2 bits at a time in the ■ cycle, and A/
D conversion speed is improved.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to realize a DA converter and an AD converter with an extremely simple configuration. Furthermore, since the conversion time is determined only by the settling time of the sample-and-hold circuit, a high-speed data converter for video signal processing, for example, can also be realized using a monolithic integrated circuit. Therefore, the present invention will have an extremely important effect on the future development of data converters.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a circulating type A converter which is the first embodiment of the present invention, FIG. 2 is a circuit diagram showing the principle of the digital-to-analog conversion method of the present invention, and FIG. 3 is a circuit diagram of the present invention. FIG. 4 is a circuit diagram of a successive approximation type A converter which is a second embodiment of the invention, and FIG. 4 is a circuit diagram of a pipeline type I)-A converter which is a third embodiment of the invention.
A circuit diagram of a converter. FIG. 5 is a circuit diagram of a D-A converter in the case of an n-digit m-adic digital signal showing a fourth embodiment of the present invention. FIGS. FIG. 8 is a circuit diagram showing Examples 1 to 8; In addition, in the reference numerals used in the drawings, 11, 12------------all have the same resistance value R21~28------------------switch 31~
34-11---Sample hold circuit 4------
−−−−・−−−111 Reference voltage source 5−−−−−−−
---------Shift registers 61 to 63---
-------AND circuit 7-----
---It is an inverter.

Claims (1)

[Claims] 1. In a digital-to-analog conversion method for converting a signal having an n-digit m-ary digital value into an analog signal, (a) a first voltage is set as a first reference voltage in an initial state; (b) The value of the i-th digit from the most significant digit of the above n-digit digital value is set as bi, and i is first set as 1, (c) This When the first voltage is Va(i), the second voltage is Va(i), and the second voltage is Va(i).
When the voltage of is Vr(i), Va(i+1) is Va(
i+1)=bi/m(Vr(i)-Va(i))+Va
(i) and set Vr(i+1) to Vr(i+1)
=bi/m+1/m(Vr(i)-Va(i))+Va
A digital-to-analog conversion method characterized in that (i) and (d) an analog voltage is obtained by sequentially repeating the operation of (c) until i becomes equal to from 1 to n. Using two or four voltage holding means, the voltage holding means holds Va(i), Vr(i), Va(i+1) and Vr(i+1) n times for i=1 to n, respectively. A digital-to-analog conversion method according to claim 1, characterized in that: 3. In a digital-to-analog conversion method for converting a signal having an n-digit binary digital value into an analog signal, at least two voltage holding means are used, and the voltage holding means allows at least Va(i) and Vr(i )of,
Hold n times for i=1 to n, Va(i+1)=@bi@Va(i)+bi/2(Va
(i)+Vr(i)), and Vr(i+1)=bi/2
(Va(i)+Vr(i))+@bi@Vr(i) (where @bi@ represents the negation of bi). Analog conversion method. Va(i), Vr(i), and 1/2(V
4. The digital-to-analog conversion method according to claim 3, wherein a(i)+Vr(i)) is held n times for i=1 to n. Using three voltage holding means, Va(i)+Vr(i) and Va(i) or Vr(
i) for i=1 to n, respectively.
4. The digital-to-analog conversion method according to claim 3, wherein the digital-to-analog conversion method is held twice. 6.2(n-1) voltage holding means are used, and (n-1) corresponding to i=1 to n-1 are respectively applied to the voltage holding means.
1) The digital-to-analog conversion method according to claim 1, wherein the set of Va(i) and Vr(i) is sequentially held. 7. In a digital-to-analog conversion circuit that converts a signal having an n-digit m-ary digital value into an analog signal, in the initial state, the first voltage is set to the first reference voltage, and the second voltage is set to the second voltage. means for setting the reference voltage to a reference voltage of 2, and the i-th digit from the most significant digit of the n-digit digital value to
i, the first voltage is Va(i), and the second voltage is Vr(i), then Va(i+1)=bi/m(Vr(i)-Va(i))
While setting Va(i+1) to be +Va(i), Vr(i+1)=(bi/m+1/m)(Vr(i)−
means for setting Vr(i+1) to be Va(i))+Va(i), and Va(i), Vr
(i) A digital-to-analog conversion circuit characterized in that it is provided with a control means for setting. 8, Va(i), Vr(i), Va(i+1), Vr(
8. The digital-to-analog conversion circuit according to claim 7, characterized in that four voltage holding means are provided for holding each voltage i+1). 9. In a conversion circuit that converts an n-digit binary digital value, a voltage holding means is provided, and this voltage holding means allows
Va(i+1), Vr(i+1) as Va(i+1)=@
bi@Va(i)+bi/2(Va(i)+Vr(i)
) and Vr(i+1)=bi/2(Va(i)+Vr(
8. The digital-to-analog conversion circuit according to claim 7, wherein: i))+@bi@Vr(i) (where @bi@ represents the negation of bi). 10, Va(i), Vr(i), Va(i)+Vr(i
10. The digital-to-analog conversion circuit according to claim 9, characterized in that three voltage holding means are provided for holding each of the voltages .)/2. 11, Va(i), Vr(i) and Va(i) or Vr
10. The digital-to-analog conversion circuit according to claim 9, further comprising three voltage holding means for holding either one of (i), respectively. 12, 2(n-1) to hold (n-1) sets of Va(i) and Vr(i) corresponding to i=1 to (n-1)
8. The digital-to-analog converter circuit according to claim 7, further comprising two voltage holding means.