JPH01158814A - High speed signal processor - Google Patents

Abstract

PURPOSE:To attain round-off without using any externally mounted adder by giving a high-order M-bit in N-bits of the result of product sum operation to an adder in the processor and using a data of the (M+1)th bit from the most significant bit as a carry input of the said adder. CONSTITUTION:A path from a register RB latching a filter output to an adder 2 is provided in a processor in which, e. g., 15 bits are used for the internal arithmetic processing and RB[14-7] being high-order 8 bits from the register RB are given to a register RD 1, from which they are given to an adder 2. Moreover, the bit RB[6] to be subject to round-off is given to a carry of the adder 2 receiving the RB[15-7] to truncate the low-order RB[5-0]. The 8-bit output subject to round-off is obtained as an output from an output register RO, then the round-off processing is attained without any externally mounted circuit and any excess increase in the program steps.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to digital signal processing devices and the like, and particularly to an internal rounding processing circuit of a product-sum calculation circuit.

[Conventional technology]

The signal processing circuit in Figure 3 is a linear phase FER shown in Figure 2.
(Fini Impulse Response: (Fini
fe Impulse R55ponse) filter. Since the group delay of this filter does not depend on frequency, it exhibits favorable characteristics in image signal filtering, and is used in many video signal processing devices. Here, the input signal IN is multiplied by the filter coefficient Ci, and the result is added to the output of each delay circuit Di and delivered to the next stage delay circuit Di+1. By the way, the multiplier
The circuit scale of the adder is large, and it is difficult to integrate this many circuits. Therefore, the patent application No. 61-142998
As shown in FIG. 3, the above filter is realized by the signal processing circuit shown in FIG. Its function will be explained using FIG. 3 and Table 1 showing its program.

First, data is input to register RIN, and filter coefficient CO is input to register RC. Program step 2
The product of RIN and RC is latched in register RM, 0 is latched in register RDI, and the contents of accumulator D4 are latched in register RD2. In step 3, the sum of RM and RDI is input to the accumulator DO, and the output register R
The sum of RM and RD2 is input to O. Following the above processing, in a pipeline manner, filter coefficient 01 is input to register RC in step 2, and RI is input to RM in step 3.
The product of M and RC is input, and DO1 is input to RDI, and D3 is input to RD2. In the next step, RM and RDI to Dl
The sum of RM and RD2 is input to D4. Furthermore, following the above processing, the filter coefficient C2 is input to RC in step 3 in a pipeline manner, the product of RIN and RC is input to RM in the next step, and Dl is input to RDI.
, D2 is input to RD2. In the next step, the sum of RM and RDI is input to D2, and the sum of RM and RD2 is input to D3.

Eight bits (two's complement) are used as data for the video signal. By the way, the above product-sum calculation result is obtained with 15 bits. This is because the result of multiplying 8 bits by 8 bits becomes 15 bits. However, after the above filtering, the word width of the output signal must be returned to the original 8 bits. If only the lower 7 bits of the 15 bits are rounded down to 8 bits, a large error will occur.

This will be explained using FIG. Here, the horizontal axis shows the input (15 bits) to the data conversion (conversion from 15 bits to 8 bits data) circuit, and the vertical axis shows the converted output (8 bits). The original signal quantized to 15 bits is a highly accurate signal as shown in FIG. However,
The conversion characteristic obtained by simply truncating the lower 7 bits becomes as shown by the broken line 4 shown in FIG. 4, which results in an error of up to 128 steps compared to the original signal when converted to 15 bits. This is 128/2
This corresponds to an error of 1/2g=1/256.

This is an ILSB error for 8-bit data and cannot be tolerated. Therefore, when converting 15 bits to 8 bits, it is necessary to round off the 7th bit from the LSB. The conversion characteristics at this time are as shown in FIG. 4, and the maximum error from the original signal is 64 steps. This corresponds to an error of 1/29=11512, which is an error of 1/2 LSB for 8-bit data.

Rounding is achieved by adding the data of the 7th bit from the LSB starting from the lowest of the upper 8 bits of data.

[Problem that the invention seeks to solve]

Conventionally, in the case of high-speed signal processing processors, rounding has been performed using an external circuit, requiring an external adder. Furthermore, when processing is performed using an adder inside the processor, a problem arises in that the speed of arithmetic processing decreases.

An object of the present invention is to perform rounding in a high-speed signal processing processor using an adder inside the processor without using an adder that is conventionally attached externally, and without reducing the arithmetic processing speed.

[Means for solving problems]

In order to solve the above problem, as shown in FIG. 1, a path is created to input the filter output RB inside the processor to the adder inside the processor once again. At this time, the output of RB is 15 bits and the output of output register RC is 8 bits. The upper 8 bits of the RB small output are input to RDI, bit 6 is input to the carry input of the adder, and the lower bits 0 to 5 are discarded. Conventionally, in the calculation program shown in Table 1, when DO=RD1+RM in step 3,
Since RD1=O, there is virtually no need to use an adder. Therefore, if the value of register RM is input directly to accumulator DO and the free adder is used in step 3 to add RB (6) and RB [15 to 7], no external circuit is required. Rounding can be done without adding extra program steps.

〔Example〕

As shown in FIG. 1, consider a processor whose internal arithmetic processing is 15 bits. First, a path is provided from register RB, where the filter output is latched, to the adder. The upper 8 bits from register RB, RB (15 to 7), are input to register RDI to be input to the adder in the processor. Also, the bit RB [6] to be rounded off is input to R
Input B (15 to 7) to the carry of the adder,
The lower RB (5 to 0) is rounded down. By performing such arithmetic processing, a rounded 8-bit output is obtained from the output register RO.

Table 2 shows the calculation program at this time. First, data is input to register RIN, and filter coefficient CO is input to register RC. In step 2, the product of RIN and RC is directly input to the multiplication result register RM, RB (6) is input to the carry register CIN, and RB (14 to 7
], the contents D4 of the accumulator are input to the register RD2.

In step 3, RM to accumulator DO and RDI to RO
and CIN are input, and the sum of RM and RD2 is input to RB. Following the above processing, in a pipeline,
In step 2, filter coefficient 01 is input to RC, in step 3, the product of RIN and RC is input to RM, O to CIN, DO1 to RD1, accumulator content D3 to RD2.
is input. In the next step, R to accumulator D1.
The sum of M, RDI and CIN is input, and RM and RD are input to D4.
The sum of 2 is input. Furthermore, following the above processing, filter coefficient 02 is input to RC in step 3 in a pipeline, the sum of RIN and RC is input to RM in the next step, 0 is input to CIN, Dl is input to RDI, and D2 is input to RD2. be done. In the next step, the sum of RM, RDI, and CIN is input to D2, and the sum of RM and RD2 is input to D3.

With the above calculation program, rounding can be performed without reducing the calculation processing speed.

〔Effect of the invention〕

According to the present invention, when performing rounding processing on output data in a high-speed signal processing processor, it is not necessary to provide a rounding processing circuit using an adder as an external circuit, and the processing can be performed without increasing the number of steps in the calculation program. Therefore, there is an effect that the overall circuit scale does not increase and the arithmetic processing speed does not decrease.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the internal configuration of a processor that is an embodiment of the present invention, FIG. 2 is a signal flow diagram of a linear phase FIR filter, FIG. 3 is a block diagram showing the internal configuration of a conventional processor, and FIG. The figure is an input/output characteristic diagram comparing the outputs when the input signal is rounded off and when the input signal is rounded down. 1... Multiplier, 2... Adder, 3... External adder, 4... Output when lower 7 bits are truncated, 5
... Output when bit 6 is rounded off, 6... Original signal (input signal). 1st opening N 2nd RO 3rd area N 60-cho 3 Extension lip of outer material 11

Claims (1)

[Claims] 1. In a high-speed signal processor that consists of a multiplier, an adder, a control circuit, and a register, and outputs only M bits of the N bits of the product-sum operation result to the outside, the upper M bits of the N bits of the product-sum operation result are internally output to the processor. A high-speed signal processing processor, characterized in that data input to an adder and the M+1th bit from the most significant bit is used as a carry input of the adder, and an addition output of the adder is used as a processor output.