JPH01156878A - Pattern matching circuit - Google Patents

Abstract

PURPOSE:To perform matching processes among plural patterns by setting latches containing clearing functions and controlled by the output of a ROM at a position before central value circuits. CONSTITUTION:Subtractors 21-27 and the central value circuits 31-37 are used together with the latch circuits 51-57 containing clearing functions set between said circuits 31-37 and the subtractors 21-27, a minimum value area detecting circuit 41, a pattern selection ROM 61 serving as a pattern control circuit which decides and controls patterns after applying clear signals to the circuits 51-57, and a multiplexer 42. The circuits 51-57 which are controlled by the output of the ROM 61 are set before the circuits 31-37. Thus a pattern matching pattern can be varied into plural pieces. In other words, the matching processes are carried out among plural patterns.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a pattern matching circuit used for image recognition and the like.

BACKGROUND OF THE INVENTION In recent years, image processing technology has been applied to many fields, and among these, pattern matching technology for image recognition has come to be widely used in order to improve the quality of ICs and reduce their prices.

Hereinafter, a conventional pattern matching circuit will be explained with reference to the drawings. FIG. 4 is a block diagram showing the configuration number of a conventional pattern matching circuit. In Fig. 4, 21 to 27 are pattern matching current signal group "04".
This is a subtracter that subtracts corresponding signals of the signal groups b01 to bo7 obtained by dividing the pattern matching reference signal group "03" into blocks of the same size as the current signal group "04" to pixel quantiles. 31 to 37 are median value circuits that use the central value of the differences within each block as a representative value. 41 is a minimum value/part detection circuit that outputs a code '01 representing a reference signal group that has produced the minimum value "18" from the output values of the median value circuits 31 to 37; 42 is center data d22 of the reference signal group; This is a multiplexer that selects the value of the region detection signal c01 and the output data a.7 from the inputs of ~d28.

The operation of the pattern matching circuit configured as described above will be explained below.

First, the current signal group a O4 for pattern matching is 3×3
The nine pixel signals obtained with each pixel as one block are
The pattern matching reference signal group a is configured as two signal groups. 3 has a configuration of 3×7 pixels when the pattern matching range is ±3 pixels in the horizontal direction, and is divided into seven reference signal groups b01 to b07. Input signal a. 4
In order to compare with the reference signal groups b01 to b07, subtractors 21 to 27 perform subtraction between corresponding pixels, respectively. Outputs b1. of subtractors 21-27. ~b, 7, the median value of intra-block differences is determined by median value circuits 31 to 37 for each signal group. Since the signal group that takes the minimum value in the median value data is a matched signal group, the median value data b21
~b2□ is the minimum value, which is input to the part detection circuit 41, and the minimum value a18 and the code C01 representing the signal group that is the source of the minimum value are output. The multiplexer 42 outputs a group of reference signals. ,~b. 7 center data d22 to d28 are input, data of a signal group matched from the value of code C81 is selected and output as ao7.

Problems to be Solved by the Invention However, with the above configuration, matching processing can only be performed in the form of one fixed signal group, and it is not suitable for matching processing with many types of patterns. .

SUMMARY OF THE INVENTION In view of the above problems, it is an object of the present invention to provide a pattern matching circuit that can perform matching processing using a plurality of patterns.

Means for Solving the Problem ゛In order to achieve this object, the pattern matching circuit of the present invention includes a subtracter that takes the difference between an image signal group obtained by image recognition and a reference signal group, and a reference pattern. It consists of a latch circuit whose output is controlled by a clear signal applied from a control circuit, and a median circuit that calculates the median value of the difference output from the output of the latch circuit.

Function: With this configuration, matching processing can be performed using a plurality of patterns using a combination of a reference pattern control circuit and a latch having a clearing function.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a pattern matching circuit in one embodiment of the present invention. Components similar to those shown in FIG. 4 are designated by the same reference numerals, and detailed explanation thereof will be omitted. In Figure 1, 21~
27 is a subtracter, 31 to 37 are median value circuits, 61 to 67 are latch circuits with a clear function inserted between each subtractor 21 to 27 and median value circuits 31 to 37, and 41 is a minimum value/part detection The circuit 61 is a pattern control circuit which applies a clear signal to the latch circuits 61 to 67 and determines and controls patterns, and the pattern selection ROM 142 is a multiplexer.

FIG. 2 shows the subtracter 21 in FIG. Latch 61°RO
It is a detailed diagram of Mel. In order to make the configuration easier to understand, the explanation will be based on the assumption that the input to ROMel that determines the pattern of the clear signal is 1 bit, and that there are two types of patterns.

The operation of the pattern matching circuit configured as described above will be explained below.

First, recognized image signal group a04. Reference signal group b01 to bo
7 is input to subtracters 21 to 27 as a signal group, and subtraction processing is performed for each image signal obtained from each pixel for all data, and outputs b11 to b1□ are obtained.

Since the processing for each block is common, the subtracter 21 and the latch 61. The median circuit 31 will be explained.

The latch 61 with clear function outputs data when the clear signal from ROMcz is o'', and outputs 1 when the clear signal is 1''.
0'' output. Output b111 of subtractors 211 to 219
- If you want to pattern match all of b119, use RO
Mel output (clear signal) 021. All 29 @
0". In other words, input signal e to ROMel
. Then, o'' is applied as shown in the table. At this time, all of the clear signals 0021 to e029 become 0'', and the pattern to be matched becomes the pattern shown in FIG. 3(a).

Next, when performing pattern matching using the pattern shown in Figure 3Cb), select e in the table. It is sufficient to use the outputs e021 to e029 of the ROM 61 when 1 is "Ill".

As shown in the table, according to this embodiment, the median circuits 31 to 37
By using latches 61 to 67 with a clear function controlled by the output of ROMel before the pattern matching, a plurality of patterns, here two types, can be used for pattern matching.

In this embodiment, the basic reference data group is 3×3 and the number of patterns is 2 types, but by increasing the number of bits of the input e01 of the ROM 61, the basic reference data group can be expanded and the number of patterns can be increased in the same way. is possible.

Effects of the Invention As described above, the present invention can perform matching processing with a plurality of patterns by adding a pattern control circuit and a latch circuit with a clear function, and has great practical effects.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a pattern matching circuit according to an embodiment of the present invention, FIG. 2 is a detailed block diagram of the pattern matching circuit shown in FIG. 1, and FIGS.
b) is a front view of a screen for explaining a matching pattern based on a ROM output code, and FIG. 4 is a block diagram of a conventional pattern matching circuit. 21-27...Subtractor, 61-67...
- Latch with clear function, 31 to 37... Median value circuit, 41... Minimum value 1 part detection circuit, 42.
...Multiplexer circuit, 61...RO
M0 Name of agent Patent attorney Toshio Nakao and 1 other person
Figure 3 ((IJ (b) Figure 4

Claims (1)

[Claims] a plurality of subtracters that input a group of recognized image signals and a group of reference signals and take a difference for each image signal obtained for each pixel; and a plurality of subtracters that receive the output of the subtracters and whose output pattern is controlled by a clear signal. a latch circuit, a median value circuit which inputs the output of the latch circuit and calculates the median value of the difference output; a minimum value/part detection circuit which inputs the output of the median value circuit and calculates the minimum value among the inputs; 1. A pattern matching circuit comprising: a multiplexer inputting a minimum value, an output of the part detection circuit, and center data of the reference signal group and selecting data of the matched signal group.