CN114897747A - 1-2 order fractional order differential filter of digital image - Google Patents

1-2 order fractional order differential filter of digital image Download PDF

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CN114897747A
CN114897747A CN202210430917.XA CN202210430917A CN114897747A CN 114897747 A CN114897747 A CN 114897747A CN 202210430917 A CN202210430917 A CN 202210430917A CN 114897747 A CN114897747 A CN 114897747A
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fractional order
order differential
image
fractional
digital image
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肖利芳
金大聪
罗茗洋
吴云韬
张俊
徐国平
段梅
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Wuhan Institute of Technology
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T5/00—Image enhancement or restoration
    • G06T5/20—Image enhancement or restoration using local operators
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T3/00—Geometric image transformations in the plane of the image
    • G06T3/40—Scaling of whole images or parts thereof, e.g. expanding or contracting
    • G06T3/4038—Image mosaicing, e.g. composing plane images from plane sub-images
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T5/00—Image enhancement or restoration
    • G06T5/70—Denoising; Smoothing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/02—Frequency selective networks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T2200/00—Indexing scheme for image data processing or generation, in general
    • G06T2200/32—Indexing scheme for image data processing or generation, in general involving image mosaicing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T2207/00—Indexing scheme for image analysis or image enhancement
    • G06T2207/10—Image acquisition modality
    • G06T2207/10016—Video; Image sequence
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T2207/00—Indexing scheme for image analysis or image enhancement
    • G06T2207/10—Image acquisition modality
    • G06T2207/10024—Color image
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T2207/00—Indexing scheme for image analysis or image enhancement
    • G06T2207/20—Special algorithmic details
    • G06T2207/20024—Filtering details

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Abstract

The invention discloses a 1-2 order fractional order differential filter of a digital image, wherein a serial digital video code stream is divided into 3 paths after being input into the fractional order differential filter: the 1 st path sequentially passes through a time sequence control circuit, a read-write address generator, a double-port RAM group and a latch/shift circuit group, is processed by a 1 st to 8 th fractional order differential mask convolution algorithm unit circuit, respectively outputs the approximate values of fractional order partial differentials of the point in 8 directions, and outputs the maximum value thereof as the approximate value of the fractional order differential of the point after being processed by a maximum value comparator; the 2 nd path triggers the time sequence control circuit to generate a corresponding time sequence control signal; the 3 rd path is fed into the latch/shift circuit group together with the output of the dual port RAM group to generate the pixel array. The invention can solve the problem that the first-order image enhancement template can generate wide edges when processing images and the second-order template can simultaneously enhance textures and noise, and has unique advantages and good effect on images with relatively important significance of texture information.

Description

1-2 order fractional order differential filter of digital image
Technical Field
The invention relates to the field of computer digital image processing, in particular to a 1-2 order fractional order differential filter for a digital image.
Background
With the development of scientific technology, the technical requirements of people on digital image processing are higher and higher, and image enhancement as an important part of image processing plays a very important role in modern life. The current image enhancement method is mainly differential mask operation based on integral order differential, and comprises a Sobel operator based on first order differential, a Roberts operator, a Prewitt operator and a Laplacian operator based on second order differential. Integer order differentiation has the following disadvantages: first order differential processing typically produces wider edges; the second order differential processing is strongly responsive to details, including texture and noise portions, and produces a double response to gray scale step changes.
Disclosure of Invention
The invention aims to solve the technical problem of providing a fractional order differential mask based on Riemann-Liouville definition aiming at the side effect generated by an integer order differential template in the prior art, and constructing a 1-2 order fractional order differential filter of a digital image based on the definition.
The technical scheme adopted by the invention for solving the technical problems is as follows:
the invention provides a 1-2 order fractional order differential filter of a digital image, which comprises: the device comprises a 1 st to 8 th fractional order differential mask convolution algorithm unit circuit, a time sequence control circuit, a read-write address generator, a double-port RAM group, a latch/shift circuit group and a maximum comparator; wherein:
serial digital video code stream S x (K) After being input into the fractional order differential filterThe method is divided into 3 paths:
the 1 st path sequentially passes through the time sequence control circuit, the read-write address generator, the double-port RAM group and the latch/shift circuit group, is processed by the 1 st to 8 th fractional order differential mask convolution algorithm unit circuits in parallel, and respectively outputs a pixel S x The approximate value of the v-order fractional partial differential of (K + (n-1) (H +1)) in 8 directions is processed by the maximum value comparator, and the maximum value of the 8 approximate values is output as S x Approximation of the v fractional order differential of (K + (n-1) (H +1))
Figure BDA0003610442500000021
The 2 nd path triggers the time sequence control circuit to generate a corresponding time sequence control signal;
the 3 rd path is fed into the latch/shift circuit group together with the output of the dual-port RAM group to generate a pixel array of (2n +1) × (2n + 1);
wherein: h denotes the width of the original image, S x (K) Representing pixels in a serial digital video code, K representing pixel S x (K) Pixel number in serial digital video code, v denotes the order of fractional order filter, n denotes a self-defined integer and requires v-n<0。
Furthermore, the timing control circuit of the present invention generates the corresponding timing control signals required for controlling the operations of the read-write address generator, the dual-port RAM bank, the latch/shift circuit bank, the 1 st to 8 th fractional differential mask convolution algorithm unit circuits and the maximum comparator under the triggering of the row and column valid signals of the input digital video stream;
the read-write address generator generates read-write addresses of the double-port RAM group under the action of a time sequence control signal and is responsible for processing initialization and rotation of the read-write addresses; according to the input characteristics of serial digital video code streams and the properties of digital images, the input of a 1-2 order fractional order differential filter of the digital images is divided into 2 types: the first is that when processing digital gray image, the input of the fractional order differential filter is the gray value of the digital image; the second is when processing the digital color image, the input of the said fractional order differential filter is I component value of digital image HSI space;
the dual-port RAM group adopts 2n line memories to complete the acquisition of 2n +1 lines of video image data.
Furthermore, the latch/shift circuit group of the invention adopts 3n in common 2 +3n D triggers, generating (2n +1) × (2n +1) pixel array required for calculating digital image fractional order differential by carrying out point delay on the digital image; the 1 st row of the pixel array adopts 2n D triggers, the 2 nd row adopts 2 n-1D triggers, the n +1 th row adopts n + 1D triggers until the nth row, the n +1 th row adopts n + 1D triggers, the n +2 th row adopts n + 2D triggers until the 2n +1 row adopts 2n D triggers.
Further, the maximum comparator of the present invention calculates a maximum value among circuit output values of 1 st to 8 th fractional order differential mask convolution algorithm units of the fractional order differential mask convolution circuit; the inputs and outputs of the maximum comparator are classified into 2 types according to different properties of processed digital images: the first one is that when processing digital gray image, the maximum comparator has 8 inputs and 1 output, which are fed into the gray values of the 1 st to 8 th fractional order differential mask convolution arithmetic unit circuit, respectively, and outputs the maximum value of 8 fed-in gray values; in a second case, when processing a digital color image, said maximum comparator has 8 inputs and 1 output, and outputs the maximum value among the 8 input I component values, which are fed to the I component values in the HSI space of said 1 st to 8 th fractional order differential mask convolution algorithm unit circuits, respectively.
Furthermore, the 1 st to 8 th fractional order differential mask convolution algorithm unit circuits are the core of the 1-2 order fractional order differential filter of the digital image, and the key points of the convolution algorithm unit circuits are that fractional order differential masks are constructed in 8 symmetrical directions of an x positive direction, an x negative direction, a y positive and negative direction, a y negative direction, an upper left diagonal line, an upper right diagonal line, a lower left diagonal line and a lower right diagonal line respectively; determining a fractional order gradient of the digital image by a modulus of an 8-dimensional fractional order gradient column vector constructed by v-order fractional partial differentiation in 8 directions; the construction formula of the fractional order differential mask is as follows:
Figure BDA0003610442500000031
wherein the value of the order v is between 1 and 2; when the processed digital image is a gray image, directly performing convolution processing on the fractional order differential mask and the original image; when the processed digital image is a color image, since R, G, B components of the RGB space are not orthogonal, the color image is processed using the HSI space; firstly, converting a color image into an HSI space, then independently extracting an I component of the image, performing convolution processing on the I component and a fractional differential mask according to the method, and then converting the processed I component and the original H and S components into an RGB space.
The invention provides a method for denoising a picture by adopting a 1-2 order fractional order differential filter of a digital image, which comprises the following steps:
step 1, serially inputting pixel gray values of an original gray image into a 1-2 order fractional order differential filter of a digital image, firstly converting the gray image into a 255 multiplied by 255 matrix, and sequentially and serially inputting the pixel gray values of corresponding positions into the 1-2 order fractional order differential filter of the digital image;
step 2, the pixel gray value enters a key part of the filter after passing through a time sequence control circuit, a read-write address generator, a double-port RAM group and a latch/shift circuit group, namely a fractional order differential mask convolution algorithm unit circuit in eight directions; each direction is compared to the mask formula:
Figure BDA0003610442500000041
carrying out convolution processing on the generated fractional order differential operator;
step 3, the pixel gray value after the operation processing enters a maximum comparator, and the maximum comparator outputs the maximum value in the eight directions as a new pixel gray value at the position;
and 4, splicing the processed pixel gray values into a new gray image through an algorithm again.
The invention has the following beneficial effects: according to the 1-2 order fractional order differential filter of the digital image, firstly, a fractional order differential mask is constructed through fractional order differential definition proposed by Riemann-Liouville, and a serial digital video code stream is formed by the digital image to be processed in a mode that one row of pixels is connected with one row of pixels. If the image is a gray image, the image is directly input into a fractional order filter, and then pixels processed by the filter are sequentially spliced into a new image; if the image is a color image, firstly converting the color image into an HSI space, then independently extracting an I component of the image, processing the I component according to the method, and then converting the processed I component into an RGB space together with the original H and S components. The filter can solve the problem that a first-order image enhancement template can generate wide edges when processing images and a second-order template can simultaneously enhance textures and noise. Not only can the low-frequency contour information of the smooth area be reserved, but also the texture information of high-frequency edges and high frequencies in the image can be enhanced in a nonlinear mode. The method has unique advantages and good effects for the image with relatively important meaning of the texture information.
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The invention will be further described with reference to the accompanying drawings and examples, in which:
FIG. 1 is a structural diagram of a 1-2 order fractional order filter of a digital image according to an embodiment of the invention;
FIG. 2 is an overall flow chart of denoising of a digital image by a 1-2 order fractional order filter according to an embodiment of the present invention;
FIG. 3 is an original sample image of a 1-2 order fractional order filter of a digital image according to an embodiment of the present invention;
FIG. 4 is a structural diagram of a fractional order differential mask convolution algorithm unit circuit of a digital image 1-2 order fractional order filter according to an embodiment of the present invention.
FIG. 5 is a new gray scale graph of a digital image 1-2 order fractional order filter after the filter denoising process according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
As shown in FIG. 1, the image denoising method through the 1-2 order fractional order filter of the digital image according to the embodiment of the invention includes the following steps:
the serial digital video code stream is divided into 3 paths after being input into a fractional order differential filter: the 1 st path sequentially passes through a time sequence control circuit, a read-write address generator, a double-port RAM group and a latch/shift circuit group, is processed by a 1 st to 8 th fractional order differential mask convolution algorithm unit circuit, respectively outputs the approximate values of fractional order partial differentials of the point in 8 directions, and outputs the maximum value thereof as the approximate value of the fractional order differential of the point after being processed by a maximum value comparator; the 2 nd path triggers the time sequence control circuit to generate a corresponding time sequence control signal; the 3 rd path is fed into the latch/shift circuit group together with the output of the dual port RAM group to generate the pixel array.
As shown in fig. 2, the specific implementation process of the 1-2 order fractional order filter for the digital image according to the embodiment of the present invention includes:
the pixel gray value of the gray image is serially input into a digital filter, after the gray image of the previous step is obtained, the gray image is directly split and can only be serially and sequentially input into a fractional order differential digital filter due to picture code stream;
the pixel gray value is subjected to mask operation in eight directions, and is input into a maximum value comparator after being subjected to fractional order differential operator operation in eight directions of an x positive direction, an x negative direction, a y positive direction, a y negative direction, an upper left diagonal, an upper right diagonal, a lower left diagonal and a lower right diagonal respectively;
the maximum comparator outputs the processed maximum value, the maximum comparator respectively compares the pixel gray values which are subjected to fractional order differential operator operation in eight directions, and the maximum value is output as a result;
recombining the processed pixel gray values into a new gray image, and realizing the specification of splicing and restoring the serial pixel gray values into an original image by utilizing circulation after the output of the maximum comparator is obtained;
as shown in FIG. 3, in another embodiment of the present invention, the denoising with a 1-2 order fractional order filter of a digital image comprises the following steps:
1. the pixel gray value of an original gray image is serially input into a 1-2 order fractional order filter of a digital image, the gray image is firstly converted into a 255 multiplied by 255 matrix, each number is the pixel gray value of a corresponding position, and then the pixel gray values are sequentially and serially input into the 1-2 order fractional order filter of the digital image.
2. The pixel gray value enters the key part of the filter, namely a fractional order differential mask convolution algorithm unit circuit in eight directions after passing through a time sequence control circuit, a read-write address generator, a double-port RAM group and a latch/shift circuit group. Each direction is compared to the mask formula:
Figure BDA0003610442500000071
the generated fractional order differential operator is used for convolution processing, and fig. 4 is a structural diagram of a fractional order differential mask convolution algorithm unit circuit.
3. The pixel gray value after the operation processing enters a maximum comparator, and the maximum comparator outputs the maximum value in the eight directions as a new pixel gray value at the position.
4. And splicing the processed pixel gray values into a new gray map through an algorithm again, as shown in fig. 5.
It will be understood that modifications and variations can be made by persons skilled in the art in light of the above teachings and all such modifications and variations are intended to be included within the scope of the invention as defined in the appended claims.

Claims (6)

1. A1-2 order fractional order differential filter for a digital image, the fractional order differential filter comprising: the device comprises a 1 st to 8 th fractional order differential mask convolution algorithm unit circuit, a time sequence control circuit, a read-write address generator, a double-port RAM group, a latch/shift circuit group and a maximum comparator; wherein:
serial digital video code stream S x (K) After being input into the fractional order differential filter, the filter is divided into 3 paths:
the 1 st path sequentially passes through the time sequence control circuit, the read-write address generator, the double-port RAM group and the latch/shift circuit group, is processed by the 1 st to 8 th fractional order differential mask convolution algorithm unit circuits in parallel, and respectively outputs a pixel S x The approximate value of v order fractional order partial differential of (K + (n-1) (H +1)) in 8 directions is processed by the maximum value comparator, and the maximum value of the 8 approximate values is output as S x Approximation of the v fractional order differential of (K + (n-1) (H +1))
Figure FDA0003610442490000011
The 2 nd path triggers the time sequence control circuit to generate a corresponding time sequence control signal;
the 3 rd path is fed into the latch/shift circuit group together with the output of the dual-port RAM group to generate a pixel array of (2n +1) × (2n + 1);
wherein: h denotes the width of the original image, S x (K) Representing pixels in a serial digital video code, K representing pixel S x (K) Pixel number in serial digital video code, v denotes the order of fractional order filter, n denotes a self-defined integer and requires v-n<0。
2. The 1-2 order fractional order differential filter of digital image according to claim 1, wherein the timing control circuit generates the corresponding timing control signals required for controlling the operation of the read-write address generator, the dual-port RAM group, the latch/shift circuit group, the 1-8 order fractional order differential mask convolution algorithm unit circuit and the maximum comparator under the trigger of the row and column effective signals of the input digital video stream;
the read-write address generator generates read-write addresses of the dual-port RAM group under the action of a time sequence control signal and is responsible for processing initialization and rotation of the read-write addresses; according to the input characteristics of serial digital video code streams and the properties of digital images, the input of a 1-2 order fractional order differential filter of the digital images is divided into 2 types: the first is that when processing digital gray image, the input of the fractional order differential filter is the gray value of the digital image; the second is when processing the digital color image, the input of the said fractional order differential filter is I component value of digital image HSI space;
the dual-port RAM group adopts 2n line memories to complete the acquisition of 2n +1 lines of video image data.
3. The digital image 1-2 fractional order differential filter of claim 1, wherein the latch/shift circuit set uses 3n total 2 +3n D triggers, generating (2n +1) × (2n +1) pixel array required for calculating digital image fractional order differential by carrying out point delay on the digital image; the 1 st row of the pixel array adopts 2n D triggers, the 2 nd row adopts 2 n-1D triggers, the n +1 th row adopts n + 1D triggers till the nth row, the n +1 th row adopts n + 1D triggers, the n +2 th row adopts n + 2D triggers till the 2n +1 row adopts 2n D triggers.
4. The 1-2 order fractional order differential filter of a digital image according to claim 1, wherein said maximum comparator calculates a maximum value among output values of 1 st to 8 th fractional order differential mask convolution algorithm unit circuits of said fractional order differential mask convolution circuit; the inputs and outputs of the maximum comparator are classified into 2 types according to different properties of processed digital images: the first one is that when processing digital gray image, the maximum comparator has 8 inputs and 1 output, which are fed into the gray values of the 1 st to 8 th fractional order differential mask convolution arithmetic unit circuit, respectively, and outputs the maximum value of 8 fed-in gray values; in a second type when processing a digital color image, said maximum value comparator has 8 inputs and 1 output, which are fed to the I component values in the HSI space of said 1 st to 8 th fractional order differential mask convolution algorithm unit circuit, respectively, and outputs the maximum value among the 8 fed-in I component values.
5. The 1-2 order fractional order differential filter of the digital image according to claim 4, characterized in that the 1-8 order fractional order differential mask convolution algorithm unit circuit is the core of the 1-2 order fractional order differential filter of the digital image, and the key is to construct fractional order differential masks in 8 symmetrical directions of x positive direction, x negative direction, y positive and negative direction, y negative direction, left upper diagonal, right upper diagonal, left lower diagonal and right lower diagonal respectively; determining a fractional order gradient of the digital image by a modulus of an 8-dimensional fractional order gradient column vector constructed by v-order fractional partial differentiation in 8 directions; the construction formula of the fractional order differential mask is as follows:
Figure FDA0003610442490000031
wherein the value of the order v is between 1 and 2; when the processed digital image is a gray image, directly performing convolution processing on the fractional order differential mask and the original image; when the processed digital image is a color image, since R, G, B components of the RGB space are not orthogonal, the color image is processed using the HSI space; firstly, converting the color image into HSI space, then separately extracting I component of the image, and making convolution treatment with fractional differential mask according to the above-mentioned method, then converting the treated I component together with original H and S components into RGB space.
6. A method for denoising a picture using the 1-2 order fractional order differential filter of the digital image of claim 1, comprising the steps of:
step 1, serially inputting pixel gray values of an original gray image into a 1-2 order fractional order differential filter of a digital image, firstly converting the gray image into a 255 x 255 matrix, and sequentially and serially inputting the pixel gray values of each digit at corresponding positions into the 1-2 order fractional order differential filter of the digital image;
step 2, the pixel gray value enters a key part of the filter after passing through a time sequence control circuit, a read-write address generator, a double-port RAM group and a latch/shift circuit group, namely a fractional order differential mask convolution algorithm unit circuit in eight directions; each direction is compared to the mask formula:
Figure FDA0003610442490000041
carrying out convolution processing on the generated fractional order differential operator;
step 3, the pixel gray value after the operation processing enters a maximum comparator, and the maximum comparator outputs the maximum value in the eight directions as a new pixel gray value at the position;
and 4, splicing the processed pixel gray values into a new gray image through an algorithm again.
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