JPH01156844A - Storage control system - Google Patents

Abstract

PURPOSE:To execute a test and adjustment in a memory control system under the same conditions as a normal clock working state by varying the delay time of the control signal in response to the cycle of a 2nd clock in case all control signals required to set the read data at a read data register by means of the 2nd clock. CONSTITUTION:The optionally fixed timing signal which is produced with use of a free run clock FCLK for setting the read data at a read data register 21 can be shortened in response to the cycle of the clock FCLK. As a result, a reading cycle shortening circuit is always available and the action cycle time has no change to a memory element (RAM). Thus the test and the control are carried out under the same conditions as a normal clock working state.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Application Fields Prior Art and Problems to be Solved by the Invention Means for Solving the Problems Actions Embodiments Effects of the Invention [Summary] Random Access Memory Elements The address and chip select signal given to the random access memory element (RAM) etc. are switched by a control signal controlled by a gated clock, and this control signal is used as a starting signal to read out the read data output from the random access memory element (RAM) etc. Set timing signal (read clock) to set in register
With regard to a read control method for a storage device that uses a method in which the clock is delayed and set using a free rank clock, a read control method is realized in which the operation of the storage device does not depend on the cycle of the clock when testing and adjusting the storage device. The address and chip select signals given to the memory element group (RAM) are switched by a control signal controlled by a first clock (gated clock), and the control signal is used as a starting signal to activate the memory element group (RAM). All the control signals necessary to set the read data to the read data register for the transmission time required for the read data (RAM-RD) output from RAM) to be set in the read data register. The second clock (free rank clock)
, the delayed control signal sets the read data in a read data register, and the output of the read data register is transmitted to a circuit that operates with the first clock. In this case, when all control signals necessary to set in the read data register are delayed using the second clock, the length of the delay time is made variable in accordance with the cycle of the second clock. Configure it as follows.

[Industrial application field]

The present invention switches the address and chip select signals given to a random access memory element (RAM) etc. using a control signal controlled by a gated clock, and uses this control signal as a starting signal to
The present invention relates to a read control method in a storage device that uses a method in which a set timing signal (read clock) is delayed by a free rank clock and set in order to set read data output from a memory device such as M) in a read data register.

2. Description of the Related Art With recent advances in semiconductor technology, memory elements constituting storage devices are becoming faster and faster.

On the other hand, as storage devices become larger, the time required to transmit a control signal from a control circuit to the memory element cannot be ignored, and various measures have been taken.

However, when testing and adjusting the storage device, the test and adjustment are performed by setting it to single clock mode or slowing down the clock itself, but the operation at this time is different from the normal clock. A read control method is required that does not

[Prior art and problems to be solved by the invention] FIG. 2 is a diagram showing an outline of a configuration example of a conventional storage device, and FIG. 3 is an operation time chart of the prior art.

In this figure, only one bit is shown for convenience of explanation.

First, the address (ADD) and chip select signal (block) are sent to the address register (ADD-REG) 31. After passing through the output cover sofa from chip select register (C5-RUG) 32, passing through a long printed circuit board wiring, and passing through the large power buffer of array card 1 or level converter, etc., the data is transferred to memory element (RAM) 11.
ADD, input as RAM-C5.

When an address is input to the memory element (RAM) 11, read data (RAM-RD) is output from the memory element (RAM) 11 after the access time of the memory element (RAM) 11 has passed, and is sent to the array card. After being output to the outside of 1 and being dot-ORed with another array card 1, it is passed through a long printed circuit board wiring again to a highly integrated readout circuit (on which a readout data register (RD-REG) 21 is mounted). The read data register (RD-REG)
21.

The delay on the bus through which data passes is so large that it cannot be overlooked.

The operation at this time is explained using the time chart in Figure 3.
The first clock (CLOCK) is output and the address register (ADD-REG) 31. Dip select register (C5-REG) 32 becomes valid.

This output is delayed and enters array card 1, and the memory element (
RAM) Address for 11 (RAM-ADD)
, becomes the chip select signal (RAM-C5), and the output of the memory element (RAM) 11, RAM-RD, is
The output is delayed by the maximum access time (TAA), and is output to the outside of the array card 1.

This RAM-RD is transferred to the read data register (
RD-REG) 21 input (RD-REG-IN), r RCLK created by the 9th clock
The read data register (RD-RE
G) is set to 21.

Also, at the ninth clock, since the next access address is set in the address register (ADD-REG) 31, the memory element (1?) in the array card 1 is delayed in the same way as above. AM) 11 address input (RAM-ADD).

Output of the memory element (RAM) 11 (RAM-RD)
Under the worst condition, the above access time (T
It becomes effective at the maximum value of chip select signal (R
AM-C5) is cut out, the memory element (RAM)
The output of No. 11 becomes invalid after waiting for the minimum time (TLZ).

Therefore, from this time chart, read data is input to the read data register (RD-REG) 21 from the 9th clock to the 12th clock.
RD-REG-IN), it can be seen that it becomes effective by about 3τ.

However, in reality, the read data register (RD-R
EG) Since the time required to set the clock to 21 is just a short hold time after the clock is turned on, most of the above 3τ is wasted time.

As is clear from the above time chart, the time required for a read cycle (READ CYCLE) is 8τ in this memory element (RAM) 11, which is the access time of the memory element (RAM) 11 in use. (TAA)' was significantly larger than '.

In order to shorten this cycle time, the time to set the next access address should be changed from the 9th clock to
For example, it is sufficient to advance the read data register (RD-RE) by 3τ to the 6th clock.
G) There is almost no wasted time in the input timing to 21, and the processing capacity of the storage device can be improved.

However, when the entire system including this storage device operates in single-clock mode, the interval (period) between the clocks is large, so by doing the above, the sixth clock enters and the current cycle starts. address expires, the next access address enters, and by the time the 9th clock enters, the read data register (RD
-REG) 21 has a problem in that the data of the next access address is stored.

Therefore, the read data register (RD-REG) 2
They created a clock that entered 1 starting from the 6th clock, and devised a way to make it look like the 9th clock.

FIG. 4 is a diagram explaining the improved control method of the storage device, in which (a) and (b) show operation time charts, and (c) shows an example of a read clock (RD-CLK) generation circuit. It shows.

In this improved conventional storage device control method,
In the above-mentioned single clock mode, after the address register (ADD-REG) 31 is switched at the sixth clock, the read data register (RD-REG)
) Before the read data (RAM-RD) from the memory element (RAM) 11 at the input of 21 becomes invalid, the read data (RAM-RD) is taken into the read data register (RD-REG) 21. .

For this reason, a read clock (RCLK) for taking in read data (RAM-RD) is generated at a phase position corresponding to the ninth clock using the sixth clock as a trigger. □ Specifically, if the clock used during normal operation is called the normal clock, it has the same phase as this normal clock, and even when the system is in single-clock operation, it always operates at the same cycle as the normal clock. The read clock (RCLK) is generated using the free rank clock rFCLKJ.

In correspondence with this free rank lock r FCLK J,
The clock that is sporadically output during single clock operation will be referred to as gated clock rGCLKJ.

The gated clock rGCLKJ is normally used as the normal clock.

First, the activation signal (T
RiG), the above free run clock r FCLK J
Activate the shift register 22 that operates as follows.

For example, the activation signal (TRiG) generated by the sixth clock (see (c) in FIG. 4) is converted to 1τ by the free rank clock rFCLKJ, and is sent to the shift register 22 any number of times (in this example, , 3 times), even in single clock mode, a fixed timing of 1τ width (
SOUT 1) can be created.

Depending on this timing, the memory element (RAM) 11
If the read data (RAM-RD) is taken into the read data register (RD-R1!G) 21, and this output is controlled to be taken out using the read control signal (RD-OUT-CONT) generated by the gated clock rGCLKJ. good.

To explain in more detail using FIG. 4, rGCLKJ
is the gated clock, r FCLK J is the free rank clock, and (a), (
The operation time chart shown in b) shows the case in the single clock mode, and in the normal clock mode, the gated clock r GCLK J and the free run clock r FCLK J operate simultaneously and in the same cycle.

The address register (ADD-REG) 31 is switched at the 6th gated clock rGcLKJ, and at the same time, the activation signal (TRiG) of 1τ is output, and this signal remains '1' until the 7th gated clock rGCLKJ arrives. It has become.

This activation signal (TRiG) is used as a free rank clock rFC.
The data is input to the shift register 22 operating with LKJ, shifted by 3τ, and read data register (RD-
By using the gate signal to set the read data (R^l'1-RD) to REG) 21, the read data (RAM- RD) delayed data (R
D-REG-IN) and read the data register (RD-R
EG) Can be set to 21.

The output of the read data register (RD-REG) 21 is the RD-O signal generated by the clock at the 9th port, which is the normal timing of the gated clock rGCLKJ.
taken out by the UT-CONT signal and the same r GC
The 10th clock of LKJ is transferred to the next stage circuit using the gated clock rGCLKJ.

In the time charts showing the single clock mode in Figures (a) and (b), the read data register (R
D-REG) Read data (RD
It takes about 8τ until the above-mentioned RD-OUT-CONT signal is input to take out the RD-OUT-CONT signal (9
th clock timing) and functions to take out the output of the register.

In this way, even when in single clock mode.

Even in the normal clock mode, the start signal from the 6th gated clock rGcLKJ uses the free rank clock rFCLKJ to gain 3τ time, making the timing look like it was created by the 9th clock. Even in this method, which operated normally and was intended to shorten the cycle time of the read operation, there were the following drawbacks.

That is, in the above conventional method, the free rank clock r
A fixed time of 3τ is created using FCLK J, but this time is not absolute.

In other words, the fixing time of 3τ is influenced by the period of the free rank clock rFCLKJ itself.

Normally, a computer system has only one clock oscillator, which can be frequency-divided to create a clock with any period, a stop signal can be added to create a gated clock, or a raw clock can be used to create a gated clock. free rank lock r
Fishing on a boat is the best way to use FCLK J.

In testing during the development of a computer system using such a lock, the test is often performed at a clock cycle that is slower than the target clock cycle.

Furthermore, when operating with a target clock, the cycle of the clock may be slowed down in order to investigate a failure.

In these cases, a slower clock cycle means that the fixed time value of the circuit created using the above method becomes larger.

Depending on the target clock period, the free rank clock r
A fixed timing is created using FCLK J, and this timing signal is used to read data register (RD-RE).
G) Read data coming into input of 21 (RAM-
The attempt was made to import the data into the read data register (RD-REG) 21 before the data register (RD-REG) became invalid, but the basic free-rank clock [FCLKJ]
If the fixed timing becomes wider due to a change in the period of , the address register (ADD-
REG) 31. Chip select register (CS-RE
G) Read data register (1?) after 32 operates.
D-REG) Since the delay between 21 and 21 is absolute time,
As a result, the read data (RAM-RD) from the memory element (RAM) 11 is read out from the read data register (R
A problem arises in that the data cannot be correctly imported into the D-REG) 21.

Therefore, currently, when operating a computer system with a clock cycle other than the target clock cycle, the clock set in the address register (ADD-REG) 31 is used to store the read data (RAM-REG) in the read data register (RD-REG) 21. It was made the same as the read clock (RCLK) that sets the clock (RD), and was set as the ninth clock.

That is, at this time, the circuit for shortening the cycle time of the read operation described above (see FIG. 4(c)) is not used, and the test is performed in a state where the cycle time is long.

I was conducting an investigation.

For this reason, the cycle time of the read operation of the storage device on the computer system changes, resulting in a problem that the phenomenon does not necessarily match the actual situation.

In view of the above conventional drawbacks, the present invention switches the address and chip select signals given to a random access memory element (RAM) etc. using a control signal controlled by a gated clock, and uses this control signal as a starting signal to switch the address and chip select signal given to a random access memory element (RAM) etc. In a computer system that controls reading in a storage device using a method in which a set timing signal (read clock) is delayed and set by a free rank clock to set read data output from (RAM) etc. in a read data register. ,test.

It is an object of the present invention to provide a control method in which the operation process of a storage device does not differ from the normal operation even during adjustment.

[Means for solving problems]

The above problems are achieved by a storage device control method configured as follows.

The address and chip select signal given to the memory element group are switched by a control signal controlled by a first clock, and the read data output from the memory element group is set in the read data register using the control signal as an activation signal. All control signals necessary to set the read data in the read data register are delayed by the transmission time required for the read data register using a second clock, and the read data is read using the delayed control signals. In a storage device that uses a read method in which data is set in a data register and the output of the read data register is transmitted to a circuit that operates with the first clock, all of the data necessary to set the data in the read data register are When delaying the control signal using the second clock, the amount of delay time is configured to be variable in correspondence with the cycle of the second clock.

[Effect]

That is, according to the present invention, a random access memory device (
The address and chip select signal given to the random access memory element (RAM) etc. are switched by a control signal controlled by a gated clock, and using this control signal as a start signal, the read data output from the random access memory element (RAM) etc. is read out and sent to the data register. In a storage device that uses a method of delaying the set timing signal (read clock) with a free rank clock to set the read data to the read data register, Since the arbitrary fixed timing signal generated using the rank lock can be shortened according to the period of the free rank clock, a read cycle shortening circuit can be used at all times, and the memory element (RA
There is no change in the operation cycle time for M), and there is an effect that testing and tA adjustment can be performed under the same conditions as during normal clock operation.

〔Example〕 Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention, in which a selector 23 is a necessary means for carrying out the present invention. still,
Like numbers refer to like objects throughout the design.

The storage device control method of the present invention will be described below with reference to FIG.

Even if the present invention is implemented, the basic operation of the storage device will not change in particular, so it will be omitted, and the explanation here will focus on the read operation when the clock cycle is slowed down, such as during testing. .

As is clear from FIG. 1, in the present invention, the circuit for shortening the read cycle used in the conventional system, that is, the output of the shift register 22 using the free rank clock rFCLKJ is transferred to the free rank clock rFCLKJ.
Selector 2 that can be selected based on FcLKJ cycle information
3 has been added.

In the selector 23, the control signal rNOR for selection is
M-CYCJ is a signal that becomes effective when the computer system operates at the target clock cycle, and the fixed delay time of 3τ, which is the same as in the conventional system, is selected.

If the computer system is to be operated with a double-cycle clock during testing, etc., in order to make the fixed delay time the same, for example, the output from the shift register 22 should be separated by one layer. , “Enable the control signal of 2τ-MODE J.

By doing this, the free rank clock r
Even if the cycle of FCLK J is delayed, the read data (RAM-RD) is transferred to the read register (17) after the address register (ADD-REG) 31 is switched.
0-RUG) 21 can be held approximately constant, and the read data (RAM-RD) from the memory element (RAM) 11 can be correctly read and read out from the data register (RUG) 21.
D-REG) 21.

Furthermore, if the clock period becomes slower, rLOW
- Activate the CYCJ control signal to enable the read data (
Read data register (RD-R11)
:G) The timing of loading into the address register (ADD-REG) 31 is set to match the 6th clock, which is the same as the set timing of the address register (ADD-REG) 31.

In such an example, since the period between the clocks is large, there is a margin in the access time (TAA) until the read data (RAM-RD) is output from the memory element (RAM) 11. This is because it is sufficient to use the second clock as the read clock (RCLK).

In this way, in the present invention, the address and chip select signals given to a random access memory element (RAM) etc. are switched by a control signal controlled by a gated clock, and this control signal is used as a starting signal to switch the random access memory element (RAM) etc. In a storage device that uses a method in which a set timing signal (read clock) is delayed by a free rank clock to set read data output from a read data register (RAM), etc., the address register (ADD The clock that sets the read data register (RD-REG) is fixed at the 6th clock, and the read data (1?
Since only the position of the clock that sets AM-RD is changed, there is no change in the cycle time of the read cycle, and there is no difference in the operating process between the normal time and the test time.

〔Effect of the invention〕

As described above in detail, the storage device control method of the present invention switches the address and chip select signals given to random access memory elements (RA old, etc.) using a control signal controlled by a gated clock, and activates this control signal. In order to set the read data outputted from the random access memory element (RAM) etc. to the read data register as a signal, a method is used in which the set timing signal (read clock) is delayed by a free rank clock and set. In a storage device, an arbitrary fixed timing signal generated using the free rank clock for setting read data in the read data register can be shortened according to the cycle of the free rank clock. Therefore, the read cycle shortening circuit can be used at all times, there is no change in the operation cycle time for the memory element (RAM), and there is an effect that testing and adjustment can be performed under the same conditions as during normal clock operation.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the present invention. FIG. 2 is a diagram schematically showing a configuration example of a conventional storage device. FIG. 3 is an operation time chart of the prior art; FIG. 4 is a diagram illustrating an improved control method for a storage device. It is. In the drawing, 1 is an array card, and 11 is a memory element (RAM). 2 is a highly integrated readout circuit (LSI). 21 is a read data register (RD-REG). 22 is a shift register, and 23 is a selector. 31 is an address register (ADD-REG). 32 is a chip select register (C3-REG). 24M-RD is read data. RCLK is the read clock. FCLK is a free run clock. GCLK is a gated clock. TR1G is a start signal. are shown respectively.

Claims (1)

[Claims] The address and chip select signals given to the memory element group (1) are switched by a control signal controlled by a first clock, and the control signal is used as a starting signal to switch the address and chip select signal given to the memory element group (11).
), the control signal necessary to set the read data in the read data register (21) is transmitted to the second , the delayed control signal sets the read data in the read data register (21), and the output of the read data register (21) is transmitted to the circuit operated by the first clock. In a storage device using this method, when the control signal necessary to set the read data register (21) is delayed using the second clock, the amount of the delay time is determined by the amount of the delay time of the second clock. A storage device control method characterized by variable control in accordance with a cycle.