JPH01155600A - Lsi test system - Google Patents

Abstract

PURPOSE:To facilitate the preparation of expected value data by executing the switching control of the expected value data to a port based on the respective preparation timing of plural address information prepared correspondingly to other port, plural reading/writing control information prepared correspondingly to the other port, and the control information. CONSTITUTION:When the same address is detected, the conditions of a security port at the time of a simultaneous writing previously set by an address matching detecting and timing conditions deciding device 6 are decided, and the comparison with reading data is executed after the switching of an expected value pattern is executed in a pattern selecting and pin electronics part 8 corresponding to a pin for the expected value of an A port according to the decided result. Thereafter, for example, when the data are the one of a single bit, the writing conditions of dissimilar data to A and B ports are decided at the conditions deciding device 6, and the expected value data of the A port are inverted according to the decided result. Thus, the expected value can be prepared automatically.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a memory/logic mixed LSI test method, and particularly relates to an LSI test method suitable for testing multi-port memories.
This relates to the I test method.

[Conventional technology]

Conventional testing methods for 2-port memory include sending and receiving test data between two units connected to each port of the 2-port memory, as described in, for example, Japanese Unexamined Patent Publication No. 61-280099. It is determined whether the contents are normal or not.

[Problem that the invention seeks to solve]

However, the above method does not mention generation of expected values when both ports operate simultaneously.

In particular, during simultaneous write operations from both ports, different data such as “1” and 0” are simultaneously written to the same address from both ports, and then read from both ports simultaneously and stored at that address. When testing the integrity of data written from each port, the data written from each port is not necessarily the expected value, and the integrity of the data must be correctly determined on both ports. .In general, when both ports operate simultaneously including read operation,
The expected value for read data at each port depends on whether different data has been written to the same address on other ports before or at the same time, and on the write conditions on both ports when writing simultaneously. This is because there will be cases where the expected value at port must be the same as the expected value at port.

An object of the present invention is to provide an LSI that can easily generate expected value data and test the LSI even when each port operates simultaneously.
The test method is provided.

[Means for solving problems]

The above object is achieved by checking the write conditions for each port at the time of simultaneous writing, and then generating an expected value for read data at the time of simultaneous reading based on the result of checking the write conditions.

[For production]

One of the write conditions for guaranteeing the integrity of data in the memory during simultaneous write operations at each port is a timing difference (time difference) between memory write signals. If this time difference is maintained at a certain level or more, the write data from the port with the slower timing will be saved in the memory, so if you set this condition in advance, If the addresses at the time of memory access from each port match, the expected value of another port can be used as that of the own port based on preset determination conditions.

〔Example〕

The present invention will be explained below with reference to FIGS. 1 to 4, taking a two-port memory as an example.

First, we will explain the 2-port memory using Figure 2.
Unlike ordinary DRAM-like memories, 2-port memory has two accessible port buffers 25,26 for one memory cell, so two external buses can be connected simultaneously or in different pass cycles. One memory 21 can be shared by two devices. It is also used for message communication between different computers (CPUs), such as writing something written from one port and reading it from the other port, but in this type of memory test, the normal single In addition to port memory testing, simultaneous operational testing from both ports is required to test the functional features described above. In a simultaneous operation test from both ports, reading and writing may be performed simultaneously to the same specified address. Specifically, there are three types: simultaneous writing to both ports, simultaneous reading from both ports, and port reading for one port writing. The reprinted 2-port memory usually has two internal readout circuits, so simultaneous reading is guaranteed unconditionally, but in the case of simultaneous writing or port reading for one-port writing, Warranty conditions vary slightly depending on the manufacturer. Examples of guaranteed conditions include, as mentioned above, that among the write signals to both ports, the data from the port with the slower timing is preferentially stored in the memory cell, and Among the write signals and chip selection signals, data from the port that is input earlier is preferentially stored (a busy signal is output to the ignored port). In any case, it is necessary to read and test the data in the cell during simultaneous writing from both ports. Furthermore, the simultaneous operation of one-port write and port read is a real-time data transfer function test between ports, and the timing conditions between the memory control signals described above must be satisfied between both ports. In addition, the second
In the figure, 22 and 23 indicate address decoders, and 24 indicates a control logic.

Now, simultaneous operation tests may be conducted in the same test cycle or in different test cycles, but in order to simplify the explanation, in this example, the case in the same test cycle will be explained below.

FIG. 1 shows the overall configuration of a test device according to the present invention for a 2-port memory. According to this, a memory pattern generator (PGI) is provided for each port.
, PIE2) 3 is for generating addresses and various data independently for each port, and can operate at basic clock rates A and B arbitrarily selected from timing generator (TG) 2. It becomes. Of course, parallel operation at the same rate is also easily possible.

As shown in the figure, each pattern generator 3 consists of a test sequence processor section (TSP) 4 and an algorithmic pattern generation section (ALPG) 5, and the algorithmic pattern generation section 5 operates according to a microprogram and generates a memory pattern into an internal memory. The test sequence processor section 4 outputs to the pattern generation section 5 an address that specifies the operation sequence of the microprogram in the algorithmic pattern generation section 5 . The processor section 4 also specifies a rate for setting the operating frequency and a phase for setting the pattern output timing for the timing generator 2, and specifies the predetermined rates A, B and phase arbitrarily from the timing generator 2. It is now selected. The start/stop of the test is controlled by the start/stop controller 1 controlling the timing generator 2 and the test sequence processor section 4.

Here, to explain the operation of the test equipment using an example of pattern generation during a simultaneous operation test shown in FIG. 3, the memory addresses for A port and B port output from each pattern generator 3 are internal Memory under test (CUT) as a 2-port memory is output to bus 7. Pattern selection corresponds one-to-one to the pins of memory under test (CUT) 9. Predetermined pattern selection and waveform generation are performed in pin electronics section 8, and the same address is output. The pattern is supplied to the memory under test 9 as a pattern. At that time, each of the pattern generators 3 outputs a write/write control signal R/W for controlling simultaneous writing and simultaneous reading for the A port and the B port, write data at the time of writing, and read data. The expected value data EXP at the time is output in the same way as the address, but in this example, the timing between the read/write control signals R/W to the A port and the B port is set to a certain time difference tvwt as shown in the figure. Since the phase is specified to the timing generator 2 by the processor section 4 in advance, in the illustrated example, the write data DBo to the B port is
will be read from the A port and B port during the next simultaneous read cycle T1. Write data D for A port
Since ^ is generally different from the write data DB for B port,
At the time of simultaneous successive cycle T1, it is necessary to switch the expected value pattern for port A to the expected value pattern for port B. An address match detection/timing condition determiner 6 is provided for this switching control, and if the same address is detected, the preset guaranteed port conditions for simultaneous writing are determined. Based on the judgment result, A
The expected value pattern is switched within the pattern selection/pin electronics section 8 corresponding to the expected value pin of the port, and then compared with successive data by a comparator. The data width of a normal two-port memory is multiple bits, but in the case of single-bit data, the condition determiner 6 determines the conditions for writing different data to both ports, and depending on the determination result, the A port Even if the expected value data is inverted, the expected value can be automatically generated.

Next, the fourth example of the pattern that occurred during the data transfer test.
To explain with a diagram, data D^ written to address Ao from port A in cycle TO is simultaneously read out by port B, and then data D written to address AO from port B in cycle T1 is simultaneously read out by port A. By performing a read operation every time a cell address is updated, a data transfer test in both directions is performed for all cells. In this case, the expected value is the data written from the other port, so the condition determiner 6 uses the read/write control signal R/W and the preset test. The expected value at the time of reading at the reading port can be automatically generated based on the mode.

In addition, in the simultaneous operation test, the output from the address match detection/timing condition judger 6 is used to control expected value switching and also to the pass/fail judgment comparator (from the memory under test 9) included in the pin electronics section 8. If necessary, it can also be used for control to mask the judgment of a comparator that compares and judges successive outputs with expected values. The determination output from the condition determiner 6 is inside each pin electronics section 8,
It is possible to independently select each pin by an enable signal from the processor section 4.

Furthermore, when the pattern generator 3 operates asynchronously at different rates, if the same address occurs in a cycle and the timing condition determiner 6 detects the simultaneous operation, the processor unit 3 Interlocking control is performed by interrupting the pattern generator 5 to cause the pattern generator 5 to stop or pause pattern generation, and after keeping pace with the pattern generators 3, restarting or canceling the pause is performed. By performing the test between the processor units 4, more complicated tests can be performed and synchronized patterns can be generated.

Furthermore, for memories with three or more ports, simultaneous operation tests can be performed by selecting the pattern output to the internal bus 7 at each pin electronics section 8, without fundamentally changing the configuration shown in Figure 1. You will get it.

〔Effect of the invention〕

As explained above, according to the present invention, in a simultaneous operation test of a multi-port memory such as a 2-port memory, expected values are automatically generated for simultaneous write and read operations, so that test pattern programs can be created. This not only reduces the complexity of the process, but also allows for different cycle operations that are close to actual usage conditions.

This has the advantage that flexible synchronization patterns can be generated.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the overall configuration of an example of a test device according to the present invention for a 2-port memory, FIG. 2 is a diagram showing a general configuration of a 12,2-port memory, and FIG. FIG. 4 is a diagram illustrating an example of pattern generation during a simultaneous operation test by the device, and FIG. 4 is a diagram illustrating an example of pattern generation during a data transfer test. DESCRIPTION OF SYMBOLS 1... Start/stop controller, 2... Timing generator, 3... Pattern generator, 4... Test sequence processor section, 5... Algorithmic pattern generation section, 6... Address match Detection/timing condition determiner, 7... Internal bus, 8... Pattern selection/pin electronics section, 9... Memory under test. Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] 1. Address information, write data, read/write control information, and This is an LSI test method in which expected value data is generated, and the expected value data is compared and judged with data read from a port, and a plurality of address information generated corresponding to the ports,
An LSI testing method characterized by controlling switching of expected value data to other ports based on a plurality of pieces of read/write control information generated corresponding to ports and the generation timing of each of the control information. 2. When address information, write data, read/write control information, and expected values corresponding to ports are generated by program control, the generation of the information and data is stopped and the stop is canceled, and the generation of the information and data is stopped and the stop is stopped. The release is controlled by either a plurality of address information generated corresponding to ports, a plurality of read/write control information generated corresponding to ports, and the generation timing of each of the control information. LSI test method described in section. 3. When the read data from each port and the expected value data are compared and judged, the comparison judgment result is a plurality of address information generated for each port or a plurality of read/write control information generated for each port. 2. The LSI test method according to claim 1, wherein mask control is performed by any of the generation timings of each of the control information and the control information.