JPH01154550A - Manufacture of complementary mos semiconductor device - Google Patents

Abstract

PURPOSE:To provide a complementary MOS semiconductor device capable of preventing short-circuit caused by electrostatic breakdown of an insulating film, by forming a polysilicon layer on an interlayer insulating film including contact holes, providing the polysilicon layer with electrical conductivity, and introducing dopants in the contact holes by means of ion implantation. CONSTITUTION:Contact holes 8, 9 and 10 are formed in an interlayer insulating film 7 of PSG reflown by a heat treatment, corresponding to a P-type diffusion layer region 6, an N-type diffusion layer region 5 and a gate electrode 4, respectively. Then a thin polysilicon layer 11 is deposited all over the surface. Phosphorus contained in the interlayer insulating film 7 is diffused thermally into the polysilicon layer 11 and it is further heat-treated to decrease its specific resistance. Only the P-channel side is covered with a resist mask 12 and phosphorus ions as N-type dopant are implanted so that a second N-type diffusion layer region 13 deeper than the N-type diffusion layer region 5 is formed in the region 5. Then, the N-channel side is covered with a resist mask 14, and boron ions as P-type dopants are implanted so that a P-type diffusion layer region 15 deeper than the P-type diffusion layer region 8 is formed in the region 6.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a complementary MOS semiconductor device, and particularly to a method for introducing impurities into a contact hole for taking out an electrode.

[Conventional technology]

In recent years, with the miniaturization and high-density integration of complementary MOS semiconductor devices, various planar margins have become smaller, and the junction depth of the P and N diffusion layers formed on the main surface of the semiconductor substrate has also become shallower. There is. Therefore, when connecting electrodes to this type of diffusion layer, contact holes are opened in the insulating film at locations corresponding to the 20P and N diffusion layers, and then impurities of the same conductivity type as each diffusion layer are inserted. is introduced into this contact hole by a self-line, thereby preventing a short circuit between the electrode and the semiconductor substrate due to junction breakdown that is likely to occur in the contact hole portion.

Therefore, when forming this structure in a conventional complementary MOS semiconductor device, after forming a contact hole, the -channel side, for example, the P channel side, is covered with a mask material and N type impurity ions are implanted into the contact hole on the N channel side. What is needed is a method of introducing P-type impurities into the P-channel side by ion implantation, covering the opposite N-channel side with a mask material, and then introducing P-type impurities into the P-channel side by ion implantation.

[Problem that the invention seeks to solve]

In the conventional method of introducing impurities into contact holes described above, the main surface of the semiconductor substrate is covered with an interlayer insulating film or a resist layer for a mask when impurity ions are implanted, so the surface is charged by the energy during ion implantation. However, there are problems in that the gate electrode and the semiconductor substrate are short-circuited due to electrostatic breakdown of the gate insulating film, and the interlayer insulating film itself is electrostatically damaged, resulting in short-circuiting between the wiring electrode and the semiconductor substrate.

SUMMARY OF THE INVENTION An object of the present invention is to provide a manufacturing method capable of manufacturing a highly reliable complementary MOS semiconductor device by preventing short-circuit accidents caused by electrostatic breakdown of an insulating film.

[Means for Solving the Problems] The method for manufacturing a complementary MOS semiconductor device of the present invention includes a step of opening a contact hole in an interlayer insulating film facing a PN junction formed in a semiconductor substrate, and an interlayer insulating film including this contact hole. A process of forming a polysilicon layer on the insulating film, a process of diffusing impurities contained in the interlayer insulating film into this polysilicon layer to make it conductive, and a process of introducing impurities into the contact hole area by ion implantation. This makes it possible to implant ions into the contact hole portion without charging the insulating film.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

1 to 3 are longitudinal cross-sectional views showing the main steps of an embodiment of the present invention.

In Figure 1, an N well 2 is formed on the main surface of a P-type semiconductor substrate 1, a field insulating film 3 for element isolation is formed, a gate electrode 4 of a MOS type FET is formed here, and a semiconductor N-type diffusion layer regions 5 forming the source and drain of an N-channel MOS transistor on the main surface of the substrate 1;
This shows a state in which P-type diffusion layer regions 6 forming the source and drain of a P-channel MOS transistor are formed.

Note that 7 is an interlayer insulating film made of PSG that has been reflowed by heat treatment, and here the P-type diffusion layer region 6 is
．． N-type diffusion N region5. Contact holes 8, 9 and 10 are formed corresponding to the gate electrodes 4, respectively.

Then, as shown in FIG. 2, a thin polysilicon layer 11 is deposited over the entire surface. The thickness of the polysilicon layer 11 is 100
~1000 people is appropriate. Then, the interlayer insulating film 7
The phosphorus contained in the polysilicon layer 11 is thermally diffused into the polysilicon layer 11, and the specific resistivity is further reduced by heat treatment. The heat treatment temperature is 7, which is a temperature at which the interlayer insulating film 7 does not reflow.
00-900°C is suitable.

Then, in order to introduce an impurity into the contact part, only the P channel side is covered with a resist mask 12, ions of phosphorus as an N type impurity are implanted, and a second N type diffusion layer deeper than this is formed in the N type diffusion layer region 5. A region 13 is formed.

Similarly, the N-channel side is covered with a resist mask as shown in FIG.
form.

In each of the ion implantations described above, the dose is set so that the impurity concentration on the surface of the contact portion becomes 1020 or more with energy that allows the ions to sufficiently penetrate the polysilicon layer 11.

After the above steps, a metal or polysilicon film for an electrode is formed as usual and etched into a desired pattern to form the P-type diffusion layer region 6. Electrodes connected to each of the N-type diffusion layer regions 5 can be formed. The polysilicon layer 11 may be etched at the same time as the respective electrodes during this etching. Alternatively, it may be removed before forming the metal for the electrode.

Therefore, in this manufacturing method, when ions are implanted into the contact portion, the entire surface of the semiconductor device is covered with the polysilicon layer 11 imparted with conductivity, so the insulating film is not charged, and the insulating film at this time Electrostatic damage can be reliably prevented.

In the above example, PS is used as the interlayer insulating film containing phosphorus.
Although BPSG was explained above, it may also be BPSG or a mixture of these and other glasses. Furthermore, there is no limit to the method of depositing the thin polysilicon layer 11, and CVD can be used.

Any method such as sputtering may be used. Furthermore, the atmosphere for heat treatment for thermally diffusing phosphorus into the polysilicon layer 32 can be freely selected.

〔Effect of the invention〕

As explained above, the present invention forms a polysilicon layer on an interlayer insulating film including a contact hole, makes this polysilicon layer conductive, and then introduces impurities into the contact hole by ion implantation. Since this polysilicon layer includes a step of It has the advantage of being manufacturable.

[Brief explanation of the drawing]

1 to 3 are vertical sectional views showing an embodiment of the present invention in the order of steps. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... N well, 3... Field insulating film, 4... Gate electrode, 5... N type diffusion layer region, 6... P type diffusion layer region, 7 ...Interlayer insulating film (psc), 8.9.10...contact hole, 1
1... Polysilicon layer, 12... Resist mask,
13... Second N type diffusion layer region, 14... Resist mask, 15... Second P type diffusion layer region.

Claims (1)

[Claims] (1) When manufacturing a complementary MOS semiconductor device having an interlayer insulating film containing impurities such as phosphorus, a step of opening a contact hole in the interlayer insulating film facing a PN junction formed in a semiconductor substrate, and including this contact hole. a step of forming a polysilicon layer on the interlayer insulating film; a step of diffusing impurities contained in the interlayer insulating film into the polysilicon layer to make it conductive; and a step of implanting impurities into the contact hole by ion implantation. 1. A method for manufacturing a complementary MOS semiconductor device, the method comprising: introducing a complementary MOS semiconductor device.