JPH01154253A - Data processor - Google Patents

Abstract

PURPOSE:To apply a break to access given to each register and to perform program debugging with high efficiency by setting an interruption permission flag in response to the access flag of an access flag register and carrying out comparison between both flags. CONSTITUTION:When the access is given to registers R1-Rn during execution of a program, access signals a1-an are supplied to an access flag register 1. Then the access flags b1-bn are set. While interruption permission flags C1-Cn set in an interruption permission flag register 2 are compared with corresponding flags b1-bn by a comparator 3 in each bus cycle. When the comparator 3 detects the coincidence among those flags, an interruption signal 4 is activated to interrupt the execution of the program. Then break point processing is carried out.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a data processing device that facilitates debugging during software development.

[Conventional technology]

When developing software, several breakpoints are set in the middle of the program in order to debug the program, and execution of the program is temporarily suspended at these points when the program is debugged. Then, the program is checked by checking the access state of the data processing device at that time.

FIG. 2 is a block diagram showing an example of conventional hardware for checking the access status of registers.

In this figure, 11 is a data processing device (hereinafter referred to as CPU), and 12 is a register group, which is composed of one or more registers. R1 to R represent individual registers constituting the register group 12, and 1"l-1"n represents data transferred from within the registers R1 to Rn. However, n is an integer.

13 is external memory, register R1 before program execution
- Store data r1 to ro in Rn.

14 is a data bus.

Further, FIG. 3 is a flowchart illustrating the investigation procedure for investigating the register access status at a breakpoint. Note that (1) to (6) indicate each step.

The procedure will be explained below with reference to FIGS. 2 and 3.

First, before executing the program, data r1 to r in registers R1 to Rn are stored in the external memory 13 (step (1)), and then the program is executed (step (1)).
2)). Next, when a breakpoint set in the program is reached (step (3)) and program execution is interrupted, the register group 12 after program execution is
Step (4)) compares the data stored in the external memory 13 with the data r1 to rn stored in the external memory 13 before executing the program. I understand (step (5))
.

On the other hand, if the comparison in step (4) is YES, it is unknown whether or not it has been accessed (step (6)).

[Problems to be solved by the invention] As described above, when the data in registers R1 to Rn is read and examined by a program, if the read value has not changed, it means that the register has not been accessed and remains as before. I don't know if it is, or if it is accessed but the same value as before is entered and the value has not changed. Another problem is that it is not known whether data has actually been read from the register.

The present invention was made to solve this problem, and an object of the present invention is to provide a data processing device that allows for efficient debugging by easily determining whether or not a register has been accessed when depacking a program. .

[Means for solving problems]

The data processing device according to the present invention includes an access flag register that sets an access flag in a bit corresponding to an access signal of each register, and an interrupt enable flag register that sets an interrupt enable flag corresponding to each access flag of the access flag register. and a comparator that compares the flags of the interrupt permission flag register and the access flag register and outputs an interrupt signal.

[Effect]

In this invention, the access flag register sets an access flag in the bit corresponding to the access signal of each register, the interrupt enable flag register sets an interrupt enable flag corresponding to each access flag in the access flag register, and the comparator It compares the flags in the interrupt enable flag register and the access flag register and outputs an interrupt signal.

〔Example〕

FIG. 1 is a circuit diagram of a data processing device showing an embodiment of the present invention.

In the figure, the same symbols as in FIG. 2 indicate the same or corresponding parts, 1 is an access flag register, and each register R1
Access flags b1-bn are set in bits corresponding to access signals a1-an of ~Rn. 2 is an interrupt permission flag register, which sets the interrupt permission flag cl"'-ac in the bit corresponding to each access flag bl to bn of access flag register 1. 3 is a comparator, which is used for accessing interrupt permission flag register 2. Flag register 1
When the flags of the corresponding bits match, an interrupt signal 4 is output. 14a is an internal data bus.

When the interrupt signal 4 is output, the data processing device 11 interrupts the execution of the program and performs interrupt processing (breakpoint processing). That is, the flag state of the access flag register 1 at the time when the interrupt signal 4 is generated is outputted to the outside.

Next, the operation will be explained.

First, all access flags b1 to bn in the access flag register 1 are reset before program execution. Next, the interrupt permission flags C1 to C in the interrupt permission flag register 2 corresponding to the registers R8 to Rn whose access status is to be detected are set. While the program is running,
When each register R1-Rn is accessed, each access signal a1-a is input to the access flag register 1. And access signals a1-a.

Access flags b1 to bn corresponding to each partner are set.

On the other hand, the interrupt permission flag C, ``-10n'' set in the interrupt permission flag register 2 is compared with the corresponding access flags b1 to b in every bus cycle by the comparator 3.

When a match of the flags is detected, interrupt signal 4 becomes active and program execution is interrupted. In other words, breakpoint processing is performed.

For example, interrupt enable flag C1 is set before program execution.
If you set register R1 during program execution,
When accessed, the access flag b1 is set, a match is detected by the comparator 3, and breakpoint processing is activated.

At this time, the data processing device 11 uses the internal data bus 14a.
Since the contents of access flags b, ~b, are output to the outside via can be done efficiently.

Note that by setting a plurality of interrupt permission flags 01 to cn, the interrupt signal 4 may be generated by the logical sum of the flags.

Furthermore, if the comparator 3 is configured to generate the interrupt signal 4 by the AND of the flags, when the plurality of set interrupt permission flags c1 to C all match, that is, the plurality of registers R1 corresponding to the flags Breakpoint processing is activated for the first time when ~Rn are all accessed.

〔Effect of the invention〕

As explained above, the present invention includes an access flag register that sets an access flag in a bit corresponding to an access signal of each register, and an interrupt enable flag register that sets an interrupt enable flag corresponding to each access flag of this access flag register. , a comparator is provided that compares the flags of this interrupt enable flag register and the access flag register and outputs an interrupt signal.
A break can be applied to access to each register, and the access status of each register when a break occurs can be determined from the access flag, which has the effect of efficiently depacking the program.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram of a data processing device showing an embodiment of the present invention, FIG. 2 is a configuration diagram showing an example of conventional hardware for checking register access status, and FIG. 3 is a diagram showing register access. It is a flowchart explaining investigation of a situation. In the figure, 1 is an access flag register, 2 is an interrupt enable flag register, 3 is a comparator, 4 is an interrupt signal, R1-Rn are registers, at to an are access signals,
b+ to bn are access flags, and clNcn is an interrupt permission flag. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa (2 others) Figure 1 R1-Rn Registers 81-an Access signals b1-bn Access flags c1-Cn Harmful request permission flag Figure 2 Figure 3 Procedure amendment ( (Spontaneous) 1. Indication of the incident Patent Application No. 1983-314616 2.
Name of the invention Data processing device 3, relationship to the person making the amendment Patent applicant address 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Name (601) Mitsubishi Electric Corporation Representative Moriya Shiki 4, Agent Address Mitsubishi Electric Corporation, 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Name (7375) Masuo Oiwa, Patent Attorney (Contact address: 03 (213) 3421, Licensing Department) 7'5, Invention of the specification subject to amendment Detailed Explanation Column 6, Contents of Amendment (1) “01-Ci” on page 8, line 8 of the specification (((
(2) Correct "R1-R・" on page 8, line 10 to "I (more than one of Rt-R1)".

Claims (1)

[Claims] In a data processing device that has one or more registers and accesses these registers, an access flag register sets an access flag to a bit corresponding to an access signal of each register, and an access flag register corresponding to each access flag of this access flag register. A data processing device comprising: an interrupt enable flag register for setting an interrupt enable flag; and a comparator for comparing flags between the interrupt enable flag register and the access flag register and outputting an interrupt signal. .