JPH01152881A - Video signal processing unit - Google Patents

Abstract

PURPOSE:To obtain a video signal with synchronizing signal representing a converted pattern with comparatively simple processing by providing a memory capable of storing one field of a video signal, extracting the synchronizing part and the picture part except the synchronizing part in the inputted video signal from different fields and writing them in the memory. CONSTITUTION:Edge pulses of horizontal and vertical synchronizing signals HD, VD obtained from edge detection circuits 104, 105 are fed to horizontal vertical synchronizing area extraction circuits 106, 107. The synchronizing areas VA, HA extracted by both the circuits 106, 107 are stored in other field memory different from that for the picture part. The circuits 106, 107 output a signal being at an Lo during the VA, HA. The signal representing the areas VA, HA is used to control the write timing and memory address to the field memory 42. For example, the VA, HA are written in the 1st field and the reduced patterns a, b, c, d are written sequentially in the 2nd-5th fields. Thus, the processing in each field is simple and simple processing is obtained.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a video signal processing device, and particularly to a video signal processing device that converts an image using a memory capable of storing one field worth of video signal. .

[Conventional technology]

In recent years, so-called helical scan video tape recorders (VTRs) have been developed to digitally encode video signals and write them into a memory (hereinafter referred to as field memory) that stores one field of digital video signals. Things that realize this function have been proposed and implemented.

That is, by appropriately setting the write and read addresses and write and read timings to the field memory,
Good special playback and various special effects have been realized.

This type of VTR will be explained below.

FIG. 9 is a diagram showing a schematic configuration of a reproduction system of this type of VTR, and FIG. 10 is a timing chart for explaining the operation of each part of the same.

HA and HB are 180 degrees from each other along the outer circumferential surface of the rotating head cylinder where the tape is wound over an angular range of 180 degrees or more.
The rotary head rotates with a phase difference of .degree., and has different azimuth angles. 2 is the above rotating head)
(A, a head for detecting the rotational phase of HB,
A rectangular wave signal (hereinafter referred to as PG) as shown in FIG. 10(a-1) is output. For example, if the recorded signal is an NTSC television signal, this PG controls the head switch 4 (3 Q Hz) = As a result, a reproduced video signal is continuously obtained from the head switch 4, and this reproduced The video signal is a Y/C signal that separates the FM modulated luminance signal (FM-Y) and the low frequency converted carrier color signal (low frequency C).
It is supplied to the separation circuit 6. FM- separated by the circuit 6
Y is subjected to known processing such as FM demodulation in the luminance signal processing circuit 8, and low frequency C is subjected to frequency conversion and other processing in the chroma signal processing circuit 10.

The baseband luminance signal and carrier color signal thus obtained are mixed in a mixer 12 to obtain a reproduced composite color video signal.

During standard playback, the switch 14 is connected to the N side in the figure, and the output of the mixer 12 is outputted to the output terminal 16 via the switch 14.

Next, the operation during playback using field memory will be explained. The terminal 18 is a terminal to which a signal that becomes high level (Hi) for a period of two fields is input when a write command to the field memory is issued by an operation unit (not shown) during standard playback. 20 is a terminal to which a clock of color subcarrier frequency (fsc) obtained by, for example, the chroma signal processing circuit 10 is input; the frequency of the input clock is multiplied by the PLL 22 and used as a driving pulse for the timing controller 26. It is said that

A clock obtained by frequency-dividing the output of the PLL 22 by the divider 24 is also input to the timing controller 26, and the timing controller 26 controls the timing of each part based on these clocks.

28.30 is a D-flip-flop (D-FF), the above-mentioned PG is connected to the D terminal of D-FF28, and D-FF3
The Q outputs of D-F'F'28 are respectively input to the D terminal of 0. The clock terminals of the D-FFs 28 and 30 are supplied with a sufficiently high frequency, for example fs, from the timing controller 26.
When the clock of c is input, the pulse output from the Q terminal of D-FF30 is opposite in phase to the pulse inputted from the Q terminal of D-FF28 and is 1/f s.
It has a delay of c. Therefore, these are exclusive ORed (EX
OR) 32, a low-level signal is obtained only at the edge portion of PG, and by ORing the output of this EXOR 32 and the Q output of D-FF 28 with OR gate 34, the falling edge of PG is obtained. A 2-field periodic pulse (hereinafter referred to as a frame pulse) is obtained in which only the shift portion is at a low level.

Multiple write command signals input through the terminal 18 are synchronized by the D-FF 36 with the frame pulse output from the OR gate 34. When the Q output of the D-FF 35 rises, the multivibrator (MM) 38 is activated by +1, and a one-shot pulse is output. The one-shot pulse output by MM38 is set-reset flip-flop (SR-
FF) Set 40. The Q output of this 5R-FF 40 switches between writing and reading of the memory 42. That is, the memory 42 enters the write state at the PG falling timing immediately after the write command signal input to the terminal 18 becomes Hi.

On the other hand, the frame pulse output from the OR gate 34 passes through the AND gate 44 to reset the address counter 46 (
R8T) terminal and is also input to the clear (CL) terminal of the 263H detection circuit 48, which will be described later, to set these to the initial state.

Writing to the memory 42 will be explained below. The composite color video signal output from the mixer 12 is band-limited by a pre-low pass filter (LPF) 5Q, and then digitized by an analog-to-digital (A/D) converter 52. 54 and 56 are input/output interfaces (F) that control the data transfer rate, transfer timing, mode, etc. of the memory 42.

In the NTSC signal, one field has 262.5 horizontal scanning lines. However, if a video signal for 262.5 horizontal scanning lines is simply stored in the memory 42 and read out repeatedly, a skew of 0.5 horizontal scanning period (0.5H) will occur. This situation is shown in FIG. Figure 10 (a-II) and (a-ill) are LPF'
The vertical synchronization signal (V1) and horizontal synchronization signal (HD) of the composite color television signal input to 5Q are input. FIG. 10 (b-i) shows 262.
This is a write/read switching signal when storing 5H worth of signals. FIG. 10(b-If)r(b-iii) is the VD and HD of the signals obtained by writing to and reading from the memory in this case, and as shown in the figure, a skew of <3AH occurs. become.

Therefore, it is considered that the writing period to the memory is set to 263H and the reading of 262H and the reading of 263H are performed alternately. FIG. 10 (c-1) shows the write/read switching signal in this case, (c-1) and (c-ill) are F(D, VD, respectively) in this case.

The configuration shown in FIG. 9 also has a write period of 263H in this way, and when the address color/receiver 46 counts 263H of addresses, the 263H detection circuit 48 outputs a pulse, and the 5R-FF 40 At the same time, the address color/reset 46 is reset. Along with this, 5R-F
The Q output of F40 becomes Hi, and the υ memory 42 reads data at the address specified by the reset address counter 46.

The data read from the memory 42 is converted into an analog signal by a digital-to-analog (D/A) converter 58 via an FF 56, band-limited by a downstream LPF 60, and sent to the switch 1.
It is input to the M side terminal of 4. In addition, the A/D converter 52.1
F54, 56 and D/A converter 58 are controlled by a clock output from timing controller 26.

When the memory 42 performs the read operation and 262H elapses without any subsequent write command, a frame pulse is input from the OR gate 34 to the reset terminal of the address callan 346, and the read address of the memory 42 is reset. . In the next field, the address counter 46 continues until the 263H detection circuit 48 outputs a pulse.
operates, and 263H worth of data is read from the memory 42. From then on, until a new write command signal is input, 2
Data for 62H and data for 263H are read out alternately.

With the above configuration, still image playback, slow motion playback, etc. can be realized by changing the tape speed variously, switching the switch 14 at a predetermined timing, and further inputting a write command signal as appropriate.

On the other hand, as mentioned above, by defining (mapping) various memory addresses two-dimensionally rather than using an address counter, the image can be reduced or enlarged.
It is also possible to perform transformations such as rearrangement and composition.

[Problem that the invention seeks to solve]

By the way, when performing the above-mentioned image conversion, the synchronization signal is generally generated by a separate pseudo synchronization signal adding circuit. This is because, for example, when reducing an image, the image is written at every pixel in the horizontal and vertical directions, but all sampling points must be written for the synchronization signal, which requires addressing processing and writing timing settings. This is because it becomes extremely troublesome.

According to the present invention, it is an object of the present invention to provide a video signal processing device that realizes generation of a video signal including a synchronization signal and a conversion screen by simple memory control without providing a separate synchronization signal addition circuit. With the goal.

[Means for solving problems]

For this purpose, the video signal processing device of the present invention includes a memory capable of storing one field of a video signal, and stores a synchronous portion including a synchronous signal in an input video signal, and a synchronous portion including a synchronous signal. The configuration is such that the image portion other than the above image is extracted from a different field and written into the memory.

[Effect]

According to the configuration described above, it is possible to separately set the memory control method for the field in which the synchronous part is written and the memory control method in the field in which the image part is written, and the conversion screen can be changed with relatively simple processing. It has now become possible to obtain a video signal with a synchronization signal.

By configuring as described above, images at the same position on multiple screens can be stored in addresses corresponding to different positions on one screen, and even in a method of addressing field memory using address color. It is now possible to combine multiple images.

〔Example〕

The configuration of a VTR as an embodiment of the present invention will be described below.

FIG. 1 is a diagram showing the main part configuration of a reproduction system of a VTR as an embodiment of the present invention, and FIG. 9 shows a part of the memory processing circuit indicated by 1, and the configuration of other parts. About the 9th
The configuration is similar to that shown in the figure. However, the memory address in this embodiment treats one period of the color subcarrier of the composite video signal as one unit, and if the sampling frequency in the A/D converter 52 is 3 fsc, three pieces of data are treated as one unit. It will be treated as an address. Writing to the memory using such addresses and successive readings are disclosed in detail in Japanese Patent Application No. 164819/1989, previously filed by the present applicant, and will therefore be omitted in this specification.

In FIG. 1, 101 is a terminal to which the horizontal synchronization signal (HD) in the reproduced video signal is input, 102 is the terminal to which the vertical synchronization signal (VD) in the reproduced video signal is input, and 103 is an operation not shown. This is a terminal to which an image multi-display command is input from the unit.

HD input to terminals 101 and 102.

VD is a negative logic input, that is, a signal that indicates a synchronization signal section when it is Lo, and these are used in the falling edge detection circuits 104 and 10.
5. Figure 2 (A) shows this edge detection circuit 1.
04.105, FIG. 2(B) is a diagram showing an example of the configuration of
Figure (A) is a timing chart showing waveforms of various parts.

In FIG. 2 CA), 201 is a clock (FIG. 2
B) is a terminal to which a clock (shown as CK) is input, and a clock is supplied from the timing controller 26 in FIG. 202 is a terminal to which a negative logic synchronization signal as shown in (a) in FIG. 2(B) is supplied, and this synchronization signal is connected to D
-Input to FF203. The Q output of D-F'F' 203 (shown as (b) in FIG. 2(B)) is D-F F 20
4 is input. The Q output of F204 (shown as (C) in Fig. 2 (B)) and the Q output of D-FF203
The output is supplied to an EX-OR 205, edges are detected as shown in FIG. 2(d), and an OR gate (OR) 206 selects only falling edges.

HD, VD thus obtained from circuits 104 and 105
The edge pulses are supplied to a horizontal synchronization area extraction circuit 106 and a vertical synchronization area extraction circuit 107. The synchronous areas extracted by the area extraction circuits 106 and 107 are stored in a field memory separately from the image portion. Considering the protection of the vertical synchronization signal, the vertical synchronization area VA has a starting point 5H (H is the horizontal scanning period) before the leading edge of VD and has a period of 20H, and the horizontal synchronization area HA is
and the color burst signal period. The circuits 106 and 107 output signals that are LO during the first half (VA, )IAO.

A specific configuration example of the area extraction circuits 106 and 107 is shown in FIG. 3(A), and waveforms of each part of FIG. 3(A) are shown in FIG. 3(B). 210 is HD or VD (a) in Figure 3 (B)
As shown in the figure, a terminal 211 to which a negative logic is input is a terminal to which a clock to be counted is input, and a counter 212 is a counter that is reset at the leading edge of HD or VD. The count value of the counter 212 is calculated by comparators 213 and 214.
and is compared with predetermined values A and B. Comparator 213
, 214 become addition signals shown in (b) and (C) of FIG.
5 becomes a signal that becomes LO during VA" and HA as shown in FIG. 3(B) (d).Circuit 10
6.107, it is natural that the values of A and B are different.

In this embodiment, signals indicating these areas VA and HA are used to control the timing of writing to the field memory 42 and the memory address.The outline of the multi-display in this embodiment is shown in Fig. 4 below. Explain using.

Figure 4 schematically shows memory addresses, in which VA and HA are address areas corresponding to the vertical synchronization area and horizontal synchronization area, respectively. Indicates the address area of Here, if the number of IH addresses is Ha and the number of HA addresses for IH is Ba, the number of VA addresses is 20 Ha, and the remaining number of addresses is 243 Ha. Here, if the VAO write start address is 0, the write start addresses of reduced screens a, b, c, and d are 20Ha+Ba and 20Ha+(
Ha+Ba)/2゜142Ha+Ba, 142Ha+
(Ha+Ba)/2.

In this embodiment, VA and HA are written in the first field, and reduced screens a, b, c, and are written in the second to fifth fields.
Write d sequentially. Here, the reduced screens a, b, c,
When writing d, the frequency of the clock counted by the address counter is set to % when writing VA and HA, and if the address counter is always preset at the leading edge of VA, then the second to fifth fields are The count value of the address counter at the writing start timing of the image portion (portion excluding VA and HA) is 10Ha+Ba/2. However, in reality, each screen is written every horizontal scanning line, so for the reduced screen d, writing starts from the 22nd scanning line, so the count value of the address counter at the writing start timing is 1
0 Ha + (Ha+Ba)/2.

Therefore, the preset values PR2, PR, , PR4, PR5 of the address counters of the second to fifth fields are calculated as follows.

PR2=20Ha+Ba-(10Ha+Ba/2)
=10Ha+Ba/2PR5=20Ha+(Ha+Ba
)/2-(10Ha+(Ha+Ba)/2)=10H
aPR4-142Ha+Ba-(10Ha+Ba/2
)=132Ha+Ba/2PRs=142Ha+ (
Ha + Ba )/2- (10Ha + (Ha +
Ba)/2)=132Ha By setting the above-mentioned seven preset data, each reduced screen can be written in the address area as shown in FIG.

Hereinafter, the operation of each part of the first embodiment, including the above-mentioned control functions, will be explained using the timing charts of FIGS. 5 to 8.

This is to match the phase of the VA extraction signal with the phase of the HA extraction signal (HA).
The VH extraction signal (VA) output from the D-FF 108 is input to the field counter 109. On the other hand, terminal 115
A pulse synchronized with the falling edge of PG is output from the edge detector 110 having a configuration as shown in FIG. The counter 109 is D-F
Figure 2 (A) shows the edge where the Q output of F141 becomes LO.
It is reset by a pulse output from the edge detector 142 having the configuration as follows, and the outputs (1), (li), (fi
t), (iv).

(V) is sequentially brought to LO every one field period, and is composed of, for example, a shift register. In Figure 5, (1), (it), (iii).

The periods indicated by (ly) and (v) are the outputs (1), (II), and (iii) of the field counter 109, respectively.

(Iv) and (■) indicate the period of LO.

In the first field (1), the output of AND 111 is Hi, and selectors 112 and 113 each select the input signal on the B side. Therefore, the clock of frequency fsc obtained from the timing controller 26 is supplied as the clock to be counted by the address counter 114. Terminal 115' is a terminal to which an inverted signal PG of PG is input, and D-F'Ftt6 samples PG at the falling edge of VA and supplies it to edge detection circuit 117 as a Q output. The edge detection circuit 117 has a configuration as shown in FIG. 2(A) and detects only falling edges. Therefore, the edge detection circuit 117 generates a pulse synchronized with the falling edge of VA immediately before the even field signal of each frame is input. Output in cycles. −
On the other hand, when the address counter 114 counts an address of 263Ha, the detector 140 outputs a negative pulse, so the AND 118 is 263H.

A negative pulse is output every 262H. This 525H
The periodic pulse is input to the preset terminal R8T of the address counter 114 via the AND 118 and the selector 113, and presets the address counter. Therefore, the address counter is preset by the output pulse of the 263Ha detector 140 at the timing when the output (+) of the field counter 109 becomes LO. -At this time, ANDI
Since the output of II is Hi and the output of inverter 119 is Lo, data generator 121 is activated and O is set as preset data. On the other hand, (:) is ORI 2
0R126 gates the output of AND127. HA and VA are input to AND 127, and the LO signal is output only in HA and VA, and this signal is used as the memory write control signal (W/R).
W/ of Fieldme "E-!742" via ND128
It is input to the R terminal. In the first field, this signal (
(shown as W/R-1 in FIGS. 6, 7, and 8), signals are recorded in the memory 42 during the VA and HA periods.

In the second field, the output of ANDll is L
0, and the selectors 112 and 113 each output the signal input to the A side. Therefore, address counter 11
4, the clock to be counted is a clock IT type flip-flop (T-FF) 130 with frequency fsc.
A clock having a frequency fSC/2 divided by % is input. On the other hand, a pulse synchronized with the falling edge of VA obtained by the edge detector 131 is used as a preset pulse for the address counter 114.

On the other hand, since the output of ANDIII is LO, 0R13
2 is the output of the NAND gate (NAND) 133, that is, HA
, gates the signal that becomes LO except for the period of VA, and outputs 0R1.
34. T-F' F135 is a signal that is triggered by the falling edge of HA and switches between Hi and Lo every IH. The output of AND136 is low at the start of the second field.
The falling edge is detected by the edge detector 13.
7, so in the second field T
-The output of F'F' 135 becomes LO at the first IH.

Since the VA period is 20H, the first IH immediately after the VA surface
Similarly, the output of KT-FF135 is Lo.

T-FF138 outputs fsc/
2 (indicated by 3Afsc in FIG. 8) is further frequency-divided by % to obtain a clock of fsc/4.

This clock is gated by 0R139 for each IH by the output of T-FF135, and is further gated by HA.

It is gated in a period 0R134 other than the VA period and is used as a write control signal for the memory 42, and is output to the W/R terminal of the memory 42 via an AND128.

This write control signal is indicated by W/R-3 in FIG.
W/R-' in Figure 8;! , 3 shows the details.

Since the data generator 122 is activated in this second field, (10Ha+Ba/2) is supplied as the preset data to the address counter 114, and as a result, the reduced screen a is transferred to the fourth field in the memory as described above. It is stored in address area a in the figure.

Next, in the third field, the output of the T-FF 135 becomes Hi in the first IH after the completion of VA, so the write control signal becomes as shown by VV/R-2 in FIG. The details are similar to the second field. Furthermore, 1QHa is supplied from the generator 123 as address preset data. As a result, the reduced screen image is stored in the address area shown in FIG. 4 in the memory 26.

Thereafter, in the field of cylinder 4, the write control signal is the same as in the second field, and is output from the data generator 124 as address preset data (132Ha+B
a/2) is the supply sarel.

In the fifth field, the write control signal is the same as in the third field, and 132Ha output from the data generator 125 is supplied as address preset data. Along with this, the reduced screens c and d are stored at the addresses shown in FIG. be remembered.

After the fifth field, the field memory 42 is always kept in the read state, but the selectors 112, 1
13 outputs the input on the A side, so in the field following the fifth field, the address counter 114 is preset by the output pulse of the edge detector 117, and the preset data becomes 0. Furthermore, in the next field, the address counter 114 is preset by the output pulse of the 263Ha detector 140, and similarly the preset data becomes 0.

As a result, in the field after the 5th field, the 4th
The video signal for one field including the synchronization signal and four reduced screens stored at the address shown in the figure is
Read over 63H, and then 262H in the next field.
It will be read out over a period of time.

In the above embodiment, by extracting the four reduced screens and synchronization signals from separate fields of the video signal, the address preset data and write control signal of each field, as well as the counted pulses of the address counter, etc., can be separately extracted. Can be set. Therefore, the processing in each field is monotonous and simple. Also, reading from memory is
Since all processing is completed by memory control during writing, it is extremely simple, and a video signal including a synchronization signal and four reduced screens can be obtained.

In this embodiment, address control of the memory is performed using an address counter, but even when performing the above-mentioned mapping process, the synchronization signal part and the image part are written to the memory in separate fields. This allows completely different and simple mapping processing to be performed for each field.

Furthermore, in the above embodiment, the case where four % reduced screens are synthesized is taken as an example, but the present invention can also be applied when performing conversion processing such as compositing the same size screen, enlarging the screen, etc. A similar effect can be obtained.

〔Effect of the invention〕

As described above, according to the data processing device of the present invention, memory control can be simplified when a video signal indicating a converted screen is obtained together with a synchronization signal without providing a separate synchronization signal adding circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the main part configuration of a VTR as an embodiment of the present invention. FIG. 2(A) is a diagram showing the specific configuration of the edge detector in FIG. 1. 2(B) is a timing chart showing the operation of each part of FIG. 2(A), FIG. 3(A) is a diagram showing a specific configuration of the area extraction circuit in FIG. 1, and FIG. 3(B) Figure 3 (A) is a timing chart showing the operation of each part, Figure 4 is a diagram showing the address arrangement of the composite screen by the VTR of Figure 1, Figures 5, 6, 7, and 8 are FIG. 9 is a timing chart showing the waveform of the numbered part in FIG. 1, FIG. 9 is a diagram showing an example of the configuration of a conventional VTR playback system using field memory, and FIG. 10 is a diagram for explaining the operation of each part in FIG. Check the timing chart. In the figure, f(A, HB is a rotary head, 26 is a timing controller, 42 is a field memory, 106 is a horizontal synchronization area extraction circuit, 107 is a vertical synchronization area extraction circuit, 109 is a field counter, 112 and 113 are selectors, 114 is the address counter, 121.122
．． 123. 124 and 125 are preset data generators, respectively.

Claims (3)

[Claims] (1) A memory capable of storing one field of a video signal is provided, and a synchronous part including a synchronous signal and an image part other than the synchronous part are extracted from different fields from the input video signal and stored in the memory. A video signal processing device characterized by writing. (2) An address counter for determining the write address of the memory is provided, and the frequency of the counted pulse supplied to the address counter is determined in a field for writing the synchronization part and a field for writing the image part. The video signal processing device according to claim 1, characterized in that the video signal processing device is different from the above. (3) an address counter that is preset for each field for determining the write address of the memory; The video signal processing device according to claim 1, characterized in that the writing field is different.