JP2898980B2 - Video signal processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing apparatus, and more particularly to a video signal processing apparatus that synthesizes an image using a memory capable of storing one field of video signal. . [Related Art] In recent years, in a so-called helical scan type video tape recorder (VTR), a video signal is digitally encoded and written in a memory (hereinafter referred to as a field memory) for storing one field of digital video signals. Various functions have been proposed and implemented by incorporating such functions. That is, by appropriately setting the write and read addresses and the write and read timings for the field memory, better special reproduction and various special effects are realized. Hereinafter, this type of VTR will be described. FIG. 9 is a diagram showing a schematic configuration of a reproducing system of this type of VTR, and FIG. 10 is a timing chart for explaining the operation of each unit in FIG. HA and HB are rotary heads that rotate with a phase difference of 180 ° from each other along the outer peripheral surface of a rotary head cylinder around which the tape is wound in an angular range of 180 ° or more, and have different azimuth angles. Reference numeral 2 denotes a head for detecting the rotation phase of the rotation heads HA and HB, and outputs a rectangular wave signal (hereinafter referred to as PG) as shown in FIG. 10 (a-i). This PG is, for example, 30 Hz when the recorded signal is an NTSC television signal, and controls the head switch 4. As a result, a reproduced video signal is continuously obtained from the head switch 4, and the reproduced video signal is a Y signal for separating the FM modulated luminance signal (FM-Y) and the low-frequency converted carrier color signal (low frequency C). / C is supplied to the separation circuit 6. The FM-Y separated by the circuit 6 is subjected to FM demodulation and other well-known processing in a luminance signal processing circuit 8, and the low band C is subjected to frequency conversion and other processing in a chroma signal processing circuit 10. The baseband luminance signal and the carrier chrominance signal thus obtained are mixed by the mixer 12 to obtain a reproduced composite color video signal. At the time of standard reproduction, the switch 14 is connected to the N side in the figure, and the output of the mixer 12 is supplied to the output terminal 16 via the switch 14.
Is output to Next, the operation at the time of reproduction using the field memory will be described. The terminal 18 is a terminal to which a signal which becomes high level (Hi) for two fields when a write command to the field memory is issued by an operation unit (not shown) at the time of standard reproduction. Reference numeral 20 denotes a terminal to which a clock of the color subcarrier frequency (fsc) obtained by the chroma signal processing circuit 10 or the like is input.
The frequency of the input clock is multiplied by the PFF 22 and used as a drive pulse for the timing controller 26. Also
Clocks obtained by dividing the output of the PLL 22 by the frequency divider 24 are also input to the timing controller 26, and the timing controller 26 controls the timing of each unit based on these clocks. 28 and 30 are D-flip flops (D-FF).
The aforementioned PG is input to the D terminal of -FF28, and the Q output of D-FF28 is input to the D terminal of D-FF30. A sufficiently high frequency, for example, a clock of fsc is input from the timing controller 26 to the clock terminals of the D-FFs 28 and 30.
In response to the pulse output from the Q terminal of D-FF28,
The pulse output from the terminal of FF30 has the opposite phase and 11
It has a delay of / fsc. Therefore, these are exclusive OR (EX
OR) 32, a low-level pulse is obtained only at the edge of the PG, and the output of the EXOR 32 and the Q of the D-FF 28
By ORing with the output at the OR gate 34, the PG
, A pulse (hereinafter referred to as a frame pulse) having a low level only in the falling edge portion and having a period of 2 fields is obtained. The write command signal input from the terminal 18 is synchronized by the D-FF 36 with the frame pulse output from the OR gate 34. The rising edge of the Q output of the D-FF 36 triggers the monomultivibrator (MM) 38 to output a one-shot pulse. The one-shot pulse output from the MM 38 sets a set-reset flip-flop (SR-FF) 40. The output of the SR-FF 40 switches the writing / reading of the memory 42. That is, the write command signal input from the terminal 18 is Hi
The memory 42 enters the write state at the falling timing of the PG immediately after the above. On the other hand, the frame pulse output from the OR gate 34 is passed through the AND gate 44, and the address counter 46 is reset (RS
The signal is input to the T) terminal and also to the clear (CL) terminal of the 263H detection circuit 48 described later, and these are set to an initial state. Hereinafter, writing to the memory 42 will be described. Mixer
The composite color video signal output from 12 is band-limited by a low-pass filter (LPF) 50 before being digitized by an analog-to-digital (A / D) converter 52. 54 and 56 are input / output interfaces (I / O) for controlling the data transfer speed, transfer timing, mode, etc. of the memory 42.
F). One field of the NTSC signal is composed of 262.5 horizontal scanning lines. However, when the video signal for 262.5 horizontal scanning lines is simply stored in the memory 42, and the video signal is repeatedly read out, 0.
A skew of 5 horizontal scanning periods (0.5H) occurs. This is shown in FIG. Fig. 10 (a-ii), (a-ii
i) are the vertical synchronizing signal (VD) and the horizontal synchronizing signal (HD) of the composite color television signal input to the LPF 50,
FIG. 10 (b-1) shows a write / read switching signal when a signal for 262.5H is stored in synchronization with PG (a-i). FIGS. 10 (b-ii) and (b-iii) show VD and HD of the signal obtained by writing and reading to and from the memory in this case, and a skew of 1 / 2H is generated as shown in FIG. Therefore, it is considered that the writing period to the memory is 263H, and the reading of 262H and the reading of 263H are performed alternately.
FIG. 10 (ci) shows a write / read switching signal in this case,
(C-ii) and (c-iii) are HD and VD respectively in this case. The configuration shown in FIG. 9 also sets the writing period to 263H, and when the address counter 46 counts the address for 263H, the 263H detection circuit 48 outputs a pulse and the SR-FF4
Resets 0 and resets the address counter 46. As a result, the output of the SR-FF 40 becomes Hi, and the memory 42 reads the data at the address designated by the reset address counter 46. The data read from the memory 42 is converted into an analog signal by a digital-analog (D / A) converter 58 via an IF 56,
The signal is band-limited by the post-LPF 60 and input to the M-side terminal of the switch 14. The A / D converter 52, the IFs 54 and 56, and the D / A converter 58
Is controlled by the clock output from the timing controller 26. When 262H elapses without performing a new write command after the memory 42 performs the read operation in this way, a frame pulse is input from the OR gate 34 to the reset terminal of the address counter 46, and the read address of the memory 42 is reset. Then, in the next field, the address counter 46 operates until the 263H detection circuit 48 outputs a pulse, and data for 263H is read from the memory 42. Thereafter, data of 262H and data of 263H are read alternately until a new write command signal is input. With the above configuration, the tape speed can be variously switched, the switch 14 can be switched at a predetermined timing, and a write command signal can be appropriately input to realize still image reproduction, slow motion reproduction, and the like. On the other hand, as described above, the address of the field memory is not defined by the address counter, but by two-dimensionally defining (mapping) the memory address in a two-dimensional manner to reduce or enlarge the image.
It is also possible to perform synthesis or the like. [Problems to be Solved by the Invention] However, the addressing processing of the memory requires a large-scale operator and a large-capacity storage element. On the other hand, in the method using the address counter, processes such as image reduction, enlargement, and synthesis cannot be performed. In particular, processing for synthesizing a plurality of screens is extremely complicated in addressing, and the use of the address counter has not been performed. In view of the above background, it is an object of the present invention to provide a video signal processing apparatus capable of synthesizing a plurality of screens by a simple addressing process using an address counter. [Means for Solving the Problems] For this purpose, the present invention is an apparatus for processing images of a plurality of reduced fields, which can be displayed on the same screen, and a video signal for one field. , An address counter for determining a write address of the memory, and a first mode for supplying a first count clock of a predetermined frequency to the address counter and writing a synchronization signal to the memory A plurality of preset values corresponding to a display position of the reduced image of each field to be displayed on the same screen on the screen to the address counter, and a second count clock having a frequency lower than the predetermined frequency. Is supplied to the address counter, and the memory in which the synchronization signal is written in the first mode is And a memory control means having a second mode for writing the reduced plurality of video signals of different fields. [Operation] By configuring as described above, images of a plurality of fields can be stored at addresses corresponding to different positions on one screen, and a plurality of images can be stored even in a method of addressing a field memory using an address counter. It became possible to synthesize. Further, at this time, the synchronization signal can be added to the composite reduced screen only by controlling the writing of the memory without providing a pseudo synchronization signal addition circuit. Embodiment Hereinafter, a configuration of a VTR as an embodiment of the present invention will be described. FIG. 1 is a diagram showing a configuration of a main part of a reproduction system of a VTR as one embodiment of the present invention. FIG. 9 shows a portion of a memory processing circuit indicated by 1 in FIG. This is the same as the configuration in FIG. However, the memory address in this embodiment handles one cycle of the chrominance subcarrier of the composite video signal as one unit, and if the sampling frequency in the A / D converter 52 is 3 fsc, the three data are the same. It will be treated as an address. Writing and reading data to and from the memory using such addresses are disclosed in detail in Japanese Patent Application No. 62-164829 filed earlier by the present applicant, and will not be described herein. In FIG. 1, reference numeral 101 denotes a terminal to which a horizontal synchronizing signal (HD) in a reproduced video signal is input, 102 denotes a terminal to which a vertical synchronizing signal (VD) in a reproduced video signal is input, and 103 denotes an operation (not shown) This is a terminal to which a multi-display instruction of an image is input from the unit. HD and VD input to the terminals 101 and 102 are negative logic inputs, that is, signals indicating a synchronizing signal portion when Lo, and these are supplied to the falling edge detection circuits 104 and 105. Fig. 2 (A)
FIG. 2 shows a configuration example of the edge detection circuits 104 and 105.
FIG. 2B is a timing chart showing waveforms at various points in FIG. 2A. In FIG. 2A, reference numeral 201 denotes a terminal to which a clock having a frequency sufficiently high with respect to the synchronization signal, for example, a clock having a frequency fsc (indicated by ck in FIG. 2B) is input.
The clock is supplied from the timing controller 26 in FIG. Reference numeral 202 denotes a terminal to which a negative logic synchronization signal as shown in FIG. 2B (a) is supplied. This synchronization signal is input to the D-FF 203. The Q output (shown by (b) in FIG. 2B) of the D-FF 203 is input to the D-FF 204. The output of the D-FF 204 (shown by (c) in FIG. 2 (B)) and the Q output of the D-FF 203 are supplied to the EX-OR 205, and an edge is detected as shown in FIG. 2 (d). O
R) At 206, only the falling edge is selected. The edge pulses of HD and VD obtained from the circuits 104 and 105 are supplied to the horizontal synchronization area extraction circuit 106 and the vertical synchronization area extraction circuit 107. The synchronous areas extracted by the area extracting circuits 106 and 107 are stored in a field memory separately from the image part. The vertical synchronization area VA takes into consideration the protection of the vertical synchronization signal, and the starting point is 6H (H is the horizontal scanning period) before the leading edge of VD, and the period is 20H. The horizontal synchronization area HA is the HD and color burst signal. Period. The circuits 106 and 107 output a signal which becomes Lo between the above VA and HA. FIG. 3 (A) shows a specific configuration example of the area extraction circuits 106 and 107, and FIG. 3 (B) shows the waveforms of the respective parts in FIG. 3 (A). Numeral 210 denotes a terminal to which HD or VD is inputted by negative logic as shown in FIG. 3B (a), numeral 211 denotes a terminal to which a counted clock is inputted, and counter 212: HD or VD.
This is a counter that is reset at the leading edge of D. The counter 2
The twelve count values are supplied to comparators 213 and 214 and compared with predetermined values A and B. The outputs of the comparators 213 and 214 become signals as shown in (b) and (c) of FIG. 3 (B). These signals are inputted to an AND gate (AND) 215, and are output as shown in FIG.
(D) is a signal that is low between VA and HA as shown in FIG. It is natural that the values of A and B are different between the circuits 106 and 107. In the present embodiment, the signals indicating these areas VA and HA are used to control the write timing and the memory address in the field memory 42, and FIG. 4 shows an outline of the multi display in the present embodiment. It will be described using FIG. FIG. 4 schematically shows the addresses of the memory, in which VA is
HA is the address area corresponding to the vertical synchronization area and horizontal synchronization area, respectively, and a, b, c, and d are half the screen of one field respectively.
Shows the address area of the reduced image. If the number of 1H addresses is Ha and the number of HA addresses for 1H is Ba, then VA
Has 20 Ha and the remaining number of addresses is 243 Ha. Here, if the writing start address of VA is O, the reduced screen
The write start addresses of a, b, c, d are respectively 20Ha + Ba, 20Ha
+ (Ha + Ba) / 2, 142Ha + Ba, 142Ha + (Ha + Ba) / 2. In this embodiment, writing of VA and HA is performed in the first field, and reduced screens a, b, c, and d are sequentially written in the second to fifth fields. Here, when writing the reduced screens a, b, c, and d, the clock frequency counted by the address counter is halved compared to when writing VA and HA, and the address counter is always preset at the leading edge of VA. If so, the count value of the address counter at the write start timing of the image portion (the portion excluding VA and HA) of the second to fifth fields is 10Ha + Ba / 2. However, each screen is actually written for each horizontal scanning line, and writing starts from the 22nd scanning line for the reduced screens b and d. Therefore, the coefficient value of the address counter at the writing start timing Is
10Ha + (Ha + Ba) / 2. Therefore, Purisetsuto value PR ₂ of the address counter of the second to fifth field, PR _3, PR _4, PR ₅ is calculated as the respective following. _{PR 2 = 20Ha + Ba- (10Ha} + Ba / 2) = 10Ha + Ba / 2 PR 3 = 20Ha + (Ha + Ba / 2- {10Ha + (Ha + Ba / 2} = 10Ha PR 4 = 142Ha + Ba-10Ha + Ba / 2 = 132Ha + Ba / 2 PR 5 = 142Ha + (Ha + Ba / 2− {10Ha + (Ha + Ba / 2) = 132H
a By setting the preset data as described above, each reduced screen can be written in the address area as shown in FIG. Hereinafter, the operation of each part of FIG. 1 will be described with reference to the timing charts of FIGS. D-FF108 converts the phase of the VA extraction signal to the HA extraction signal (▲
▼) to match the phase, and D-FF108
Is output to the field counter 109. On the other hand, a pulse synchronized with the falling edge of the PG input from the terminal 115 is output from the edge detector 110 having the configuration shown in FIG. 2A, and the multi-display command signal is synchronized with this pulse by the D-FF 141. Let me do. The counter 109 resets the edge at which the Q output of the D-FF 141 has become Lo with a pulse output from the edge detector 142 having the structure shown in FIG. 2A, and outputs the next field, that is, the odd field of each frame. (I), (ii), (ii)
i), (iv) and (v) are sequentially changed to L every one field period.
It is set to 0, and is composed of, for example, a shift register party. In FIG. 5, (i), (ii), (iii), (iv),
The period indicated by (v) indicates a period in which the outputs (i), (ii), (iii), (iv), and (v) of the field counter 109 are Lo. In the first field (i), the output of the AND 111 is Hi, and the selectors 112 and 113 each select the B-side input signal. Accordingly, the counted clock of the address counter 114 is the frequency obtained from the timing controller 26.
fsc clock is supplied. Terminal 115 'is a terminal to which the inverted signal PG of PG is input, and D-FF116 is ▲
At the falling edge of ▼, ▲ is sampled and supplied to the edge detection circuit 117 as a Q output. Edge detection circuit 1
17 is configured as shown in FIG. 2 (A), and detects only the falling edge, so that a pulse synchronized with the falling edge of ▼ immediately before the signal of the even field of each frame is input is output at a period of 525H. . On the other hand, if the address counter 114
Since the detector 140 outputs a negative pulse when the address of 63Ha is counted, the AND 118 outputs a negative pulse every time 263H and 262H elapse. The pulse of the 525H cycle is input to the preset terminal ▼ of the address counter 114 via the AND 118 and the selector 113 to preset the address counter. Therefore, the output (i) of the field counter 109 becomes L
At the timing of "o", the address counter is preset by the output pulse of the 263Ha detector 140. At this time, the output of AND111 is Hi and the output of inverter 119 is Lo.
Therefore, the data generator 121 operates and 0 is set as the preset data. On the other hand, (i) is input to OR 126, which gates the output of AND 127. ▲ ▼ and ▲ ▼ are input to AND127, and a signal of L0 is output only at HA and VA, and this signal is used as a memory write control signal (/ R) via AND128 as a field memory.
Input to 42 / R terminal. In the first field, signals are recorded in the memory 32 during the VA and HA periods by this signal (indicated by / R-1 in FIGS. 6, 7, and 8). In the field of FIG. 2, the output of the AND 111 becomes Lo, and the selectors 112 and 113 each output the signal input to the A side. Therefore, as the clock to be counted by the address counter 114, the clock of the frequency fsc is a T-type clock.
Frequency fs divided by 1/2 with flip-flop (T-FF) 130
The clock of c / 2 is input. On the other hand, a pulse synchronized with the falling edge of the triangle obtained by the edge detector 131 is used as a preset pulse of the address counter 114. On the other hand, since the output of the AND 111 is Lo, the OR 132 gates the output of the NAND gate (NAND) 133, that is, a signal that is Lo during periods other than HA and VA, and supplies the gate to the OR 134. T-FF135 is ▲
The signal is triggered by the falling edge of ▼ and switches between Hi and Lo every 1H. Output of AND136 is Lo at the start of the second field.
Since the falling edge is detected by the edge detector 137, T-FF is used in the second field.
The output of 135 becomes Lo in the first 1H. Since the period of VA is 20H, the output of T-FF135 is similarly L for the first 1H immediately after VA.
o. The T-FF 138 further divides the clock of fsc / 2 (represented by 1/2 fsc in FIG. 8) output from the T-FF 130 by 1/2 to obtain a clock of fsc / 4. This clock is gated by OR139 every 1H by the output of T-FF135, and further gated by OR134 other than the periods of HA and VA to become a write control signal of the memory 42. Output to terminal.
This write control signal is indicated by / R-3 in FIG.
The detail part is shown by / R-2,3 in FIG. In the second field, since the data generator 122 is operated, (10Ha + Ba / 2) is supplied as the preset data of the address counter 114, and the reduced screen a is stored in the memory as described above. Is stored in the address area a in FIG. Next, in the third field, the output of the T-FF 135 becomes Hi at the first 1H after the end of the VA, so that the write control signal becomes the sixth field.
As shown in FIG. The details are the same as in the second field. 10Ha is supplied from the generator 123 as the address preset data. As a result, the reduced screen b is stored in the address area shown in FIG. Thereafter, in the fourth field, the write control signal is the same as that in the second field, and (132Ha + Ba / 2) output from the data generator 124 is supplied as address preset data. In the fifth field, the write control signal is the same as in the third field, and 132Ha output from the data generator 125 is supplied as address preset data. Accompanying this, the reduced screens c and d are stored at the addresses shown in FIGS. 4c and 4d, and by the fifth field, the video signal for one field including the synchronization signal and the four reduced screens is stored in the field memory 42. Is stored. After the fifth field, the field memory 42 is always kept in the read state.
Outputs the input on the A side, the address counter 114 is preset by the output pulse of the edge detector 117 in the field next to the fifth field, and the preset data is 0.
Becomes In the next field, the address counter 114 is preset by the output pulse of the 263Ha detector 140, and the preset data becomes 0 in the same manner. As a result, in the next field after the fifth field, the synchronization signal stored at the address shown in FIG. 4 and the video signal for one field including four reduced screens are transmitted.
Reading is performed over 263H, and in the next field, reading is performed over 262H. In the above embodiment, since the preset values of the address counter at the time of writing the four reduced screens are different from each other, the four reduced screens can be arranged at desired positions of the composite screen, and It is no longer necessary to perform mapping. In addition, since the synchronization signal portion is written in a different field and counts pulses to be counted at different frequencies, the combined reduced screen is only provided by controlling the writing and reading of the memory without providing a special synchronization signal addition circuit. Can be added to the synchronization signal. In the present embodiment, the case where the reduced screen is combined has been described. However, the present invention is extremely effective when the same size screen is combined and arranged at a position different from at least one screen original screen. [Effects of the Invention] As described above, according to the video signal processing apparatus of the present invention, the combined position of a plurality of screens can be freely determined by simple addressing processing using an address counter. In addition, the synchronization signal can be added to the composite reduced screen only by controlling the writing of the memory without providing a pseudo synchronization signal addition circuit.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a main part of a VTR according to an embodiment of the present invention, and FIG. 2 (A) shows a specific structure of an edge detector in FIG. FIG. 2 (B) is a timing chart showing the operation of each unit in FIG. 2 (A), FIG. 3 (A) is a diagram showing a specific configuration of the area extraction circuit in FIG. 1, FIG. (B) is a timing chart showing the operation of each unit in FIG. 3 (A), FIG. 4 is a diagram showing the address arrangement of the composite screen by the VTR in FIG. 1, FIG. 5, FIG. 6, FIG. 8 is a timing chart showing waveforms of respective parts in FIG. 1, FIG. 9 is a diagram showing a configuration example of a conventional VTR reproducing system using a field memory, and FIG. 10 explains the operation of each part in FIG. It is a timing chart for. In the figure, HA and HB are rotary heads, 26 is a timing controller, 42 is a field memory, 106 is a horizontal synchronization area extraction circuit, 107 is a vertical synchronization area extraction circuit, 109 is a field counter, 112 and 113 are selectors, 114 is an address counter, Reference numerals 121, 122, 123, 124 and 125 denote preset data generators, respectively.

Claims (1)

(57) [Claims] An apparatus for processing images of a plurality of different fields, each of which has been reduced, so as to be displayed on the same screen, comprising: a memory capable of storing video signals for one field; and an address counter for determining a write address of the memory A first mode in which a first count clock of a predetermined frequency is supplied to the address counter and a synchronization signal is written to the memory; and a screen of a reduced image of each field to be displayed on the same screen. A plurality of preset values corresponding to the upper display position are provided to the address counter, and a second count clock having a frequency lower than the predetermined frequency is supplied to the address counter, and a synchronization signal is written in the first mode. Writing the reduced plurality of different field video signals to the memory Video signal processing apparatus and a memory control means and a second mode. 2. The address counter is further configured to also determine a read address of the memory, and the memory control unit supplies the first clock to the address counter and performs the first clock in the first and second modes. 2. The video signal processing device according to claim 1, wherein the synchronization signal and the video signal written in the memory are read.