JPH01151004A - Information recording and reproducing device - Google Patents

Abstract

PURPOSE:To prevent an erroneous erasing and to easily and surely erase by identifying that the operation of a special switch and the loading operation of a recording medium are both executed in a prescribed time interval and erasing all tracks based on the identified result. CONSTITUTION:When an erasing switch is operated in a prescribed time interval and a magnetic disk is charged to a device main body, an erasing detecting means 34 and a disk detecting means 31 identify that an erasing command operation is executed in a prescribed time. When an erasing detecting signal from the erasing detecting means 34 and a disk detecting signal from the disk detecting means 31 are both to an erasing command generating means 33, all track erasing commands are given from the erasing command generating means 33 to the erasing generating circuit. Thus, the erroneous erasing is prevented over all tracks and at the time of the erasing, the erasing can be easily and surely executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information recording and reproducing apparatus used for recording and reproducing, for example, photoelectrically converted image information on a recording medium such as a magnetic disk.

[Prior Art] In general, in this type of information recording and reproducing apparatus, when recording image information etc. on a recording medium, for example, one field of photoelectrically converted image information -<l- is recorded on a track. . Furthermore, a magnetic disk as a recording medium usually has a
It has a track and can store image information for 5o fields or 25 frames.

By the way, there are cases where the recorded information recorded on the recording medium such as the magnetic disk becomes unnecessary and it is desired to erase the recorded information from all tracks. For example, there are cases where it is desired to record new information in place of the information already recorded on a magnetic disk in order to effectively utilize the recording medium. In such a case, all tracks of recorded information are erased by loading a magnetic disk into the apparatus main body and turning on an erase switch.

[Problems to be Solved by the Invention] In erasing all tracks of the conventional magnetic disk as described above, there are the following problems. The above recorded information erasing operation forcibly erases the recorded information by turning on the erase switch, so if you operate the erase switch incorrectly and perform the erase operation by mistake, it may cause an irreversible situation. do not have. That is, in the conventional device, if the erase switch is pressed by mistake while a magnetic disk is loaded in the main body of the device, there is a problem in that all tracks of recorded information are erased. One solution to preventing such erroneous erasure is to provide two switches, a standby switch and an erase switch, and erase recorded information by operating these switches.

However, if two switches are used, the number of switches increases accordingly, resulting in an increase in cost. Furthermore, even if such measures are taken, if two switches are pressed, there is a possibility that all tracks will be erased.

Therefore, it is an object of the present invention to prevent erasing from occurring during normal operation even if the erase switch is turned on, to prevent erroneous erasing across all tracks, and to simplify the erasing operation. It is an object of the present invention to provide an information recording/reproducing device that can erase information reliably.

[Means for Solving the Problems] The present invention takes the following measures in order to solve the above problems and achieve the objectives. That is, a means is provided for identifying that both the operation of a specific switch and the operation of loading a recording medium are performed within a predetermined time interval, and based on the result of identification by this identification means, the All tracks will be deleted.

[Effects] By taking such measures, the following effects are achieved. Only when a specific switch is operated and a recording medium is loaded within a predetermined time interval,
Since the erasing intention is identified by the identifying means and the recorded information on all tracks on the recording medium is erased, even if the erasing switch is turned on outside the above-mentioned time interval, all tracks of recorded information can be erased by mistake. It can be prevented. Moreover, since the switch operation only requires turning on a single switch, the erasing operation is simple and can be easily and reliably erased.

[Example] FIG. 1 is a diagram showing an example of the present invention. In FIG. 1, ■ is an object, and 2 is a camera circuit. This camera circuit 2 takes an image of the subject 1, performs exposure control and video signal processing, and also generates a synchronization signal. 3 is a recording circuit which FM-modulates the video signal processed by the camera circuit 2 at a carrier frequency;
This is an RF multiplied signal. A recording amplifier 4 amplifies the RF signal from the recording circuit 3. 5 is a switching circuit, which connects the RF signal from the recording amplifier 4.
Either the doubled signal is applied to a recording/reproducing head 9 (described later) or the RF doubled signal from the recording/reproducing head 9 is applied to an amplifier 18 for reproducing the RF signal. That is, the switching circuit 5 switches from 0UTI to RE from the CPU 30, which will be described later.
After receiving the C/PLAY signal, the REC/PLAY signal becomes “H”.
o, the recording amplifier 4 is selected, and when the REC/PLAY signal is "L#", the playback amplifier 18 is selected. 6 is an encoder that detects the position of the recording/playback head 9. It outputs a HEAD signal to INI. 7 is a head access circuit, and CP
Input the 0N10FF signal to start or stop access from 0UT4 of U30, and also input the 0N10FF signal from 0UT5 of U30.
The head actuator 8 is accessed by inputting an F/R (forward/reverse) signal for sending the head to the inner or outer circumference of the magnetic disk 11. The head actuator 8 drives and controls a recording and reproducing head 9 for recording and reproducing the RF multiplied signal on a magnetic disk 11, which will be described later. The magnetic disk 11 is a thin circular magnetic recording medium that can store image information from the first track on the outermost track to the 50th track on the innermost track, and one image field is stored on each track. Image information for 10 minutes is stored. The erase signal generation circuit 12 receives an erase start from 0UT3 of the CPU 30, generates an erase signal for erasing recorded information on the magnetic disk 11, and sends it to the wide erase head IO via the head actuator 8. It has become. 13 is a disk detection switch, which detects the magnetic disk 11 when the magnetic disk 11 is loaded into the main body of the apparatus, and sends this detection signal to the INT of the CPU 30.
It is intended to be output to. Reference numeral 14 denotes a 50 track detection switch, which detects the 50th track on the innermost circumference of the magnetic disk 11 by turning "L" and outputs a detection signal to IN2 of the CPU 30. 15
is a PG detector which detects a rotation detection pulse as the magnetic disk 11 rotates and outputs it to the drive circuit 18. Drive circuit 1B is OU of CPU30
MOTORON signal from Tφ and the camera circuit 2
The synchronization signal s1 from the disk rotation motor 17 is inputted.
It is intended to drive the Therefore, the magnetic disk 11 rotates in conjunction with the rotation of the disk rotation motor 17, and the image signal of the subject 1 is transferred to the recording circuit 3. recording amplifier 4
The signal is converted into an RF signal via the switching circuit 5, and is recorded on the magnetic disk 11 by the recording/reproducing head 9.

Furthermore, information recorded on the magnetic disk 11 is erased by an erase signal input to the wide erase head IO. 18 is an erase switch, and when this erase switch is turned on,
Alternatively, an OFF signal is output to the INS of the CPU.

On the other hand, the above-described reproduction amplifier 19 inputs recorded information in the magnetic disk 11 from the recording/reproduction head 9 via the switching circuit 5 and amplifies the RF signal.

20 is an envelope detection circuit, and the reproduction amplifier 1
The RF multiplied signal envelope (envelope line) from 9 is detected. A comparator 21 receives an envelope signal s2 from the envelope detection circuit 20 and a reference signal s.
3 and the envelope signal s2 is the reference signal s.
When the envelope signal s2 is smaller than the reference signal s3, it outputs "H", and when the envelope signal s2 is smaller than the reference signal s3, it outputs "L".
It is converted into a digital signal. Therefore, when the output of the comparator 21 is "H", it is determined that the edge has been recorded, and when it is "L", it is determined that the edge has not been recorded. 21
is a latch circuit, which is set by inputting a digital signal from the comparator 21, reset by inputting a reset signal from 0UT6 of the CPU 30, and outputting the output signal from CP.
It is to be output to INO of U30.

That is, the purpose of the latch circuit 22 is that, if a small amount of the digitally converted recording signal exists, for example, as an unerased pulse signal, it is difficult to detect this unerased pulse signal. In other words, the latch circuit 22 is inserted and reset by 0UT6, and even if a pulse-like signal is output from the latch circuit 21 after the reset, INφ is set to II.
H11, the CPU 30 can easily detect the digitized recording signal.

FIG. 2 is a block diagram showing the internal functions of CPtJIO that controls the circuits etc. described above. The functions of this CPU 30 will be explained below. The disk detection means 31 inputs a detection signal from the disk detection switch 13 via an INT (interface), and controls the CPU operation mode control means 32.
An operation or stop mode switching signal is given to the erase command generating means 83, and an erase mode command is given to the erase command generating means 83. The erase switch detection means 34 is the erase switch 1
8 signals are inputted via the INS and given to the erasure command generation means 33. Therefore, when the erasure command generation means 33 receives both the detection signal from the disk detection means 31 and the signal from the CPU operation mode control means 32, it supplies them to the erasure signal generation circuit 12 via 0UT3. The 50 track switch detection means 35 inputs the signal from the 50 track detection 5W14 via IN2, and provides the detection result to the head access command means 37. The head position detection means 3B receives the HEAD signal from the encoder 6 via the INI and detects the head position. The head φ access command means 37 inputs signals from the head position detection means 36 and the 5o track switch detection means 35, gives an access 0N10FF signal to the head fist access circuit 7 via 0UT4, and also outputs the head access signal via 0UT5. The outer periphery or "" is used to give an F/R signal to the head access circuit 7 for sending to the inner periphery. The spindle motor rotation command means 38 provides an ON or OFF signal for motor rotation to the drive circuit 15 via OUTφ. The recording signal detection means 39 inputs the digitized recording signal from the latch circuit 21 via INφ,
It is designed to detect recording signals. The RAM 40 stores track number 1 and track information, which will be described later. Next, regarding the storage area of RAM 40, table-
This will be explained by ■.

Table 1 Table 1 is a memory map showing the storage area of the RAM 40. A 4-bit microcomputer is used for this RAM 40, and 4 bits, that is, 0b, are used for each address from address φφH to address φCH.
The 1st bit, 1st bit, 2nd bit, and 3rd bit are allocated to form a memory map. Each of the ml to 50th tracks of the magnetic disk 11 described above is assigned to the memory map. That is, the first track is assigned to the 0th bit of the address address, each track is assigned to each address sequentially, and finally the 1st bit of the address address φCH is assigned to the 0th bit of the address address.
The 50th track is assigned to the second track.

Further, address address φDH and address address φEH are for storing track NO. Here, address φDH stores the lower digits, and address φEH stores the higher digits. For example, when storing track 25 at address addresses φDH and φEH as shown in FIG.
．． Store 0101 in the lower digit. Also, when the bit corresponding to track NO0 is H”, it means that it has already been recorded.
When it is "L", it is unrecorded.

The ALU 41 performs arithmetic operations with each of the above-mentioned means. The latch reset command means 42 is
A signal is input from 41 and output to the reset terminal R of the latch circuit 21 via 0UT6.

Note that when the CPU operation mode control means 32 is in the stop mode, all sequence control is stopped and data memory is held.

Next, the operation of the apparatus constructed in this way will be explained with reference to FIGS. 4 to 9.

FIG. 4 is a flow diagram showing the erase operation from the standby state of the CPU 30. First, it is assumed that the CPU 30 is in a stop mode, that is, waiting for a disk to be loaded. When the magnetic disk 11 is loaded into the main body of the recording/reproducing apparatus, the DISKIN sensor is turned ON by the disk detection 5W13. Then, the signal “
H” is sent to the disk detection means 31, and as a result, C
The PU operation mode control means 32 is switched to L'', the stop mode is canceled, and the mode is switched to the normal operation mode (step A).

Next, the signal from the erase switch 1B is input to IN3 of the CPU 30.
The signal is input to the erase switch detection means 34 via the erase switch 18, and it is determined whether the erase switch 18 is ON or not (step B). The erase switch 18 erases the magnetic disk 11.
When it is turned on when loading the magnetic disk 11, all tracks on the magnetic disk 11 are erased (step C). This erasing of all tracks will be explained in detail with reference to FIGS. 5 to 7.

Figure 5 is a flow diagram showing all track erasing, Figure 6 is HM
(head home position), and FIG. 7 is a flow diagram showing one track reverse.

In the all-track erasing shown in FIG. 5, HM (head home position) is first performed (step D). Here, HM refers to the reference position of the head.

Specifically, this is the 50th track position on the innermost circumference. This HM
will be explained based on FIG. First, HM and C
H” is applied to the head access circuit 7 from 0UT4 and 0UT5 of the PU 30 (step D1), and the head
The access circuit 7 operates, and the head is thereby sent to the inner circumference of the magnetic disk 11. Then, the head is sequentially sent to the inner circumference until it detects "L" set at the 50th track position of the magnetic disk 11 by the 50th track detection 5W14 (step D2). And 'L from 0UT4
1 to the head access circuit 7, the head access circuit 7 is operated, and the head is stopped at the 50 track position (step D3). Furthermore, in the track NO0 of the memory map shown in Table 1, that is, the 4-bit BCD code, 5 is stored in the address φEH and 0 is stored in the address φDH.
ET.

Then, OUTφ is output from the spindle motor rotation command means 38.
"H" is applied to the drive circuit 16 via (step CI). “Ho” from OUTφ to the drive circuit 16 and synchronization signal s1 from the camera circuit 2 and the PG detector 1
A rotation detection pulse is input from 5, the disk rotation motor 17 is driven, and the magnetic disk 11 is rotated by the disk rotation motor 17. And erase command generation means 3
When the erase detection signal from the erase SW detection means 34 and the operation mode signal from the CPU operation mode control means 32 are both input to 3, an erase command signal is generated. Then, this erase command signal “H2 is transmitted via 0UT3”
H'' is applied to the erase signal generating circuit 12, and the erase signal generating circuit 12 generates an erase signal (step C2).

Therefore, an erase signal is applied to the magnetic disk 11 via the wide erase head 10.

Then, a timer is used to erase the recorded information on the magnetic disk 11, that is, a time of 1/60 seconds or more (
Step C3). Next, the track information bit corresponding to the track number is cleared (step C4). For example, when track number 9 is 25, address address φ6
The 0BLtth of the H memory is cleared by changing it from "H" to "L#." After that, it is determined whether the track is 1 (step C5). In other words, if the track is not 1, the l track reverse is repeated (
Step E).

FIG. 7 is a flow diagram showing one track reverse. First, when 'H' from 0UT4 and 'L' from 0UT5 are applied to the access circuit 7 (step El),
The head access motor 8 rotates in reverse, and the head is sent toward the outer circumference. Then, the HEAD signal from encoder 6 is
It is determined whether INI is "L" (step E2), and it is further determined whether INI is H° (step E3). In other words, “L” from the current track position
It detects the edge from "H" to "H" and detects that it has been reversed by one track. Then, "L" from 0UT4 is applied to the access circuit 7 to stop the head (step E4). Then, the value obtained by subtracting 1 from the current track is stored as track number 0, and the next command of 1 track reverse shown in FIG. 15 is returned.

When the track is 1, "L" from 0UT3 is applied to the erase signal generation circuit 12 (step CB), and the erase operation is completed. Further, "L" from OUTφ is applied to the drive circuit I6 (step C7), and the disk rotation motor 17 is stopped.

Therefore, erasing starts from the innermost circumference (50th track) of the magnetic disk 11, all information recorded on the recording medium at the outermost circumference (first track) is erased, and erasing of all tracks is completed, and the state returns to stop mode. (Step H).

On the other hand, when the aforementioned ERASE SW is OFF, empty track detection is performed (step F). This empty track detection will be explained in detail with reference to FIGS. 8 and 9. First, in empty track detection, HM
That is, the head is moved to the 50 track position (step D). Note that the details of this HM are as described above. Furthermore, drive circuit 16
to turn on the spindle motor (step Fl
). Also, 'L' from 0UTI is applied to the switching circuit 5, and P
Switch to LAY (playback) mode. Therefore, the recording signal is reproduced by the recording/reproducing head 9, and the switching circuit 5. Reproduction amplifier 19. Envelope detection circuit 20. The signal is input to the latch circuit 22 via the comparator 21. Next, "Ho" from 0UT8 is applied to the latch circuit 22 to reset it (step F3).Then, the timer sets the latch circuit 21 to the latch circuit 21 for a sufficient period of time, that is, 5
Set a reset time of about 00 μs (step F4
).

In step F5), the digitized recording signal is input to INφ.The timer determines whether recording has been made on one round of the track or not. (Step F5.
5). Thereafter, it is determined whether INφ is "H#" (step F6).

When INφ is "H", that is, the track has already been recorded, the bit corresponding to track No. 1 in the memory map is cleared (step F7). Further, when INO is "L", that is, unrecorded, a bit corresponding to the track number of the memory map is set (step FB). Further, it is determined whether the track No. 0 is 1 (step F9).

If track NO1 is not 1, l-track reverse is performed based on the flow diagram of FIG. 6 described above, and step F31. :RETL is executed repeatedly. Track No.
When 1 is l, 'L' from OUTφ is applied to the drive circuit 1B, and the SPM (spindle motor) is turned OF.
F (step F10).

Furthermore, it is determined whether the bit corresponding to track No. 1 is 1 (step F11). When the bit corresponding to track No. 9 is 71'', one track forward is performed (step F12).

FIG. 9 is a diagram showing ■Track forward.

That is, H1 from 0UT4 and “H” from 0UT5.
" is applied to the head access circuit 7, and the access is reversed (step Gl). Then, it is determined whether INI is "L" (step G2), and it is further determined whether INI is "Ho" (step G1). Step G3). Then change 0UT4 “
L" and stop the head (step G4).

Then, the track number 1 is set to the value obtained by adding 1 to the current track, step G5), 1) rack forwarding is completed, and the process returns to step Fil. Furthermore, when the bit corresponding to track NO0 is "0", empty track detection is ended and the state is set to stop mode (step H).
, the initial operation ends (step J).

As described above, according to this embodiment, when the erase switch 18 is operated within a predetermined time period and the magnetic disk 11 is loaded into the main body of the apparatus, the erase detecting means 34 and the disk detecting means 31 erase the data for a predetermined period of time. It is identified that the erase command operation was performed within the period. The erase detection signal from the erase switch detection means 34 and the disk detection signal from the disk detection means 31 are both transmitted to the erase command generation means 3.
3, an all-track erase command is given from the erase command generation means 33 to the erase generation circuit 12. Then, an erase signal is generated by the erase generator 12, and the erase signal is applied to the wide erase head 10, thereby erasing all tracks on the recording medium. Note that even if the erase switch 18 is operated during normal operation, the data will not be erased, and erroneous erasure of all tracks on the magnetic disk 11 can be prevented. Moreover, the switch operation can be performed by operating a single erase switch 18, and the erase operation is simple and can be easily and reliably erased.

Note that the present invention is not limited to the embodiments described above, and for example, the erasing switch 18 may be a SW for erasing only, or may be a switch for other switches (shutter lease SW, etc.).
But that's fine. Of course, various other modifications can be made without departing from the gist of the invention.

[Effects of the Invention] According to the present invention, a means for identifying that both the operation of a specific switch and the operation of loading a recording medium are executed within a predetermined time interval is provided, and the result of the identification means is Based on this, all tracks on the recording medium are erased, so during normal operation, even if the erase switch is turned on, erasure is not performed, preventing erroneous erasure of all tracks. Easy to operate and erase.

In some cases, it is possible to provide an information recording/reproducing device that can be easily and reliably erased.

[Brief explanation of the drawing]

1 to 9 show an embodiment of the present invention. FIG. 1 is a diagram showing the configuration of the present invention, FIG. 2 is a diagram showing the internal functions of the CPU 30, and FIG. Diagram showing storage,
FIG. 4 is a diagram showing the erase operation from the standby state of the CPU, FIG. 5 is a flow diagram showing all track erasing, FIG. 6 is a diagram showing HM, FIG. 7 is a flow diagram showing l-track reverse, and FIG. FIG. 8 is a flowchart showing empty track detection, and FIG. 9 is a flowchart showing first track forwarding. ■...Subject, 2...Camera circuit, 3...Recording circuit, 4...Recording amplifier, 5...Switching circuit, 6...
Encoder, 7... Head access circuit, 8... Head-actuator, 9... Recording/reproducing head, 10
...Erasing head, 11...Magnetic disk, 12...
- Erasing signal generation circuit, 18...disk detection switch, 14...50 track detection switch, 15...P
G detector, 16... Drive circuit, 17... Disk rotating motor, 18... Erase switch, 19... Reproduction amplifier, 20... Envelope detection circuit, 21...
・Comparator, 22...Latch circuit, 80...C
PU, 31...Disk detection means, 32...CPU
Operation mode control means, 88... Erasing command generating means, 84... Erasing switch detecting means, 35...5
0 track switch detection means, 3B... Head position detection means, 37... Head access command means, 38.
...Spindle motor rotation command means, 39.. Recording signal detection means, 40..RAM, 41..CPU. 42... Latch reset command means. Applicant's agent Patent attorney Jun Tsuboi Figure 2 Figure 3 Figure 4 Figure 6 Figure 7 Figure 9

Claims (1)

[Claims] means for identifying that both the operation of the specific switch and the operation of loading the recording medium are performed together within a predetermined time interval, and all tracks on the recording medium are identified based on the result identified by this means. An information recording/reproducing device comprising: erasing means.