JPH0115017B2 - - Google Patents

Info

Publication number
JPH0115017B2
JPH0115017B2 JP56038229A JP3822981A JPH0115017B2 JP H0115017 B2 JPH0115017 B2 JP H0115017B2 JP 56038229 A JP56038229 A JP 56038229A JP 3822981 A JP3822981 A JP 3822981A JP H0115017 B2 JPH0115017 B2 JP H0115017B2
Authority
JP
Japan
Prior art keywords
layer
capacitance
sensor element
oxide film
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56038229A
Other languages
Japanese (ja)
Other versions
JPS57153254A (en
Inventor
Teruyoshi Mihara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nissan Motor Co Ltd
Original Assignee
Nissan Motor Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nissan Motor Co Ltd filed Critical Nissan Motor Co Ltd
Priority to JP3822981A priority Critical patent/JPS57153254A/en
Publication of JPS57153254A publication Critical patent/JPS57153254A/en
Publication of JPH0115017B2 publication Critical patent/JPH0115017B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01NINVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N27/00Investigating or analysing materials by the use of electric, electrochemical, or magnetic means
    • G01N27/02Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance
    • G01N27/22Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance by investigating capacitance
    • G01N27/226Construction of measuring vessels; Electrodes therefor

Description

【発明の詳細な説明】 本発明は、半導体基板上に半導体層から成る一
対の対向電極を備えて該対向電極間静電容量から
液状又はガス媒体の性状を検出する静電容量セン
サ素子に関する。静電容量センサ素子はそのほか
実開昭51−139657号公報に開示されるように静電
容量変化から液面を検出する装置に用いるなど従
来より知られている。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a capacitive sensor element that includes a pair of opposing electrodes made of a semiconductor layer on a semiconductor substrate and detects the properties of a liquid or gaseous medium from the capacitance between the opposing electrodes. In addition, capacitance sensor elements have been known for use in devices that detect liquid levels from changes in capacitance, as disclosed in Japanese Utility Model Application Publication No. 51-139657.

この種のセンサ素子としては、第1図及び第2
図に示す構造のものを本出願人は既に提案してい
る(昭和56年3月9日付特許願56−33629(特開昭
57−148242号公報参照))。面方位(100)の単結
晶P型シリコン基板1にN層を形成し、異方性エ
ツチングよるV字形溝の堀込みでN層を櫛歯状に
分離して対向電極2,3を形成し、溝部表面には
酸化膜4を形成し、対向電極2,3の頂部の酸化
膜をエツチング除去してアルミニウム等のリード
電極5,6を形成する。この構造により、対向電
極2,3はシリコン基板1との間がPN接合によ
り夫々分離され、V字形溝により比較的小面積基
板上に静電容量を大きくした分離がなされ、検出
媒体中にセンサ素子を浸漬させることによりその
V字形溝を埋める検出媒体の性状が対向電極2,
3間の静電容量変化として検出される。例えば、
対向電極間静電容量から液状又はガス状媒体の誘
電率測定が可能となるし、ガスホール(ガソリン
とアルコールの混合物)のようにアルコール濃度
によつて誘電率εの変化する系ではアルコール濃
度測定を可能にする。
This type of sensor element is shown in Figures 1 and 2.
The applicant has already proposed the structure shown in the figure (Patent Application No. 56-33629 dated March 9, 1982
57-148242)). An N layer is formed on a single-crystal P-type silicon substrate 1 with a plane orientation of (100), and the N layer is separated into comb-like shapes by digging V-shaped grooves by anisotropic etching to form counter electrodes 2 and 3. An oxide film 4 is formed on the surface of the groove, and the oxide film on the top of the counter electrodes 2, 3 is removed by etching to form lead electrodes 5, 6 made of aluminum or the like. With this structure, the counter electrodes 2 and 3 are separated from the silicon substrate 1 by the PN junction, and the V-shaped groove provides separation with a large capacitance on the substrate with a relatively small area. The nature of the detection medium that fills the V-shaped groove by immersing the element is determined by the counter electrode 2,
It is detected as a change in capacitance between 3 and 3. for example,
It is possible to measure the dielectric constant of liquid or gaseous media from the capacitance between opposing electrodes, and in systems where the dielectric constant ε changes depending on the alcohol concentration, such as gas holes (mixtures of gasoline and alcohol), alcohol concentration can be measured. enable.

しかしながら、このような従来の静電容量セン
サ素子は、対向電極2,3とシリコン基板1を
夫々PN接合により分離するため、検出媒体によ
る基板1の汚れや湿気からPN接合の劣化を起
し、対向電極2,3間に基板1を通したリーク電
流iLが増大する問題があつた。このリーク電流iL
は高温になるほど増加し、125℃以上では急増し
て測定精度に大きく影響する。
However, in such a conventional capacitive sensor element, since the counter electrodes 2 and 3 and the silicon substrate 1 are separated by a PN junction, the PN junction may deteriorate due to dirt or moisture on the substrate 1 caused by the detection medium. There was a problem in that the leakage current i L passing through the substrate 1 between the opposing electrodes 2 and 3 increased. This leakage current i L
increases as the temperature increases, and increases rapidly above 125°C, greatly affecting measurement accuracy.

本発明は、半導体基板と対向電極を絶縁膜で分
離することにより、従来の問題点を解消した静電
容量センサ素子を提供することを目的とする。
SUMMARY OF THE INVENTION An object of the present invention is to provide a capacitive sensor element that solves the conventional problems by separating a semiconductor substrate and a counter electrode with an insulating film.

第3図は本発明の一実施例を示す断面構造であ
る。多結晶シリコン基板7の表面に酸化膜8を形
成し、その上に一定間隔に面方位(100)のP型
単結晶シリコンの対向電極9,10を配列する。
上述の酸化膜8はシリコン基板7と対向電極9,
10間の絶縁を得るもので、例えば1μmの膜厚
にして対向電極9,10とシリコン基板7間にリ
ーク電流の発生が無くまた耐圧を持つ絶縁性能を
持つようにされ、またシリコン基板7の温度上昇
にも影響されない絶縁性能を持つように形成され
る。この対向電極9,10の分離は異方性エツチ
ングによる空気層分離とし、エツチング面には酸
化膜11を形成している。対向電極9,10の頂
部表面には高濃度領域の低抵抗層12を形成し、
この低抵抗層12を接続部としてアルミニウム電
極13,14を対向電極9,10に接続してい
る。従つて対向電極9,10は絶縁膜8及び多結
晶シリコン基板7により絶縁分離され、従来の
PN接合分離に比して高い絶縁抵抗及び高耐圧に
なり、静電容量センサとしては浮遊容量分になる
分離容量が低減する。
FIG. 3 is a cross-sectional structure showing one embodiment of the present invention. An oxide film 8 is formed on the surface of a polycrystalline silicon substrate 7, and opposing electrodes 9 and 10 made of P-type single crystal silicon with a plane orientation of (100) are arranged at regular intervals thereon.
The above-mentioned oxide film 8 has a silicon substrate 7 and a counter electrode 9,
For example, the thickness of the film is 1 μm, so that there is no leakage current between the opposing electrodes 9, 10 and the silicon substrate 7, and the insulation performance has a withstand voltage. It is formed to have insulation performance that is unaffected by temperature rises. The opposing electrodes 9 and 10 are separated by air layer separation by anisotropic etching, and an oxide film 11 is formed on the etched surface. A low resistance layer 12 in a high concentration region is formed on the top surface of the counter electrodes 9 and 10,
Aluminum electrodes 13 and 14 are connected to counter electrodes 9 and 10 using this low resistance layer 12 as a connection portion. Therefore, the counter electrodes 9 and 10 are insulated and separated by the insulating film 8 and the polycrystalline silicon substrate 7, unlike the conventional
Compared to PN junction isolation, it has higher insulation resistance and higher breakdown voltage, and as a capacitive sensor, the isolation capacitance that becomes stray capacitance is reduced.

本実施例におけるセンサ素子は、第4図に示す
製造工程により実現される。面方位(100)のN
形単形晶シリコン基板15の表面にボロンをイオ
ン注入して1018〜1019/cm3の高濃度領域のP+層1
6を厚さ1〜2μmに形成する(第4図a)。P+
16表面に低濃度のエピタキシヤル成長層(P-
17を形成する(第4図b)。このP-層17は、
第3図における対向電極9,10を成す領域のた
め、異方性エツチングによる空気層分離を完全に
すること及び所期の電極面積にする上で厚さ制御
を正確にする必要がある。また、P-層17の濃
度は可能な限り低くし、異方性エツチングにおけ
る堀込み速度を高める。実用上はP-層濃度を
1016/cm3以似に抑えれば良く、この濃度での形成
は容易である。
The sensor element in this example is realized by the manufacturing process shown in FIG. N of plane direction (100)
Boron ions are implanted into the surface of the monomorphic silicon substrate 15 to form a P + layer 1 in a high concentration region of 10 18 to 10 19 /cm 3 .
6 to a thickness of 1 to 2 μm (Fig. 4a). Low concentration epitaxial growth layer (P - ) on the surface of P + layer 16
17 (Figure 4b). This P - layer 17 is
For the regions forming the counter electrodes 9 and 10 in FIG. 3, it is necessary to completely separate the air layer by anisotropic etching and to precisely control the thickness to obtain the desired electrode area. Furthermore, the concentration of the P - layer 17 is made as low as possible to increase the digging speed in anisotropic etching. In practice, the P -layer concentration is
It is sufficient to suppress the concentration to 10 16 /cm 3 or less, and formation at this concentration is easy.

次に、P-層17表面に酸化膜18を形成する
(第4図c)。この酸化膜18の厚さは絶縁性から
決められ、例えば1μmにされる。酸化膜18表
面には減圧気相成長法やスパツタリングにより多
結晶シリコン層19を形成する(第4図d)。こ
のシリコン層19は最終的には基板7を成すもの
であるから、充分な強度を持つ厚さ、例えば
150μm〜300μmにする。シリコン層19の表面
に酸化膜20を形成する(第4図e)。この酸化
膜20は次のN層15のエツチング工程でシリコ
ン層19が侵されるのを防ぐマスキング材を目的
とし、その厚さは約1μmにされる。
Next, an oxide film 18 is formed on the surface of the P - layer 17 (FIG. 4c). The thickness of this oxide film 18 is determined based on its insulation properties, and is set to, for example, 1 μm. A polycrystalline silicon layer 19 is formed on the surface of the oxide film 18 by low pressure vapor deposition or sputtering (FIG. 4d). Since this silicon layer 19 will ultimately form the substrate 7, it should have a thickness that has sufficient strength, e.g.
The thickness should be 150 μm to 300 μm. An oxide film 20 is formed on the surface of the silicon layer 19 (FIG. 4e). This oxide film 20 is used as a masking material to prevent the silicon layer 19 from being attacked in the next etching process of the N layer 15, and its thickness is approximately 1 μm.

次に、出発母材であつたN層15をアルカリエ
ツチングにより除去する(第4図f)。このアル
カリエツチングは、後の異方性エツチングと同じ
エツチング条件にされ、エチレンジアミン:ビロ
カテコール:水を重量比で25:17:3にした温度
110℃の液中で行なわれ、エツチングはP+層16
表面で自動的に終る。
Next, the N layer 15, which was the starting base material, is removed by alkali etching (FIG. 4f). This alkaline etching was carried out under the same etching conditions as the subsequent anisotropic etching, with a temperature of ethylenediamine:birocatechol:water in a weight ratio of 25:17:3.
Etching is carried out in a liquid at 110℃, and the etching is performed on the P + layer 16.
Closes automatically on the surface.

次に、沸酸+硝酸系のエツチング液を使用し、
P+層16をフオトエツチングで対向電極パター
ンに刻む(第4図g)。電極パターンは夫々<110
>方向に延びるように設定するのが望ましい。こ
のフオトエツチングに使用されるフオトレジスト
21をマスクとして上記アルカリエツチングに同
じ条件で異方性エツチングをP-層17に施し、
対向電極9,10の分離を行なう(第4図h)。
このエツチング液は面方位(111)に対してはエ
ツチングが殆んど進まないことから、分離溝は
(111)面で四方を囲まれた正確なVカツトとな
り、電極パターンが<110>方向の場合には
(111)面と(100)面のなす角度は54.7゜になる。
Next, use an etching solution containing fluoric acid and nitric acid.
The P + layer 16 is etched into a counter electrode pattern by photoetching (FIG. 4g). Each electrode pattern is <110
It is desirable to set it so that it extends in the > direction. Using the photoresist 21 used in this photoetching as a mask, the P - layer 17 is subjected to anisotropic etching under the same conditions as the alkali etching described above.
The opposing electrodes 9 and 10 are separated (FIG. 4h).
Since this etching solution hardly etches in the (111) plane, the separation groove becomes a precise V-cut surrounded on all sides by the (111) plane, and the electrode pattern is oriented in the <110> direction. In this case, the angle between the (111) and (100) planes is 54.7°.

次に、分離された対向電極17(9),17
(10)の表面を保護するため、再度に酸化膜2
2を形成し、対向電極の頂面酸化膜の一部を除去
して電極接合面23を形成する(第4図i)。電
極接合面23の形成と同様に基板19側の酸化膜
20を除去する。電極接合面23に厚さ1μmの
アルミニウム電極24を形成して第3図に示す構
造になる(第4図j)。
Next, the separated counter electrodes 17 (9), 17
In order to protect the surface of (10), an oxide film 2 is added again.
2 is formed, and a part of the top oxide film of the counter electrode is removed to form an electrode bonding surface 23 (FIG. 4i). Similarly to the formation of the electrode bonding surface 23, the oxide film 20 on the substrate 19 side is removed. An aluminum electrode 24 having a thickness of 1 μm is formed on the electrode bonding surface 23 to obtain the structure shown in FIG. 3 (FIG. 4 j).

なお、第4図に示す工程にあつて対向電極17
(9),17(10)と多結晶シリコン19との絶
縁に酸化膜(SiO2)18を形成する場合を示す
が、異方性エツチングに耐える絶縁膜、例えば窒
化シリコン(SiN4)に代替可能である。
In addition, in the process shown in FIG. 4, the counter electrode 17
(9), 17 (10) and the case where an oxide film (SiO 2 ) 18 is formed to insulate the polycrystalline silicon 19 is shown, but an insulating film that can withstand anisotropic etching, such as silicon nitride (SiN 4 ), can be used instead. It is possible.

また、対向電極の分離溝堀込みは異方性エツチ
ングに代えて通常の沸酸+硝酸系のエツチング液
によることもできる。この場合の構造は第5図に
示すように、分離溝が垂直面を持つことが第3図
と異なる部分であるが、対向電極9,10と基板
7との分離を絶縁膜8により行い第3図の場合と
同様に完全な分離を得て従来の問題点を解消でき
る。
Furthermore, instead of anisotropic etching, the separation grooves for the counter electrode can be dug using a normal etching solution of fluoric acid and nitric acid. The structure in this case is different from that in FIG. 3 in that the separation groove has a vertical surface, as shown in FIG. As in the case of FIG. 3, complete separation can be obtained and the conventional problems can be solved.

また、対向電極はエピタキシヤル成長層に限ら
れるものでなく、第6図に示すように多結晶シリ
コンを使つた対向電極25,26にして同等の作
用効果を得ることができる。この場合、対向電極
25,26は基板27上に酸化膜8を成長させた
後、多結晶シリコン層を形成してエツチング分離
することで実現される。本実施例においても対向
電極25,26と基板27とは絶縁膜8による完
全な分離を得て従来の問題点を解消できる。な
お、基板27は多結晶シリコンに限られるもので
なく、単結晶シリコンにすることもできる。
Furthermore, the counter electrodes are not limited to epitaxially grown layers, and as shown in FIG. 6, counter electrodes 25 and 26 made of polycrystalline silicon can be used to obtain the same effect. In this case, the opposing electrodes 25 and 26 are realized by growing an oxide film 8 on the substrate 27, then forming a polycrystalline silicon layer and separating it by etching. Also in this embodiment, the counter electrodes 25, 26 and the substrate 27 are completely separated by the insulating film 8, so that the conventional problems can be solved. Note that the substrate 27 is not limited to polycrystalline silicon, but may also be made of single-crystalline silicon.

以上のとおり、本発明よれば半導体基板と対向
電極を絶縁膜8で分離するため、対向電極間のリ
ーク電流が少なくしかも湿気や汚れに強い安定し
た絶縁分離構造にできる効果がある。また、高温
媒体中に置いて安定した静電容量検出が可能とな
る。
As described above, according to the present invention, since the semiconductor substrate and the counter electrode are separated by the insulating film 8, the leakage current between the counter electrodes is reduced, and a stable insulation separation structure that is resistant to moisture and dirt can be achieved. Furthermore, stable capacitance detection is possible when placed in a high-temperature medium.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の静電容量センサ素子の平面図、
第2図は第1図におけるA−A′線に沿つた断面
図、第3図は本発明の一実施例を示す要部断面
図、第4図は第3図に示す素子構成のための工程
図、第5図及び第6図は本発明の他の実施例を示
す要部断面図である。 7……多結晶シリコン基板、8……絶縁膜、
9,10……対向電極、11……絶縁膜、12…
…低抵抗層、13,14……アルミニウム電極、
25,26……対向電極、27……基板。
Figure 1 is a plan view of a conventional capacitive sensor element.
2 is a sectional view taken along line A-A' in FIG. 1, FIG. 3 is a sectional view of essential parts showing one embodiment of the present invention, and FIG. The process drawings and FIGS. 5 and 6 are sectional views of main parts showing other embodiments of the present invention. 7... Polycrystalline silicon substrate, 8... Insulating film,
9, 10... Counter electrode, 11... Insulating film, 12...
...Low resistance layer, 13,14...Aluminum electrode,
25, 26... Counter electrode, 27... Substrate.

Claims (1)

【特許請求の範囲】 1 半導体基板表面に絶縁膜を有し、この絶縁膜
上に半導体層から成る一対の対向電極を空気層分
離により形成し、上記対向電極間の静電容量から
該対向電極間の媒体の性状を検出することを特徴
とする静電容量センサ素子。 2 特許請求の範囲第1項において、半導体基板
及び対向電極は少なくとも一方を多結晶シリコン
にしたことを特徴とする静電容量センサ素子。 3 特許請求の範囲第1項において、対向電極は
面方位(100)の単結晶シリコンから異方性エツ
チングにより分離形成したことを特徴とする静電
容量センサ素子。
[Claims] 1. An insulating film is provided on the surface of a semiconductor substrate, a pair of opposing electrodes made of a semiconductor layer are formed on the insulating film by air layer separation, and the capacitance between the opposing electrodes is determined by the capacitance between the opposing electrodes. A capacitive sensor element characterized by detecting the properties of a medium between. 2. The capacitance sensor element according to claim 1, wherein at least one of the semiconductor substrate and the counter electrode is made of polycrystalline silicon. 3. The capacitance sensor element according to claim 1, wherein the counter electrode is formed separately from single crystal silicon with a plane orientation of (100) by anisotropic etching.
JP3822981A 1981-03-17 1981-03-17 Electrostatic capacity sensor Granted JPS57153254A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3822981A JPS57153254A (en) 1981-03-17 1981-03-17 Electrostatic capacity sensor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3822981A JPS57153254A (en) 1981-03-17 1981-03-17 Electrostatic capacity sensor

Publications (2)

Publication Number Publication Date
JPS57153254A JPS57153254A (en) 1982-09-21
JPH0115017B2 true JPH0115017B2 (en) 1989-03-15

Family

ID=12519471

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3822981A Granted JPS57153254A (en) 1981-03-17 1981-03-17 Electrostatic capacity sensor

Country Status (1)

Country Link
JP (1) JPS57153254A (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3310643C2 (en) * 1983-03-24 1986-04-10 Karlheinz Dr. 7801 Schallstadt Ziegler Pressure sensor
JP2002243689A (en) * 2001-02-15 2002-08-28 Denso Corp Capacity-type humidity sensor and method for manufacturing the same
JP2002243690A (en) * 2001-02-20 2002-08-28 Denso Corp Capacitance type humidity sensor and method for manufacturing the same

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57148242A (en) * 1981-03-09 1982-09-13 Nissan Motor Co Ltd Electrostatic capacity sensor

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57148242A (en) * 1981-03-09 1982-09-13 Nissan Motor Co Ltd Electrostatic capacity sensor

Also Published As

Publication number Publication date
JPS57153254A (en) 1982-09-21

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