JPH01147896A - Manufacture of multilayer printed circuit board - Google Patents
Manufacture of multilayer printed circuit boardInfo
- Publication number
- JPH01147896A JPH01147896A JP30647887A JP30647887A JPH01147896A JP H01147896 A JPH01147896 A JP H01147896A JP 30647887 A JP30647887 A JP 30647887A JP 30647887 A JP30647887 A JP 30647887A JP H01147896 A JPH01147896 A JP H01147896A
- Authority
- JP
- Japan
- Prior art keywords
- copper foil
- plate
- inner layer
- copper
- laminated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 33
- 239000011889 copper foil Substances 0.000 claims abstract description 30
- 239000003822 epoxy resin Substances 0.000 abstract description 4
- 229920000647 polyepoxide Polymers 0.000 abstract description 4
- 239000011521 glass Substances 0.000 abstract description 3
- 238000010030 laminating Methods 0.000 abstract description 2
- 239000000758 substrate Substances 0.000 abstract description 2
- 239000011800 void material Substances 0.000 abstract 3
- 238000000465 moulding Methods 0.000 abstract 2
- 230000002093 peripheral effect Effects 0.000 abstract 2
- 238000003475 lamination Methods 0.000 abstract 1
- 230000037303 wrinkles Effects 0.000 description 5
- 230000000052 comparative effect Effects 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 229910000831 Steel Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【発明の詳細な説明】 く技術分野〉 本発明は多層印刷回路板の製法に関するものである。[Detailed description of the invention] Technical fields> The present invention relates to a method for manufacturing multilayer printed circuit boards.
〈従来技術〉
従来、多層印刷回路板は回路形成された内層板と銅張積
層板又は銅箔とをグリプレグを介して積層し外層に回路
形成し、スルホール孔郷を設けて製品としていた。<Prior Art> Conventionally, a multilayer printed circuit board was manufactured by laminating an inner layer board on which a circuit was formed and a copper-clad laminate or copper foil via Gripreg, forming a circuit on the outer layer, and providing through-hole holes.
内層板には1ユニツトの回路又は複数ユニットの回路を
持つものが使用されるが、後者ではプリプレグ及び積層
面からボイドの離脱ができない、回路ユニット間に凹み
が生じ、板厚精度が確保できない、更に15〜30μの
銅箔を積層するケースでは銅箔にシワがでる、ドライフ
ィルムなど保護膜の密着が不完全になシ回路形成不良の
原因となる、などして製品不良の原因になっていた。The inner layer board has one circuit or multiple circuit units, but in the latter case, voids cannot be removed from the prepreg and laminated surfaces, dents occur between circuit units, and board thickness accuracy cannot be ensured. Furthermore, in cases where copper foil of 15 to 30 μm is laminated, wrinkles may appear on the copper foil, and the adhesion of protective films such as dry films may be incomplete, causing poor circuit formation, resulting in product defects. Ta.
〈発明の目的〉
本発明はかかる問題を解決するためなされたもので、積
層間のボイド残留のなく、板厚精度にすぐれ、更に銅箔
使用時においては銅箔にシワが出すドライフィルムの密
着が完全のため外層回路形成時の不良が回避される多層
印刷回路板の製法を提供せんとするものである。<Purpose of the Invention> The present invention has been made to solve such problems, and has excellent board thickness accuracy without leaving voids between laminated layers, and also improves adhesion of dry film that causes wrinkles in copper foil when copper foil is used. It is an object of the present invention to provide a method for manufacturing a multilayer printed circuit board in which defects are avoided during the formation of outer layer circuits due to the completeness of the process.
〈発明の開示〉
本発明の要旨は前記の通シであり、以下詳細に説明する
。第1図は本発明に係る実施例の内層板であって同一の
回路ユニット(1)が4個配置され、該回路ユニット間
(2)及び外周部(3)には直径5簡の円形の銅箔片(
4)が付着されている。<Disclosure of the Invention> The gist of the present invention is as described above, and will be explained in detail below. FIG. 1 shows an inner layer board according to an embodiment of the present invention, in which four identical circuit units (1) are arranged, and between the circuit units (2) and on the outer periphery (3) are circular Copper foil piece (
4) is attached.
実施例1に説明した通シ該内層板(5)の上下にエポキ
シ樹脂系のプリプレグ(6)及び18μの銅箔(7)が
重ねられ熱圧成形したところ、表−1に示す高い品質の
多層板が得られた。Epoxy resin prepreg (6) and 18μ copper foil (7) were layered on top and bottom of the inner layer plate (5) as described in Example 1 and hot-press molded, resulting in high quality products as shown in Table 1. A multilayer board was obtained.
また銅箔に替えてガラスエポキシ系の基板に銅箔の積層
された銅張積層板を使用した場合においても板厚精度に
すぐれ、ボイド残留のない多層板が得られている。Furthermore, even when a copper-clad laminate in which copper foil is laminated on a glass epoxy substrate is used instead of copper foil, a multilayer board with excellent board thickness accuracy and no residual voids can be obtained.
内層板の回路ユニット間及び周囲部に配置される銅箔片
の大きさは30調以下のものが好ましく、その間隙は0
.5〜6mが望ましい。銅箔片が大きすぎると材料ロス
が大きくなる、間隙が過大であれば凹み及びボイド残留
の原因になる等の問題がさけられない。銅箔片の形状は
円形の他穆々のものが利用できる。The size of the copper foil pieces placed between and around the circuit units of the inner layer board is preferably 30 scale or less, and the gap between them is 0.
.. 5 to 6 m is desirable. If the copper foil piece is too large, material loss will be large, and if the gap is too large, it will cause dents and voids to remain. The shape of the copper foil piece can be circular or other shapes.
次に実施例に従い説明する。Next, an explanation will be given according to an example.
実施例1
ガラスエポキシ基材に4つの回路ユニット(1)が形成
され、該回路ユニット間(2)及び周囲部(3)K直径
5囚の円形の銅箔片(4)が配置された内層板(5)の
上下にエポキク樹脂系のプリプレグ(6)を介して銅箔
(7)を重ね、熱圧成形して実施例1の多層板囚を成形
した。Example 1 Four circuit units (1) are formed on a glass epoxy base material, and an inner layer in which circular copper foil pieces (4) with a K diameter of 5 mm are arranged between the circuit units (2) and in the surrounding area (3). Copper foil (7) was layered on top and bottom of the plate (5) with epoxy resin prepreg (6) interposed therebetween, and hot pressure molded to form the multilayer plate of Example 1.
比較例1,2
実施例1に使用の内層板において、回路ユニット間に円
形銅箔の配置されていない内層板を使用し、実施例1と
同様に比較例1の多層板■を成形した。ま六回路ユニッ
ト間及び周囲部に円形鋼箔の全く配置されていない内層
板を使用し、実施例1と同様に比較例2の多層板Cを成
形した。Comparative Examples 1 and 2 A multilayer board (2) of Comparative Example 1 was molded in the same manner as in Example 1, using an inner layer board used in Example 1 in which circular copper foils were not arranged between circuit units. A multilayer board C of Comparative Example 2 was molded in the same manner as in Example 1 using an inner layer board in which no circular steel foil was placed between and around the six circuit units.
上記実施例1及び比較例1,2の多層板の品質は表−1
の通シであシ、実施例1の多層板は極めて高い品質を備
えるものである。The quality of the multilayer boards of Example 1 and Comparative Examples 1 and 2 is shown in Table-1.
In general, the multilayer board of Example 1 has extremely high quality.
表−1
毫測定・判定
板厚鞘度二マイクロメーターによシ測定する銅箔外観:
シワの有無を確認する
○シワなし ×シワあシ
ボイド:外層を剥離し、目視判定する
〈発明の効果〉
本発明になる多層印刷回路板の製法では回路ユニット間
及び周囲部に銅箔片が間隙を設けて配置された内層板を
使用するものであるため、積層面に残留しゃすいボイド
が容易に離脱できボイド残留が回避される。また回路ユ
ニット間の凹みが生じないため成形品の板厚精度が確保
される。Table 1: Copper foil appearance measured with a 2-micrometer plate thickness/sheath index:
Check for the presence or absence of wrinkles ○No wrinkles Since the inner layer plate is arranged with the inner layer plate provided, the voids remaining on the laminated surface can be easily removed and the remaining voids can be avoided. Furthermore, since no dents occur between the circuit units, the thickness accuracy of the molded product is ensured.
殊に15〜35μの薄くシワの生じゃすい銅箔がプリプ
レグの上に重ねられるケースでも回路ユニット間周辺及
び端部周辺での銅箔のシワが回避され、外層回路を形成
する際に積層されるドライフィルム等の保護膜との密着
が良好で回路形成が正確になされるため製品不良がさけ
られるなど著しい効果が得られる。In particular, even in the case where a thin, wrinkled copper foil of 15 to 35 μm is layered on top of the prepreg, wrinkles in the copper foil around the edges and between circuit units can be avoided, and when forming the outer layer circuit, it is possible to prevent the copper foil from being laminated. It has good adhesion with protective films such as dry films, and circuits can be formed accurately, resulting in remarkable effects such as avoiding product defects.
第1図は本発明に係る内層板屯)の平面図、第2図は該
内層板(5)の上下にプリプレグ(6)及び銅箔(7)
が配置された状態図である。
1・・・回路ユニット 2・・・回路ユニット間3・
・・外周部 4・・・銅箔片5・・・内層板
6・・・プリプレグ7・・・銅箔
特許出願人 アイカニ業株式会社Figure 1 is a plan view of the inner layer plate (5) according to the present invention, and Figure 2 is a prepreg (6) and copper foil (7) above and below the inner layer plate (5).
It is a state diagram in which are arranged. 1...Circuit unit 2...Between circuit units 3.
...Outer periphery 4...Copper foil piece 5...Inner layer plate
6... Prepreg 7... Copper foil patent applicant Aikanigyo Co., Ltd.
Claims (1)
切られるとともに、外周部及び該回路ユニット間に銅箔
片の付着された内層板と銅箔もしくは銅張積層板とをプ
リプレグを介して積層することを特徴とする多層印刷回
路板の製法。(1) A plurality of circuit units are separated by circuit units, and an inner layer plate with copper foil pieces attached to the outer periphery and between the circuit units and a copper foil or copper-clad laminate are laminated via prepreg. A method for producing a multilayer printed circuit board characterized by:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP30647887A JPH01147896A (en) | 1987-12-03 | 1987-12-03 | Manufacture of multilayer printed circuit board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP30647887A JPH01147896A (en) | 1987-12-03 | 1987-12-03 | Manufacture of multilayer printed circuit board |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01147896A true JPH01147896A (en) | 1989-06-09 |
Family
ID=17957498
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP30647887A Pending JPH01147896A (en) | 1987-12-03 | 1987-12-03 | Manufacture of multilayer printed circuit board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01147896A (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6154938A (en) * | 1984-08-27 | 1986-03-19 | 富士通株式会社 | Manufacture of multilayer printed board |
JPS6210463B2 (en) * | 1978-08-04 | 1987-03-06 | Dainippon Screen Mfg |
-
1987
- 1987-12-03 JP JP30647887A patent/JPH01147896A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6210463B2 (en) * | 1978-08-04 | 1987-03-06 | Dainippon Screen Mfg | |
JPS6154938A (en) * | 1984-08-27 | 1986-03-19 | 富士通株式会社 | Manufacture of multilayer printed board |
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