JPH0114713B2 - - Google Patents

Description

[Detailed description of the invention] [Technical field of invention] The present invention relates to a semiconductor integrated circuit.

[Technical background of the invention and its problems]

The elements used in conventional semiconductor integrated circuits are only transistors, resistors, and capacitors, and coils or inductance elements are rarely used. This is because it is difficult to form a coil in a fine, two-dimensional circuit configuration such as an integrated circuit, and even if it were formed, only a small inductance value would be obtained, making it impractical. However, the advantage of using a coil as a circuit element is that the coil, like a capacitor, does not consume power and can be combined with a capacitor to form a filter, or two coils can be combined to form a filter. They can be coupled together to form a transformer to create any amplitude waveform, and their range of applications is extremely wide.

Also, integrated circuits that operate in synchronization with external signals,
For example, in dynamic RAM, the internal circuitry operates in synchronization with external signals (RAS, CAS signals), so a large power supply current suddenly flows when an external signal is input. 64 kbit dynamic RAM, which is currently in mass production, has an average current consumption of about 40 mA during operation, but a peak current of more than 100 mA flows instantaneously. Such peak currents require increasing the capacity of the power supply circuit that supplies power to the integrated circuit, and also cause noise to be easily generated in other circuits on the printed circuit board. When flowing through metal, the electromigration effect causes metal atoms to be pressurized by electrons, causing problems such as disconnection of structurally weak parts of minute metal wiring in integrated circuits. becomes. Furthermore, when a large current flows through the wiring, the available power supply voltage is reduced due to a voltage drop due to the electrical resistance of the wiring.
Therefore, it is desirable to reduce such peak current, but so far, it has been possible to reduce the current consumed in each part of the integrated circuit, or
Alternatively, no specific method has been proposed other than shifting the timing so that the current is consumed evenly. In the future, 64kbit dynamic RAM
As the capacity increases from 256 kbit to 1 Mbit, it is expected that the peak current value will become even larger, and methods to reduce this will be developed in the future.
This can be said to be an important issue in integrated circuits, which are trending toward higher integration and larger capacity.

[Purpose of the invention]

The present invention was made in view of the above-mentioned circumstances, and it is possible to efficiently form an inductance element on an integrated circuit chip, insert it in series with a power supply line, and smooth the power supply current together with a capacitor. The object of the present invention is to provide a semiconductor integrated circuit that can prevent the generation of current.

[Summary of the invention]

The first gist of the present invention is to form a large inductance element by forming a conductor film wiring on the outer periphery of an integrated circuit chip so as to surround a bonding pad, and utilizing the space on the outer periphery of the chip. . In this case, in order to increase the inductance sufficiently, the number of turns is increased by spirally wiring the same conductor film, or the windings are stacked three-dimensionally using multilayer conductor wiring.
The present invention also provides a second method for obtaining a larger inductance value by using a high magnetic permeability material in at least a part of the integrated circuit package to form a closed magnetic circuit with the inductance element on the chip. The summary is as follows. Furthermore, the third gist of the present invention is to configure a low-pass filter for smoothing power supply current by combining a capacitor formed on a chip with the above-described inductance element.

〔Effect of the invention〕

According to the present invention, a large inductance can be efficiently formed on an integrated circuit chip. By combining this with a capacitor also formed on the chip, it is possible to create a low-pass filter, and by connecting this to the power supply line of the integrated circuit, it is possible to prevent the inflow of peak current from the power supply. Therefore, there is no need to unnecessarily increase the capacity of the power supply circuit that supplies the printed circuit board consisting of a large number of integrated circuits. In other words, where a power supply circuit large enough to supply the peak current is required, by reducing the peak current, a power supply circuit with a smaller current supply capacity is sufficient. This makes it possible to reduce the cost of the entire integrated circuit system, including the power supply circuit. In addition, the peak current flowing through an integrated circuit causes noise due to voltage drop and electromagnetic induction in the power supply line, ground line, or signal line, causing equipment malfunction. By reducing this, noise generation can be reduced, and malfunctions of the entire device can be reduced. Furthermore, even within the integrated circuit, metal wiring is no longer cut due to the electromigration effect caused by peak current flowing through the power supply line.

[Embodiments of the invention]

An embodiment of the present invention will be described below. FIG. 1 is a plan view of an integrated circuit chip of one embodiment. That is,
Reference numeral 1 designates an integrated circuit chip, on which an internal circuit 2 consisting of a plurality of elements and wiring is formed, and bonding pads A ₁ -A ₄ and B ₁ -B ₄ are arranged on the outer periphery. The pad that serves as the power supply terminal on such a chip
An inductance element 3 is formed between A ₁ and A ₂ by patterning a single layer of conductive film in a spiral shape so as to surround the pads other than pad A ₂ inside.
By doing so, the inductance element can be formed without interfering with the wiring from each pad to the internal circuit, and its size can be made sufficient.

FIGS. 2a and 2b are a plan view and a schematic sectional view of a chip of another embodiment. In this embodiment, the inductance element 3' uses multilayer conductor wiring instead of a single layer of conductor wiring. That is, as shown in Fig. 2b, each layer of conductor wiring 3 ₁ ′, 3 ₂ ′, and 3 ₃ ′ forms one coil each, and each coil is connected in series through an interlayer insulating film to form a large number of turns. inductance element 3'
complete.

When an integrated circuit chip on which such an inductance element is formed is fixed to a metal pedestal for electrical contact, the magnetic field generated by the inductance element generates eddy currents in the pedestal, causing power loss. It is necessary to ensure that there are no For this purpose, it is preferable to provide a slit 5 in the chip pedestal 4 as shown in FIG.

Assuming the size of the integrated circuit chip to be 5 mm x 10 mm, and using Al as the wiring material for the inductance element, let's calculate the inductance by ignoring its resistance.
As shown in Figure 4, the lengths of the two sides are a,
b, the self-inductance of a rectangular circuit consisting of conductors of radius r is L=μ ₀ /π [−a log (a+√ ² + ² ) − b lo
g(b+ ^√2 + ₂ )+(a+b)log2ab/f+ ^2√2 + ^2-7 /4(a+b)]. a=5mm, b=10mm, r=2μm
Then, L=45nH. Therefore, it can be seen that the one-turn coil in FIG. 1 has a power of about 45 nH.
Assuming that the wire is wound spirally 10 times and the winding width is sufficiently small compared to the size of the chip, the inductance of the chip is proportional to the square of the number of turns, so
The inductance at this time is approximately 4.5μH.

Further increases in the inductance of the coil can be achieved by modifying the packaging of the integrated circuit chip, as shown in FIG. This package constructs a magnetic circuit by sandwiching the chip 1 from above and below between an upper package core ₆₁ and a lower package core ₆₂ , which are made of a material with high magnetic permeability such as ferrite and formed into an E-shaped pot core shape. . This is an example of configuring a magnetic circuit using a DIP, which is a normal integrated circuit package, as the core. Figure 5a is a partially cutaway perspective view, Figure 5b,
c shows a cross-sectional view of the Y plane and the X plane of a, respectively. The hatched areas 7 ₁ and 7 ₂ in FIG. 5c indicate the surfaces where the upper and lower package cores 6 ₁ and 6 ₂ come into contact. In this way, if a magnetic circuit is constructed of a material with high magnetic permeability (μ ₀ to 1000) outside the chip, a gap will occur due to the thickness of the chip, and even considering that magnetic resistance will be introduced, it will be approximately
It is possible to increase the inductance by about 100 times. Therefore, in the case of the above-mentioned 10-turn coil, it is 450 μH.

In the case of 64k bit dynamic RAM, the peak waveform of the power supply current has a peak value of 100mA and the current pulse width is
It is about 20nsec. Therefore, when the power supply voltage is 5V, the circuit equivalent impedance when the peak current flows is R=5V/100mA=50Ω. As a smoothing capacitor that can supply sufficient current to this 50Ω, the CR time constant with this resistance is
Just choose one that is sufficiently larger than 20nS. CR≫
If R=50Ω at 20nS, then C≫400PF.

An embodiment in which such a smoothing capacitor is formed on a chip together with the above-mentioned inductance element will be described. The smoothing capacitor uses a MOS capacitor between the electrode and the substrate via a 200 Å gate oxide film, and a MOS capacitor under the inductance element formation area.
An area of 50 μm width is used. At this time, the capacitance is C=ε×A/d=8.854×10 ^-14 ×100×10 ^-4
×3/200×10 ^-8 = 2500×10 ^-12 (F) = 2500 (PE), which is a sufficient size. and this
6th with MOS capacitor and inductance element
If we form a low-pass filter as shown in the figure,
Its cutoff frequency is Therefore, according to this embodiment, it is possible to effectively prevent a sudden peak current of 20 μsec or less.

[Brief explanation of drawings]

1 is a plan view of an integrated circuit chip according to one embodiment of the present invention, FIGS. 2a and 2b are a plan view and a schematic sectional view of an integrated circuit chip according to another embodiment, and FIG. 3 is a diagram showing a chip pedestal. FIG. 4 is a diagram showing an equivalent rectangular circuit for determining the inductance value of the above embodiment, FIGS. 1 is an equivalent circuit diagram of a main part of an embodiment of the present invention in which a low-pass filter is inserted into a power supply line. 1... integrated circuit chip, 2... internal circuit, 3,
3'...Inductance, _A1 to _A4 , _B1 to _B4 ...
Bonding pad, 6 ₁ , 6 ₂ ...Package core.

Claims (1)

[Scope of Claims] 1. An inductance element is constructed by conductor film wiring arranged on a semiconductor chip formed by integrating a plurality of elements so as to surround a plurality of bonding pads provided on the outer periphery of the semiconductor chip. Semiconductor integrated circuit. 2. The semiconductor integrated circuit according to claim 1, wherein the inductance element is formed by patterning a single layer of conductive film disposed on a semiconductor chip in a spiral shape. 3. The semiconductor integrated circuit according to claim 1, wherein the inductance element has a plurality of windings formed by connecting in series conductor film wires laminated in a plurality of layers on a semiconductor chip. 4. A package that constitutes an inductance element by conductive film wiring arranged so as to surround a plurality of bonding pads provided on the outer periphery of a semiconductor chip formed by integrating a plurality of elements, and that houses the semiconductor chip. 1. A semiconductor integrated circuit, wherein at least a part of the semiconductor integrated circuit is made of a high magnetic permeability material, and a magnetic circuit is formed by the inductance element and the package. 5. An inductance element is constituted by a conductor film wiring arranged so as to surround a plurality of bonding pads provided on the outer periphery of a semiconductor chip formed by integrating a plurality of elements, and an inductance element is formed by a conductor film wiring arranged so as to surround a plurality of bonding pads provided on the outer periphery of the semiconductor chip, and an inductance element is formed between this and the semiconductor chip. A semiconductor integrated circuit characterized in that the formed capacitors are combined to form a low-pass filter for power supply current smoothing.