JP6420786B2 - Semiconductor integrated circuit - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit including a surge protection circuit.

  Patent Document 1 below discloses a semiconductor integrated circuit including a surge absorbing circuit. The surge absorption circuit includes a thyristor inserted between the external power supply terminal and the internal circuit element. The internal circuit element includes, for example, a MOS (Metal Oxide Semiconductor) transistor. When a surge is applied to the external power supply terminal, the thyristor of the surge absorption circuit starts operating, and the surge is absorbed. This can prevent internal circuit element breakdown due to surge, for example, junction breakdown of the source region of the transistor.

  By the way, in the surge absorbing circuit, the speed from the input of the surge to the start of the thyristor operation is equal to the speed until the breakdown at the junction of the source region of the transistor is started. For this reason, when a high-field surge having a high-frequency component is input to the external power supply terminal, the surge absorption circuit cannot absorb the surge, and the surge high-frequency component flows to the junction of the transistor, destroying the internal circuit elements. There is a risk. On the other hand, an external electronic component can be mounted on the semiconductor integrated circuit, and the high frequency component of the surge can be attenuated using this electronic component. However, when an external electronic component is added to the semiconductor integrated circuit, the circuit scale of the entire system including the semiconductor integrated circuit increases, and the degree of system integration decreases. For this reason, there was room for improvement.

JP-A-3-234052

  In consideration of the above facts, the present invention provides a semiconductor integrated circuit that can improve the protection tolerance of an internal circuit against a surge, and can reduce the number of mounted components to improve the degree of system integration.

  In order to solve the above problems, a semiconductor integrated circuit according to a first embodiment of the present invention is applied with a first external power supply terminal to which a first power supply voltage is applied and a second power supply voltage different from the first power supply voltage. A first power supply voltage is supplied from the second external power supply terminal and the first external power supply terminal via the first power supply wiring, and a second power supply voltage is supplied from the second external power supply terminal via the second power supply wiring. And a surge that is inserted between the first external power supply terminal and the second external power supply terminal and has a pn junction between the first power supply wiring and the second power supply wiring. And a coil electrically connected in series to at least one of the first power supply wiring and the second power supply wiring.

  In the semiconductor integrated circuit according to the first embodiment, a protection element is inserted between the first power supply wiring and the second power supply wiring, and a coil is electrically connected in series with at least one of the first power supply wiring and the second power supply wiring. Connected. Since the protective element has a pn junction, parasitic capacitance is added to the pn junction. For this reason, since the LC filter is configured by coupling the capacitor and the coil, the high frequency component of the surge can be attenuated by this LC filter. On the other hand, the coil is electrically connected in series to at least one of the first power supply wiring and the second power supply wiring, and is integrated in the semiconductor integrated circuit. For this reason, it is not necessary to mount an external electronic component for improving the protection strength of the internal circuit in the system, so that the circuit scale of the system can be reduced.

  In the semiconductor integrated circuit according to the second embodiment of the present invention, in the semiconductor integrated circuit according to the first embodiment, the protection element is a thyristor including a pnp bipolar transistor and an npn bipolar transistor.

  In the semiconductor integrated circuit according to the second embodiment, since the protective element is a thyristor, the thyristor has a pn junction, and a parasitic capacitance is added to the pn junction. For this reason, an LC filter can be constructed without separately providing a capacitor, so that the degree of integration can be improved.

  In the semiconductor integrated circuit according to the third embodiment of the present invention, in the semiconductor integrated circuit according to the first embodiment, the protection element is a diode connected in the reverse direction.

  According to the semiconductor integrated circuit of the third embodiment, the diode includes the anode region and the cathode region, and has a pn junction between the anode region and the cathode region. For this reason, as in the thyristor, since the LC filter can be constructed without providing a separate capacitive element, the protection strength of the internal circuit can be improved and the degree of integration can be improved. it can.

  In the semiconductor integrated circuit according to the fourth embodiment of the present invention, in the semiconductor integrated circuit according to any one of the first to third embodiments, the coil is configured by a spiral wiring in a plan view. .

  According to the semiconductor integrated circuit according to the fourth embodiment, since the coil is formed by spiral wiring, the coil can be easily configured without using a multilayer wiring.

  In the semiconductor integrated circuit according to the fifth embodiment of the present invention, in the semiconductor integrated circuit according to any one of the first to fourth embodiments, the coil has the same conductive layer as the first power supply wiring or the second power supply wiring, And it is formed of the same conductive material.

  According to the semiconductor integrated circuit according to the fifth embodiment, the coil can be easily configured without separately providing the wiring layer and the wiring arranged in the wiring layer.

  ADVANTAGE OF THE INVENTION According to this invention, the semiconductor integrated circuit which can improve the protection tolerance of the internal circuit with respect to a surge and can reduce the number of mounting components and can improve the integration degree of a system can be provided.

1 is a main part circuit diagram showing a surge protection circuit and an internal circuit of a semiconductor integrated circuit according to a first embodiment of the present invention; FIG. 2 is a main part sectional view of a semiconductor integrated circuit showing a longitudinal sectional structure of the surge protection circuit shown in FIG. 1. FIG. 2 is a main part sectional view of a semiconductor integrated circuit showing a longitudinal sectional structure of an internal circuit shown in FIG. 1. FIG. 3 is a schematic plan view of the surge protection circuit shown in FIG. 2. It is a graph which shows the relationship between the inductance of the coil of the surge protection circuit shown by FIG.2 and FIG.4, and surge protection strength. FIG. 4 is a circuit diagram of a principal part corresponding to FIG. 1 of a semiconductor integrated circuit according to a second embodiment of the present invention. FIG. 17 is a principal part circuit diagram corresponding to FIG. 6 of a semiconductor integrated circuit according to a first modification example of the second embodiment; FIG. 17 is a principal part circuit diagram corresponding to FIG. 6 of a semiconductor integrated circuit according to a second modification example of the second embodiment;

[First Embodiment]
Hereinafter, a semiconductor integrated circuit including a surge protection circuit according to the first embodiment of the present invention will be described with reference to FIGS.

(Circuit configuration of semiconductor integrated circuit)
As shown in FIG. 1, the semiconductor integrated circuit 10 according to the present embodiment includes an internal circuit 14 at the center of the main surface of a semiconductor substrate (semiconductor chip) 12. A first external power supply terminal 20, a second external power supply terminal 22, and an external signal terminal 24 are disposed around the internal circuit 14 and on the main surface of the semiconductor substrate 12. Here, only main external terminals are shown, but a number of external terminals other than those described above are arranged on the semiconductor substrate 12.

  The first external power supply terminal 20 is connected to the internal circuit 14 through the first power supply wiring 20L. A power supply voltage Vcc required for circuit operation is applied to the first external power supply terminal 20 from a power supply 26 external to the semiconductor integrated circuit 10. Since the semiconductor integrated circuit 10 according to the present embodiment is mounted on a vehicle such as an automobile, the power supply 26 is a battery mounted on the vehicle. The power supply 26 is supplied to the semiconductor integrated circuit 10, for example, by direct current 12V or direct current 24V directly or through a power supply circuit (not shown).

  The second external power supply terminal 22 is connected to the internal circuit 14 through the second power supply wiring 22L. A power supply voltage Vss required for circuit operation from the power supply 26 and different from the power supply voltage Vcc is applied to the second external power supply terminal 22. The power supply voltage Vss is a power supply voltage lower than the power supply voltage Vcc, here 0V (ground voltage).

  The external signal terminal 24 is used as an input signal terminal, and is connected to the first stage circuit 16 of the internal circuit 14 through the signal wiring 24L. Although the circuit configuration is not particularly limited, in the present embodiment, the first stage circuit 16 is configured by a complementary transistor. More specifically, the first stage circuit 16 includes a p-channel insulated gate field effect transistor (IGFET: Insulated Gate Field Effect Transistor; hereinafter simply referred to as “transistor”) Qp and an n-channel transistor Qn. The gate electrodes of both the transistor Qp and the transistor Qn are connected to the external signal terminal 24 through the signal wiring 24L. A signal IN is input to the external signal terminal 24 from the outside of the semiconductor integrated circuit 10, and the operation of the first stage circuit 16 is controlled in accordance with the input signal IN. Note that the drain region as the main electrode region of both the transistor Qp and the transistor Qn is connected to a next-stage circuit (not shown) via the output terminal 18. The first stage circuit 16 outputs a signal OUT to the next stage circuit. A power supply voltage Vcc is applied from the first power supply wiring 20L to the source region as the main electrode region of the transistor Qp. The power supply voltage Vss is applied from the second power supply wiring 22L to the source region as the main electrode region of the transistor Qn.

  The semiconductor integrated circuit 10 according to the present embodiment includes a surge protection circuit 30 between the first external power supply terminal 20 and the second external power supply terminal 22 and the internal circuit 14. The surge protection circuit 30 includes a protection element 32 and a coil 34.

  More specifically, the protection element 32 is configured by a thyristor electrically connected in parallel between the first power supply line 20L and the second power supply line 22L. The thyristor includes a pnp bipolar transistor T1 and an npn bipolar transistor T2. The bipolar transistor T1 has an emitter region (anode region) connected to the first power supply line 20L and a collector region (gate region) connected to the second power supply line 22L. The base region of the bipolar transistor T1 is connected to the collector region of the bipolar transistor T2. The emitter region (cathode region) of the bipolar transistor T2 is connected to the second power supply line 22L, and the base region is connected to the emitter region of the bipolar transistor T1 and the second power supply line 22L. The protection element 32 absorbs a surge input to one of the first external power supply terminal 20 and the second external power supply terminal 22 to either one.

  Here, in the bipolar transistor T1, a pn junction is formed between the emitter region and the base region (see FIG. 2). Since a depletion layer is formed at the pn junction, a parasitic capacitance C is added between the emitter region and the collector region.

  On the other hand, the coil 34 is electrically inserted in series with the first power supply wiring 20L. That is, one end of the coil 34 is connected to the first external power supply terminal 20 via the protection element 32, and the other end of the coil 34 is connected to the internal circuit 14.

  In the surge protection circuit 30, a capacitor C added by the pn junction of the protection element 32 and the coil 34 constitute an L-type LC filter. In this LC filter, for example, when a high electric field surge is input to the first external power supply terminal 20, the high frequency component of the surge can be attenuated.

(Device structure of semiconductor integrated circuit)
A specific device structure of the semiconductor integrated circuit 10 according to the present embodiment will be described. As shown in FIGS. 2 and 3, the semiconductor integrated circuit 10 includes a semiconductor substrate 12. The semiconductor substrate 12 is formed of a single crystal silicon substrate set to the first conductivity type p-type and set to a low impurity density. A power supply voltage Vss is applied to the semiconductor substrate 12.

  First, the transistor Qp constituting the first stage circuit 16 of the internal circuit 14 is formed in the second conductivity type n-type well region (n-type semiconductor region) 40 as shown in FIG. The n-type well region 40 is formed in the main surface portion of the semiconductor substrate 12 and is set to an impurity density higher than the impurity density of the semiconductor substrate 12. The transistor Qn is formed in the p-type well region (p-type semiconductor region) 42. The p-type well region 42 is formed on the main surface portion of the semiconductor substrate 12 at a position different from the n-type well region 40, and is set to an impurity density higher than the impurity density of the semiconductor substrate 12.

  In the region surrounded by the element isolation region 46, the transistor Qp has a main surface portion of the n-type well region 40 as a channel formation region, a pair of p-type semiconductor regions 48, a gate insulating film 52, and a gate electrode 54. It is comprised including. The pair of p-type semiconductor regions 48 are a source region and a drain region, and constitute a main electrode region of the transistor Qp. The p-type semiconductor region 48 is set to have a higher impurity density than the p-type well region 42. The gate insulating film 52 is formed on the main surface of the n-type well region 40 between the pair of p-type semiconductor regions 48. As the gate insulating film 52, for example, a silicon oxide film, a silicon nitride film, or a composite film in which a silicon oxide film and a silicon nitride film are combined is used. The gate electrode 54 is formed on the gate insulating film 52. For the gate electrode 54, for example, a polycrystalline silicon film, a refractory metal silicide film, a refractory metal film, or a composite film thereof is used. Impurities that reduce the resistance value are added to the polycrystalline silicon film.

  A first layer wiring 58 is electrically connected to the p-type semiconductor region 48. The wiring 58 is formed on the transistor Qp via the interlayer insulating film 56 and is connected to the p-type semiconductor region 48 through a connection hole (reference numeral is omitted) formed in the interlayer insulating film 56. For the wiring 58, for example, a composite film mainly composed of an aluminum alloy film is used. The wiring 58 is electrically connected to the second-layer wiring 62. The wiring 62 is formed on the wiring 58 via the interlayer insulating film 60, and is connected to the wiring 58 through a connection hole 60 </ b> H formed in the interlayer insulating film 60. The wiring 62 is formed of the same conductive material as that of the wiring 58.

  In the region separated from the transistor Qp, an n-type semiconductor region 50C is formed in the main surface portion of the n-type well region 40. The n-type semiconductor region 50C is set to the same impurity density as that of the n-type semiconductor region 50, and is used as a well contact region that supplies the power supply voltage Vcc to the n-type well region 40.

  In the region surrounded by the element isolation region 46, the transistor Qn has a main surface portion of the p-type well region 42 as a channel formation region, a pair of n-type semiconductor regions 50, a gate insulating film 52, and a gate electrode 54. It is comprised including. The pair of n-type semiconductor regions 50 are a source region and a drain region, and constitute a main electrode region of the transistor Qn. The n-type semiconductor region 50 is set to a higher impurity density than the n-type well region 40. The gate insulating film 52 is formed on the main surface of the p-type well region 42 between the pair of n-type semiconductor regions 50. The gate electrode 54 is formed on the gate insulating film 52.

  A wiring 58 is electrically connected to the n-type semiconductor region 50. A wiring 62 is electrically connected to the wiring 58. A p-type semiconductor region 48C is formed in the main surface portion of the p-type well region 42 in a region separated from the transistor Qn. The p-type semiconductor region 48C is set to the same impurity density as the p-type semiconductor region 48, and is used as a well contact region that supplies the power supply voltage Vss to the p-type well region 42.

  On the other hand, as shown in FIG. 2, the bipolar transistor T1 constituting the protection element 32 of the surge protection circuit 30 has an n-type well region 40 as a base region, a p-type semiconductor region 48 as an emitter region, and a p-type well region. 44 is configured as a collector region. That is, the bipolar transistor T1 has a lateral structure. The p-type well region 44 is formed in the main surface portion of the n-type well region 40, has an impurity density higher than that of the p-type well region 42, and has a junction depth shallower than the depth of the p-type well region 42. . In a region separated from the p-type semiconductor region 48, an n-type semiconductor region 50 </ b> C as a well contact region is formed on the main surface portion of the n-type well region 40.

  The bipolar transistor T2 includes an n-type well region 40 as a collector region, a p-type well region 44 as a base region, and an n-type semiconductor region 50 as an emitter region. That is, the bipolar transistor T2 has a vertical structure. In a region separated from the n-type semiconductor region 50, a p-type semiconductor region 48C as a well contact region is formed on the main surface portion of the p-type well region 44.

  As shown in FIG. 2, the coil 34 of the surge protection circuit 30 is formed by using the wiring 62, disposed in the same conductive layer as the wiring 62 (formed by the same manufacturing process), and made of the same conductive material. The wiring 62C is formed. That is, the wiring 62C is disposed on the interlayer insulating film 60. As shown in FIG. 4, the wiring 62 </ b> C of the coil 34 is formed in a square shape as a whole in a plan view, but is formed in a spiral shape that moves away from the center as it turns.

  In FIG. 4, the planar structure of the protection element 32 is omitted, but in this embodiment, the length L2 in the same direction of the coil 34 is set shorter than the length L1 in one direction of the protection element 32. ing. Further, the length L3 orthogonal to one direction of the coil 34 is made equal to the length of the protective element 32 in the same direction to optimize the layout. Here, for example, the length L1 of the protection element 32 is set to 650 μm. The length L2 of the coil 34 is set to 350 μm and the length L3 is set to 350 μm. In the coil 34 set to such a dimension, an inductance of 0.8 [μH] to 1.0 [μH] can be obtained.

(Operation and effect of the present embodiment)
As shown in FIG. 1, the semiconductor integrated circuit 10 according to the present embodiment includes a surge protection circuit 30, and the surge protection circuit 30 includes a protection element 32 and a coil 34. The protection element 32 is inserted between the first power supply wiring 20L and the second power supply wiring 22L, and the coil 34 is electrically connected in series to the first power supply wiring 20L. Since the protection element 32 has a pn junction, a parasitic capacitance C is added to the pn junction. For this reason, since the LC filter is constructed by coupling the capacitor C and the coil 34, the high frequency component of the surge can be attenuated by this LC filter.

  FIG. 5 shows the relationship between the inductance value of the coil 34 and the surge protection strength. The horizontal axis represents inductance [μH], and the vertical axis represents surge protection strength [kV]. The surge protection circuit 30 having a coil 34 set to an inductance of 1.0 [μH] is four times that of the semiconductor integrated circuit (symbol A) according to the comparative example in which only the thyristor is not provided as a surge protection circuit. As a result, the result (symbol B) was obtained.

  On the other hand, the coil 34 of the surge protection circuit 30 is electrically connected in series to the first power supply wiring 20 </ b> L and is integrated in the semiconductor integrated circuit 10. For this reason, there is no need to mount an external electronic component for improving the protection strength of the internal circuit 14 in the system, so that the circuit scale of the system can be reduced.

  Therefore, it is possible to provide the semiconductor integrated circuit 10 that can improve the protection tolerance of the internal circuit 14 against a surge, and can reduce the number of mounted components and improve the degree of system integration.

  In the semiconductor integrated circuit 10 according to the present embodiment, as shown in FIGS. 1 and 2, the protection element 32 of the surge protection circuit 30 is a thyristor including a bipolar transistor T1 and a bipolar transistor T2. is there. The thyristor has a pn junction, and a parasitic capacitance C is added to the pn junction. For this reason, an LC filter can be constructed without separately providing a capacitive element, so that the protection strength of the internal circuit 14 can be improved and the degree of integration can be improved.

  Furthermore, in the semiconductor integrated circuit 10 according to the present embodiment, as shown in FIGS. 2 and 4, the coil 34 of the surge protection circuit 30 is configured by a spiral wiring 62 </ b> C in plan view. Since the single-layer wiring 62C is drawn in a spiral shape, a multilayer wiring is not used, so that the coil 34 can be configured easily.

  In the semiconductor integrated circuit 10 according to the present embodiment, as shown in FIG. 2, the coil 34 (wiring 62C) of the surge protection circuit 30 is connected to the second-layer wiring 62 as the first power supply wiring 22L. The same conductive layer and the same conductive material are used. For this reason, the coil 34 can be simply configured using the wiring 62 without separately providing a wiring layer and wiring arranged in the wiring layer. The coil 34 may be formed of the same conductive layer and the same conductive material as the wiring 58 using the first layer wiring 58.

[Second Embodiment]
Hereinafter, a semiconductor integrated circuit including a surge protection circuit according to the second embodiment of the present invention will be described with reference to FIGS. In the present embodiment, the same or substantially the same components as those of the semiconductor integrated circuit 10 according to the first embodiment are denoted by the same reference numerals, and redundant description is omitted.

  In the semiconductor integrated circuit 10 according to the present embodiment, as shown in FIG. 6, the first power supply wiring 20L is electrically connected between the first external power supply terminal 20 and the protection element 32 of the surge protection circuit 30. The coil 34 of the surge protection circuit 30 is inserted in series. According to the semiconductor integrated circuit 10 shown in FIG. 6, it is possible to obtain the same operational effects as those obtained by the semiconductor integrated circuit 10 according to the first embodiment.

  The semiconductor integrated circuit 10 shown in FIG. 7 is a first modification of the present embodiment, and is between the second external power supply terminal 22 and the protection element 32 of the surge protection circuit 30 and is connected to the second power supply wiring 22L. The coil 34 of the surge protection circuit 30 is inserted electrically in series. Also in the semiconductor integrated circuit 10 shown in FIG. 7, it is possible to obtain the same operational effects as those obtained by the semiconductor integrated circuit 10 according to the first embodiment.

  A semiconductor integrated circuit 10 shown in FIG. 8 is a second modification of the present embodiment, and is electrically connected to the second power supply wiring 22L between the protection element 32 of the surge protection circuit 30 and the internal circuit 14. The coil 34 of the surge protection circuit 30 is inserted in series. Also in the semiconductor integrated circuit 10 shown in FIG. 8, it is possible to obtain the same effects as the effects obtained by the semiconductor integrated circuit 10 according to the first embodiment.

[Supplementary explanation of the above embodiment]
The present invention is not limited to the above-described embodiment, and can be modified as follows, for example, without departing from the gist thereof. For example, in the present invention, a coil is electrically connected in series to a power supply wiring between an external power supply terminal and a protection element of a surge protection circuit, and between a protection element and an internal circuit, May be built. Moreover, you may use the Zener diode (diode) connected to the reverse direction for the protection element of a surge protection circuit. The Zener diode is configured to include an anode region and a cathode region, and has a pn junction between the anode region and the cathode region. For this reason, as with thyristors, it is possible to construct an LC filter without providing a separate capacitive element even with a zener diode, so that the protection strength of the internal circuit can be improved and the degree of integration can be improved. Can do. In the present invention, a transistor may be used as the protection element of the surge protection circuit. Since a pn junction between the source or drain region of the transistor and the well region is formed, and a parasitic capacitance is added to the pn junction, an LC filter can be constructed using the capacitance.

DESCRIPTION OF SYMBOLS 10 Semiconductor integrated circuit 12 Semiconductor substrate 14 Internal circuit 20 1st external power supply terminal 20L 1st power supply wiring 22 2nd external power supply terminal 22L 2nd power supply wiring 30 Surge protection circuit 32 Protection element 34 Coil T1, T2 Bipolar transistor Qp, Qn transistor C capacity

Claims (3)

A first external power supply terminal to which a first power supply voltage is applied;
A second external power supply terminal to which a second power supply voltage different from the first power supply voltage is applied;
An internal circuit in which the first power supply voltage is supplied from the first external power supply terminal via a first power supply wiring, and the second power supply voltage is supplied from the second external power supply terminal via a second power supply wiring. When,
A surge that is inserted between the first power supply wiring and the second power supply wiring, has a pn junction, and is input to either the first external power supply terminal or the second external power supply terminal. A protective element to be absorbed by either of the other,
A coil electrically connected in series to at least one of the first power supply wiring and the second power supply wiring;
Equipped with a,
The protection element includes a thyristor having a pnp bipolar transistor and an npn bipolar transistor,
The pnp bipolar transistor has an emitter region connected to the first power supply wiring, a collector region connected to the second power supply wiring, and a base region connected to the collector region of the npn bipolar transistor,
The npn bipolar transistor has an emitter region connected to the second power supply line, and a base region connected to the emitter region of the pnp bipolar transistor and the second power supply line.
A semiconductor integrated circuit further comprising an LC filter including a capacitor and a coil formed at the pn junction between the emitter region and the base region of the pnp bipolar transistor . The semiconductor integrated circuit according to claim 1, wherein the coil is configured by a spiral wiring in a plan view . The semiconductor integrated circuit according to claim 1 , wherein the coil is formed of the same conductive layer and the same conductive material as the first power supply wiring or the second power supply wiring .

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