JPH01146448A - Frequency offset correction circuit - Google Patents

Frequency offset correction circuit

Info

Publication number
JPH01146448A
JPH01146448A JP62306591A JP30659187A JPH01146448A JP H01146448 A JPH01146448 A JP H01146448A JP 62306591 A JP62306591 A JP 62306591A JP 30659187 A JP30659187 A JP 30659187A JP H01146448 A JPH01146448 A JP H01146448A
Authority
JP
Japan
Prior art keywords
data point
multiplier
signal
data
output signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62306591A
Other languages
Japanese (ja)
Inventor
Takami Suzuki
鈴木 貴巳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62306591A priority Critical patent/JPH01146448A/en
Publication of JPH01146448A publication Critical patent/JPH01146448A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To measure a frequency offset without error from an unknown data signal by applying decision through data point arrangement less than the normal data point arrangement and applying correction when the output of an adaptive equalizer is large. CONSTITUTION:Phase difference generating means 5, 6, 7, 8 compare the data point corresponding to the product of the output signal between frequency variable oscillation means 12, 13 applying frequency offset correction and the adaptive equalizer 1 with the data point less than the usual data point for the arrangement and select the data point closest to the data point representing the output signal of a multiplier 4 and generate a phase difference signal between the output signal of the multiplier 4 and the selected data point. Control means 9, 10, 11 give the phase difference signal to frequency variable oscillation means 12, 13 when the absolute value of the output signal of the multiplier 4 is larger than the prescribed value and do not give zero to the frequency variable oscillation means when the absolute value of the output signal of the multiplier is smaller than the prescribed value. Thus, control is not carried out.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、直交振幅変調されたデータの伝送系に利用す
る。特に、周波数オフセット量の測定回路に関する。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is applied to a transmission system for orthogonal amplitude modulated data. In particular, the present invention relates to a frequency offset measuring circuit.

〔概要〕〔overview〕

本発明は、直交振幅変調されたデータのデータ点配置に
基づき周波数オフセット量を補正する手段において、 通常のデータ点配置より少ないデータ点配置による判定
を行い、適応等化器の出力が大きい場合に修正を行うこ
とにより、 未知のデータ信号から周波数オフセット量を誤りなく測
定することができるようにしたものである。
The present invention provides means for correcting the amount of frequency offset based on the data point arrangement of orthogonal amplitude modulated data, in which a determination is made using a data point arrangement smaller than the normal data point arrangement, and when the output of the adaptive equalizer is large. By making this modification, it is now possible to measure the frequency offset amount from an unknown data signal without error.

〔従来の技術〕[Conventional technology]

従来、この種の周波数オフセット量は通常の受信データ
信号を判定するデータ点配置に基づき推定が行われてい
た。
Conventionally, this type of frequency offset amount has been estimated based on a data point arrangement for determining a normal received data signal.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

このような従来の周波数オフセット補正回路は、データ
点配置が少ない場合は電話回線の特性による劣化で生ず
る符号量干渉が多く含まれてもデータ点判定を誤ること
が比較的少なく有効である。
Such a conventional frequency offset correction circuit is effective because it is relatively less likely to make errors in determining data points even if a large amount of code amount interference caused by deterioration due to telephone line characteristics is included when the number of data points is small.

しかし、データ点配置が多くとなると(例えば、64点
や128点)、測定誤りを起こしやすく、未知のデータ
信号から周波数オフセット量を推定することが困難にな
る欠点があった。
However, when the number of data points is increased (for example, 64 points or 128 points), measurement errors tend to occur and it becomes difficult to estimate the amount of frequency offset from an unknown data signal.

本発明はこのような欠点を除去するもので、データ点の
多い直交振幅変調されたデータでも、未知のデータ信号
から周波数オフセット量を誤りなく測定することができ
る周波数オフセット補正回路を提供することを目的とす
る。
The present invention aims to eliminate such drawbacks, and provides a frequency offset correction circuit that can measure the frequency offset amount from an unknown data signal without error even in quadrature amplitude modulated data with many data points. purpose.

〔問題点を解決するための手段〕 本発明は、周波数可変発振手段と、この周波数可変発振
手段の出力信号と適応等化器の出力信号との積を演算す
る乗算器と、直交振幅変調されたデータ信号のデータ点
より少ないデータ点を有するデータ点配置のデータ点の
うち上記乗算器の出力信号に対応する第一のデータ点に
最寄りの第二のデータ点とこの第一のデータ点との位相
差を示す位相差信号を生成する位相差発生手段と、上記
乗算器の出力信号の絶対値が所定値より大きいときに上
記位相差信号に基づき上記周波数可変発振手段の出力を
調整し、また、小さいときはこの調整を禁止する制御手
段とを備えたことを特徴とする。
[Means for Solving the Problems] The present invention provides a variable frequency oscillation means, a multiplier that calculates the product of an output signal of the frequency variable oscillation means and an output signal of an adaptive equalizer, and a quadrature amplitude modulated a second data point closest to the first data point corresponding to the output signal of the multiplier among the data points in the data point arrangement having fewer data points than the data points of the data signal; phase difference generating means for generating a phase difference signal indicating a phase difference of; and adjusting the output of the frequency variable oscillation means based on the phase difference signal when the absolute value of the output signal of the multiplier is larger than a predetermined value; It is also characterized by comprising a control means for prohibiting this adjustment when the adjustment is small.

〔作用〕[Effect]

周波数オフセット補正を行う周波数可変発振手段の出力
信号と適応等化器の出力信号との積に相当するデータ点
と通常の、データ点より少ないデータ点配置とを比較し
、乗算器の出力信号を表すデータ点に最も近いデータ点
を選択し、乗算器の出力信号と選択されたデータ点との
位相差信号を発生する。乗算器の出力信号の絶対値が所
定の値より大きければ位相差信号を周波数可変発振手段
に人力し、乗算器の出力信号の絶対値が所定の値より小
さければ零を周波数可変発振手段に入力させて制御を行
わない。
A data point corresponding to the product of the output signal of the frequency variable oscillation means that performs frequency offset correction and the output signal of the adaptive equalizer is compared with a normal data point arrangement having fewer data points, and the output signal of the multiplier is A data point closest to the data point being represented is selected and a phase difference signal between the output signal of the multiplier and the selected data point is generated. If the absolute value of the multiplier output signal is larger than a predetermined value, the phase difference signal is input to the frequency variable oscillation means, and if the absolute value of the multiplier output signal is smaller than the predetermined value, zero is input to the frequency variable oscillation means. control.

〔実施例〕〔Example〕

以下、本発明の一実施例を図面に基づき説明する。第1
図は、この実施例の構成を示すブロック構成図である。
Hereinafter, one embodiment of the present invention will be described based on the drawings. 1st
The figure is a block configuration diagram showing the configuration of this embodiment.

この実施例は、第1図に示すように、未知のデータ信号
に基づきトレーニングが行われる適応等化器lと、周波
数再発振幅手段であるループフィルタ12および周波数
可変発振器13と、この周波数可変発振手段の出力信号
と適応等化器1の出力信号との積を演算する乗算器4と
、直交振幅変調されたデータ信号のデータ点より少ない
データ点を有するデータ点配置のデータ点のうち乗算器
4の出力信号に対応する第一のデータ点に最寄りの第二
のデータ点とこの第一のデータ点との位相差を示す位相
差信号を生成する位相差発生手段である判定回路5、複
素共役回路6、乗算器7および虚数部抽出回路8と、乗
算器4の出力信号の絶対値が所定値より大きいときに上
記位相差信号に基づき上記周波数可変発振手段の出力を
調整し、また、小さいときはこの調整を禁止する制御手
段である絶対値化回路9、比較器10および切替器11
とを備える。
This embodiment, as shown in FIG. a multiplier 4 for calculating the product of the output signal of the means and the output signal of the adaptive equalizer 1; and a multiplier among the data points of the data point arrangement having fewer data points than the data points of the quadrature amplitude modulated data signal. A determination circuit 5 which is a phase difference generating means for generating a phase difference signal indicating a phase difference between this first data point and a second data point nearest to the first data point corresponding to the output signal of No. 4; Adjusting the output of the variable frequency oscillation means based on the phase difference signal when the absolute value of the output signal of the conjugate circuit 6, the multiplier 7, the imaginary part extraction circuit 8, and the multiplier 4 is larger than a predetermined value, and Absolute value converting circuit 9, comparator 10, and switch 11 are control means for prohibiting this adjustment when the value is small.
Equipped with.

伝送チャネルから受信される信号は適応等化器1に入力
され、適応等化器1の第1の出力はその出力の絶対値の
自乗をとる絶対値自乗回路2に入力され、絶対値自乗回
路2の出力は減算器3で所定値に減じられ、その減じら
れた値は適応等化器1に入力される。適応等化器1の第
2の出力は乗算器402つの入力の一方に入力され、乗
算器4の出力信号は判定回路5に入力される。判定回路
5の出力は複素共役回路6に入力され、その出力と乗算
器4の出力は乗算器7に入力され、乗算器7の出力は虚
数部抽出回路8に入力され、その出力は切替器11に人
力される。乗算器4の出力は絶対値化回路9に人力され
、絶対値化回路9の出力は比較器10に入力され、その
出力信号で切替器11が制御される。切替器11の出力
はループフィルタ12に入力され、その出力は周波数可
変発振器13に入力され、周波数可変発振器13の出力
は乗算器4の他方の入力になる。
The signal received from the transmission channel is input to an adaptive equalizer 1, and a first output of the adaptive equalizer 1 is input to an absolute value squaring circuit 2 which takes the square of the absolute value of its output, and the first output of the adaptive equalizer 1 is input to an absolute value squaring circuit 2 which takes the square of the absolute value of its output. The output of 2 is subtracted to a predetermined value by a subtracter 3, and the subtracted value is input to an adaptive equalizer 1. The second output of the adaptive equalizer 1 is input to one of the two inputs of the multiplier 40, and the output signal of the multiplier 4 is input to the determination circuit 5. The output of the judgment circuit 5 is input to a complex conjugate circuit 6, the output thereof and the output of the multiplier 4 are input to a multiplier 7, the output of the multiplier 7 is input to an imaginary part extraction circuit 8, and the output is input to a switch 11 will be man-powered. The output of the multiplier 4 is input to an absolute value conversion circuit 9, and the output of the absolute value conversion circuit 9 is input to a comparator 10, and a switch 11 is controlled by the output signal. The output of the switch 11 is input to the loop filter 12 , the output of which is input to the variable frequency oscillator 13 , and the output of the variable frequency oscillator 13 becomes the other input of the multiplier 4 .

適応等化層1はトレーニングを必要とし、一般に相手局
から送出された既知のデータ信号でこのトレーニングを
行う。しかし、マルチポイントなどのスレーブ側変復調
装置の場合には、未知のデータ信号で適応等化器1をト
レーニングする必要が生ずる。第3図に4点の場合のデ
ータ点配置を示し、第4図に128点の場合のデータ点
配置を示す。しかし、図示されているように受信される
データ信号は明確なものでなく、電話回線の劣化による
符号量干渉のためにそのままで判定することが難しく、
さらにデータ点配置が多くなるほど判定の困難さが増大
する。また、適応等化器1を引き込ませる場合に周波数
オフセットの影響を除去しなければならないが、その推
定も困難になる。
The adaptive equalization layer 1 requires training, which is typically done with a known data signal sent by the other station. However, in the case of a slave modem such as a multi-point modem, it becomes necessary to train the adaptive equalizer 1 with an unknown data signal. FIG. 3 shows the data point arrangement in the case of 4 points, and FIG. 4 shows the data point arrangement in the case of 128 points. However, as shown in the figure, the received data signal is not clear, and it is difficult to judge it as it is due to code amount interference due to deterioration of the telephone line.
Furthermore, the more data points are arranged, the more difficult the determination becomes. Further, when the adaptive equalizer 1 is to be pulled in, the influence of frequency offset must be removed, but estimation thereof becomes difficult.

本発明は適応等化器1の引き込みの前段階とし周波数オ
フセットを推定し、ひきつづき適応等化器1を引き込ま
せることにより適応等化器1の負担を軽減することを目
的とする。
The present invention aims to reduce the burden on the adaptive equalizer 1 by estimating the frequency offset as a step before the pull-in of the adaptive equalizer 1 and then letting the adaptive equalizer 1 pull in.

本発明では、たとえば特公昭59−24568号公報で
示される技法により絶対値自乗回路2および減算器3を
用いて適応等化器1を粗に引き込ませ、符号量干渉を減
少させる。すなわち、適応等化器1のタップの修正は次
式に基づき実行される。
In the present invention, the adaptive equalizer 1 is roughly drawn in using the absolute value square circuit 2 and the subtracter 3 using the technique disclosed in Japanese Patent Publication No. 59-24568, for example, to reduce code amount interference. That is, the correction of the taps of the adaptive equalizer 1 is performed based on the following equation.

Cnil =Ch−α′・X7・Y−(l Y、、l 
2R2)ここで、Chはタップ重みベクトル、x、、は
等化層入力信号ベクトル、Yは等化層出力信号、R2は
定数であり、nは時刻nTを表し、Tはサンプリング周
期である。
Cnil = Ch-α'・X7・Y-(l Y,,l
2R2) Here, Ch is a tap weight vector, x, is an equalization layer input signal vector, Y is an equalization layer output signal, R2 is a constant, n represents time nT, and T is a sampling period.

この適応等化器1の出力の符号量干渉は減少しているが
まだ十分ではない。゛したがって、判定回路5の判定点
を第2図のX印に示す位置にして周波数オフセットの修
正をかける。すなわち、複素共役回路6、乗算器7およ
び虚数部抽出回路8で判定回路5が判定した点と乗算器
4の出力(すなわち、受信信号)との位相角が求められ
る。また、乗算器4の出力が小さい場合はSN比が悪い
状態にあるので、絶対値化回路9、比較器10および切
替器11を用いて、乗算器4の出力が第2図の円内にあ
れば修正を行わず円外にあるときに修正をかける。ルー
プフィルタ12は切替器11の出力信号を平均化し、こ
の出力は電話回線の周波数オフセットに依存した量にな
る。周波数可変発振器13はループフィルタ12からの
値に基づき周波数を発振させる。その出力は乗算器4に
入力され、適応等化器1の出力の周波数オフセットを修
正する。
Although the code amount interference of the output of the adaptive equalizer 1 has been reduced, it is still not sufficient. Therefore, the decision point of the decision circuit 5 is set at the position indicated by the X mark in FIG. 2 to correct the frequency offset. That is, the phase angle between the point determined by the determination circuit 5 using the complex conjugate circuit 6, the multiplier 7, and the imaginary part extraction circuit 8 and the output of the multiplier 4 (ie, the received signal) is determined. Also, if the output of the multiplier 4 is small, the S/N ratio is poor, so the absolute value conversion circuit 9, the comparator 10, and the switch 11 are used to adjust the output of the multiplier 4 to within the circle in FIG. If there is, no correction is made and correction is made when it is outside the circle. The loop filter 12 averages the output signal of the switch 11, the output being a quantity dependent on the frequency offset of the telephone line. The variable frequency oscillator 13 oscillates a frequency based on the value from the loop filter 12. Its output is input to a multiplier 4 which corrects the frequency offset of the output of the adaptive equalizer 1.

128点の場合に第2図で示す場所にデータ点はないが
、よりデータ点に依存した(たとえば、8点のデータ点
を設ける)データ点配置よりも周波数オフセット測定の
特性は改善される。
Although there are no data points at the locations shown in FIG. 2 in the case of 128 points, the characteristics of the frequency offset measurement are improved over a data point arrangement that is more data point dependent (e.g., has eight data points).

〔発明の効果〕〔Effect of the invention〕

本発明は、以上説明したように、未知のデータ信号に基
づき適応等化器のトレーニングを行う場合に、適応等化
器により符号量干渉を減少させ、通常のデータ点配置よ
りも少ないデータ点配置による判定を行い、適応等化器
の出力が大きい場合だけ修正するので、周波数オフセッ
トの測定を誤りなく行える効果がある。
As explained above, the present invention reduces code amount interference by using an adaptive equalizer when training an adaptive equalizer based on an unknown data signal, and arranges data points with fewer data points than the normal data point arrangement. Since the determination is made based on the following and correction is made only when the output of the adaptive equalizer is large, the frequency offset can be measured without error.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明実施例の構成を示すブロック構成図。 第2図は本発明で使用するデータ点配置。 第3図は4点の場合のデータ点配置。 第4図は128点の場合のデータ点配置。 1・・・適応等化器、2・・・絶対値自乗回路、3・・
・減算器、4.7・・・乗算器、5・・・判定回路、6
・・・複素共役回路、訃・・虚数部抽出回路、9・・・
絶対値化回路、10・・・比較器、11・・・切替器、
12・・・ループフィルタ、13・・・周波数可変発振
器。 実施例のデータ点配置 第2図 1m データ点配置(4点) 第3図
FIG. 1 is a block configuration diagram showing the configuration of an embodiment of the present invention. Figure 2 shows the data point arrangement used in the present invention. Figure 3 shows the data point arrangement in the case of 4 points. Figure 4 shows the data point arrangement for 128 points. 1...Adaptive equalizer, 2...Absolute value square circuit, 3...
・Subtractor, 4.7... Multiplier, 5... Judgment circuit, 6
...Complex conjugate circuit, ...Imaginary part extraction circuit, 9...
Absolute value conversion circuit, 10... comparator, 11... switching device,
12... Loop filter, 13... Frequency variable oscillator. Example data point arrangement Fig. 2 1m Data point arrangement (4 points) Fig. 3

Claims (1)

【特許請求の範囲】[Claims] (1)直交振幅変調されたデータ信号が到来するデータ
受信器に含まれ、未知のデータ信号に基づきトレーニン
グが行われる適応等化器に接続された周波数オフセット
補正回路において、 周波数可変発振手段(12、13)と、 この周波数可変発振手段の出力信号と上記適応等化器の
出力信号との積を演算する乗算器(4)と、 上記直交振幅変調されたデータ信号のデータ点より少な
いデータ点を有するデータ点配置のデータ点のうち上記
乗算器の出力信号に対応する第一のデータ点に最寄りの
第二のデータ点とこの第一のデータ点との位相差を示す
位相差信号を生成する位相差発生手段(5、6、7、8
)と、 上記乗算器の出力信号の絶対値が所定値より大きいとき
に上記位相差信号に基づき上記周波数可変発振手段の出
力を調整し、また、小さいときはこの調整を禁止する制
御手段(9、10、11)とを備えたことを特徴とする
周波数オフセット補正回路。
(1) In a frequency offset correction circuit connected to an adaptive equalizer which is included in a data receiver to which a quadrature amplitude modulated data signal arrives and is trained based on an unknown data signal, a variable frequency oscillation means (12 , 13), a multiplier (4) for calculating the product of the output signal of the variable frequency oscillation means and the output signal of the adaptive equalizer, and data points smaller than the data points of the orthogonal amplitude modulated data signal. generate a phase difference signal indicating the phase difference between this first data point and a second data point closest to the first data point corresponding to the output signal of the multiplier among the data points of the data point arrangement having Phase difference generating means (5, 6, 7, 8
), and control means (9) that adjusts the output of the variable frequency oscillation means based on the phase difference signal when the absolute value of the output signal of the multiplier is larger than a predetermined value, and prohibits this adjustment when the absolute value is smaller than a predetermined value. , 10, 11).
JP62306591A 1987-12-02 1987-12-02 Frequency offset correction circuit Pending JPH01146448A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62306591A JPH01146448A (en) 1987-12-02 1987-12-02 Frequency offset correction circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62306591A JPH01146448A (en) 1987-12-02 1987-12-02 Frequency offset correction circuit

Publications (1)

Publication Number Publication Date
JPH01146448A true JPH01146448A (en) 1989-06-08

Family

ID=17958909

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62306591A Pending JPH01146448A (en) 1987-12-02 1987-12-02 Frequency offset correction circuit

Country Status (1)

Country Link
JP (1) JPH01146448A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013211688A (en) * 2012-03-30 2013-10-10 Nec Corp Frequency controller, frequency control method and program

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013211688A (en) * 2012-03-30 2013-10-10 Nec Corp Frequency controller, frequency control method and program

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