JPH01143530A - Data transmission equipment - Google Patents

Abstract

PURPOSE:To simplify the constitution of the data transmitter remarkably by transmitting a reciprocal of a coefficient to normalize a prediction residual data so as to use only one dividing circuit. CONSTITUTION:A gain control circuit 15 is a 1/g divider circuit and gain control circuits 17, 41 are multiplier circuits whose multiplier is (g) (where g is a minimum prediction error and 1/G with respect to a gain G at normalizing state). Moreover, a minimum value -Dmin detected by a minimum value detecting circuit 26 is given to the circuit 15 and g=-Dmin is supplied to the circuit 17 and also to the circuit 41 via a latch 52. The circuit 15 applies a division of 1/g of the prediction residual Dt, its output is expressed in equation I, which expresses the normalized prediction residual Dt. Thus, an output of a requantization circuit 16 is expressed in equation II, which stands for the result of requantization of the normalized error Dt/g. The value -Dt/g of equation II is multiplied by (g) by the multiplication of the circuits 17, 41 and becomes the value -Dt and a data -Xt is outputted at a terminal 44. That is only the circuit 15 in the circuits 15, 17, 41 is used as the dividing circuit.

Description

[Detailed description of the invention] The explanation will be given in the following order.

A. Industrial application field B. Summary of the invention C Conventional technology D. Problem that the invention aims to solve E. Means to solve the problem (Figure 1) F. Effect G Example G1 first embodiment (Figure 1) G2 second embodiment (Figure 2) Effect of H invention A. Industrial application field The present invention relates to a data transmission device.

B. Summary of the Invention This invention provides a method for transmitting, in a data transmission device, the reciprocal of a coefficient for normalizing prediction residual data.
This greatly simplifies the configuration.

C. Conventional technology For example, in 8 mm video, as an optional function, the audio signal is digitized into a PCM signal during recording, this PCM signal is recorded in the overscan section of the tape, and the reverse process is performed during playback. It is accepted that the original audio signal can be obtained by performing

In this case, if the sampling frequency and number of quantization bits of the PCM signal are increased, it is possible to record and play back the audio signal with better characteristics. It ends up.

Therefore, when recording, the number of bits of the PCM signal is compressed.
It has been proposed to expand the number of bits during playback so that excellent recording and playback characteristics can be obtained even if the number of bits on the tape is small.

AD is a method of bit compression/expansion.
There is a method called PCM.

FIG. 3 shows an example of a transmission system using this ADPCH. In this example, each 64 consecutive samples of input data is treated as one block, and the order of the prediction filter is set to the optimum value for each block. This is the case when controlling At this time, bit-compressed main data is output for each sample of the human data, and auxiliary data related to the bit compression is output for each l block.

That is, in FIG. 3, (10) is the encoder, (
30) is a signal transmission system, and (40) is a decoder. For example, if it is used for a PCM audio system in 8 mm video, an encoder (10) is provided in a recording system,
The decoder (40) is provided in the reproduction system, and the transmission system (30) includes an error correction processing circuit, a single rotation magnetic head, and the like.

Then, in the encoder (10), the digital data Xt is transmitted in parallel for each sample from the input terminal (11) through the delay circuits (12) and (13) to the subtraction circuit (
14). In this case, the input data Xt is a PCM signal that is A/D converted from an analog audio signal, and the sampling frequency is, for example, 48kHz.
, the number of quantization bits is 16 bits. Also, data
As shown in FIG. 4, it is assumed that t is expressed as a fixed point with -tsxt<t and as a two's complement (the same applies to other values).

Further, the delay circuits (12) and (13) are for synchronizing the timing of the main data and the auxiliary data, and each has a delay time of one block period (
Therefore, strictly speaking, if the input value of the terminal (11) is Xt, the output of the delay circuit (13) will be Xt-12s, but for the sake of complexity, we will write Xt on the car).

Further, the prediction value x t for the data Xt is taken out from the prediction filter (19), and this value 5 (t is
) and from the subtraction circuit (14), the values Xt and 5(
The difference between Dt and t is extracted. This value Di is the predicted value 5i! for the input value Xt! is the error (prediction residual) of t, therefore,
Ideally, the value Dt is Dt −0, and it is generally a small value, so even if the word length of the value Dt is, for example, 16 bits (because it is expressed as a fixed point), for example, Dt - Like “o, ooo...011011”,
All of the significant bits on the MSB side become ``0'' (except the sign bit), and the remaining few bits on the LSB side become ``0'' or ``1'' corresponding to the difference between the value Xt and Nut. Furthermore, when the value Dt becomes a large value, the lower bits can be ignored.

Therefore, this value Dt is supplied to the gain control circuit (15) and multiplied by G (G≧1) to obtain a normalized value D
t-G, and this value G-Dt is used in the requantization circuit (16)
and is requantized, for example, into a 4-bit value t)t-G.

Furthermore, this value 5t-G is supplied to the gain control circuit (17) and multiplied by 1/G, thus giving a non-normalized value 5t of the same order as the value Dt, and this value 5t is then supplied to the adder circuit (17). 18) and a filter (1
The predicted value t from 9) is supplied to the adder circuit (18), and from the adder circuit (18), the sum of the value t and the value t = nu t + 6t is taken out, and this value 55t is It is supplied to a filter (19).

In this case, the value Mt is the predicted value for the value Xt, and the value 5t is the value obtained by truncating or rounding the lower bits of @difference Dt at the time of prediction, so the sum of these values nu t and ff1t The value father t is approximately equal to the input value Xt. Since this value father t was supplied to the filter (19), the value father t which is the filter output
can be a value that predicts the input value Xtφ1 at the next sampling point.

Then, the value f5t-G from the requantization circuit (16) is
The signal is supplied to the decoder (4o) through the transmission system (30).

In this decoder (40), the value 6t-G is multiplied by 1/G by the gain control circuit (41) to obtain the value tSt, and this value ff1t is supplied to the adder circuit (42), and the added output is output from the output terminal. At the same time as being taken out in (44),
Prediction filter (4) configured similarly to filter (19)
3), and the output of the filter is added to the adder circuit (42).
is supplied to

therefore,? The output of the filter (43) becomes the value Rt, and the terminal (44) receives the data father (i.e., the input data
Digital data father t approximately equal to t is retrieved.

Furthermore, the following circuit is provided in order to optimize the orders of the filters (19) and (43).

That is, the prediction filters (19) and (43) are
For example, it is a fourth-order filter that uses PARCOR coefficients, and its first to fourth-order coefficients a1 to a4 can be changed to arbitrary values.

Further, the input data Xt from the terminal (11) is sequentially supplied to the time window circuit (21) and the autocorrelation circuit (22) and subjected to predetermined weighting, etc.
), the Percoll coefficients up to the fourth order are calculated as 1 to 4 for each block of data Xt, and the coefficients 1 to 4 are supplied to the launch (27).

Furthermore, the data Xt from the delay circuit (12) is supplied to a prediction error filter (24), and the filter output is sent to the intra-block maximum value detection circuit (25) and the minimum value detection circuit (24).
6), and its detection output is supplied to the latch (27).

In this case, the filter (24) is the prediction filter (19)
a fourth-order prediction filter (241) configured in the same manner as
The subtraction circuit (242) generates a predicted value (prediction error) 5t of the error Dt with respect to the input data Xt. Also, a detection circuit (25).

(26) detects the pass order of the filter (19) for each block of input data Xt. Processing as shown in FIG. 5 is then performed by circuits (23) to (26).

Note that since the l block has 64 samples, it is expressed as t-1 to t-64 as necessary. That is, i coefficient circuit (
In 23), 4 is calculated as the Percoll order k t ~ up to the 4th order for the block 64 sample input data Xt (=Xx ~XG4).

11 In the filter (24), for one sample of input data Xt (=Xz), the first to fourth coefficients a1 to a4 of the filter (241) are set as al-kl, a2 to a4=0. That is, the order of the filter (24) is set to 1st order, and the prediction error t)t-1 (marked with an x at the top of Xt-XL in FIG. 5) is calculated.

iii Similarly, al-kt * a2-kz * a3 = *a4
−0, that is, the order of the filter (24) is set to second order, and the prediction difference t5t2 (the second cross in X t −X x) is calculated.

iv Similarly, when al-a3-kt A'kx + a+ -0, that is, the order of the filter (24) is set to third, the prediction error is 15ta (the third cross in Xt-Xt). Calculated.

V Furthermore, in the same way, a1 to a4 = kt ~ is set to +, that is, the order of the filter (24) is set to 4th order, and a prediction error of 15ts (lowest x mark in X t - X x) is calculated. be done.

vi The above-mentioned processes Ii to V are sequentially performed for each data Xt of 64 samples of data Xt (-X2 to X64). Therefore, error data (prediction error) 15tt to t5t4 are each 6
You will get 4 pieces each.

vi In the detection circuit (25), the value 5taaxx (
The O mark at the top right end of FIG. 5) is taken out.

i Similarly, 64 pieces of error data t5tt~5
Each absolute value of t4 is a large value 5 wax2~5ma
x4 (marked with a circle in FIG. 2) are each taken out.

In the Ix detection circuit (26), the maximum value i5@aX
0 where the order n of the filter (24) giving the smallest value of max 4 is detected. For example, the value 5 ma
If the value 511axx is the smallest among x1 to 751lax4, this value j5 vsax3 is the filter (24)
Since this is the value when the order n of is 3rd order, it becomes n-3.

The coefficients detected in the xi term and the previous section are supplied with a value of 4 and the value n is supplied to the latch (27), and the coefficients detected in the previous section are supplied with a value of 1 to 4.
Among them, Percoll coefficients of the first order or lower are considered valid, and Percoll coefficients of a higher order than the first order are set to 0 and latched.

For example, if n=3, the coefficients 1 to 3 are left unchanged and k4-0 is latched.

The Percoll coefficient determined as above is 1 to 4.
However, the filter (19) has its first to fourth coefficients a1.
~a4, and is also supplied to the decoder (40) through the transmission system (30), and the first to fourth coefficients a to the filter (43) through the latch (51).
It is set as 1 to a4.

Further, from the detection circuit (26), the minimum value (5111 ns, in the present example, the value 15 max3) of the maximum value eis + axz ~ j5 taax4 in the ix term is taken out, and this minimum value is taken out from the normalized gain calculation circuit (28 ) and is converted into normalized gain G data, G-1715m1n, and this data G is supplied to the gain control circuit (<15).

(17) and is also supplied to the gain control circuit (41) through the launch (52). In this case, Dt
-G-Dt ・/ 5m1n and the value 15m1n is the maximum value i5tmax3 of the value 15t3 when n=3, so the absolute value of the above equation will never exceed "1", and therefore the data Dt-G is normalized to -1≦1)t-G<1.

Furthermore, considering the amount of data transmitted from the encoder (10) to the decoder (40) via the transmission system (30), the main data 15t-G is, for example, 4 bits and 1
The percoll coefficients 1 to 4 and data G, which are auxiliary data, are transmitted for each sample, for example, in 8 bits and 16 bits, respectively, and are transmitted in each block, so the amount of data in one block period is 4 bits x 4 bits. 64 samples + 8 bits x 4 types + 16 bits = 304 bits, and 1 when no data compression is performed.
The amount of data in the block period is 16 bits x 64 samples = 1024 pits. Therefore, the amount of data was compressed and transmitted to 304 bits/1024 bits = 29.7%.

In this way, according to this system, data compression of digital audio data can be performed, but in this case,
In particular, according to this system, even if there are restrictions on coefficients and operation word length, the order of the prediction filter (19) that minimizes the maximum value 5-ax of the prediction error 5it is determined by determining the order of the prediction filter (19).

Since the order of (43) is controlled to M common values according to the human data Xt, errors caused by compression of the decoded data bt can be minimized.

Furthermore, when transmitting the prediction residual Dt, this residual Dt is requantized to reduce the number of bits and normalized before the requantization, so the transmitted data f5t-G is , resulting in data with fewer bits and fewer errors.

Literature: "Fundamentals of Speech Information Processing", patent application published by Ohmsha, 1986
-299285 Specification and Drawing D Problems to be Solved by the Invention However, in the above system, two of the three gain control circuits (15), (17), (41) ), it is necessary to perform the division 1/G in (41). Further, the calculation circuit (28) also needs to perform division by 1/15m1n. That is, circuits (17), (41), (2B)
is composed of a division circuit, but the division circuit has a significantly complicated configuration.

This invention attempts to solve these problems.

E. Means for Solving the Problems Therefore, in the present invention, a line-related predictive coding method is used in which prediction residual data normalized by a normalization coefficient on the encoder side is transmitted to the decoder side to restore the original data. In the data transmission device according to the present invention, the restoration is performed using the reciprocal value of the normalization coefficient transmitted to the decoder.

F Effect There is only one division circuit.

G Example G1 First Example In FIG. 1, the gain control circuit (15) is composed of a division circuit that performs division by 1/g,
), (41) are configured by a multiplication circuit that multiplies by g. However, it is g-1/G.

Also, the minimum value i) detected by the minimum value detection circuit (26)
+in is supplied as the value g (g=l)sin) to the gain control circuits (15) and (17), and is also supplied as the value g to the gain control circuit (41) through the latch (52).

According to such a configuration, in the gain control circuit (15), the value Dt is divided by 1/g, so the output is the value Dt/g, but Dt/g = Dt/ (1
/G) = Dt-G Therefore, the output value Di/g of the control circuit (15) is the value (prediction residual) Dt normalized.

In addition, as a result, the output of the requantization circuit (16) is also the value obtained by requantizing the normalized error Dt/g, 6t/g = t
5t/ (1/G) t5t-G.

This value of 15t/g is the gain control circuit (17).

Since they are doubled by the multiplication of (41), their output becomes the value f5t, and the data father t is output to the terminal (44).

In this way, according to the present invention, digital audio data is compressed. In this case, particularly according to the present invention, the reciprocal g of the gain G when normalizing the prediction residual Dt is obtained, and this value g is Since the transmission is made, the gain control circuits (15) and (17) are used.

Only one circuit (15) of (41) needs to be a division circuit, which simplifies the configuration. In addition, the calculation circuit (28), which was composed of a division circuit, is no longer necessary.
This also simplifies the configuration.

G2 Second Embodiment In the example shown in FIG.
is also compressed and transmitted, and the normalized data D t
This is a case where overflow of /g is prevented.

That is, the error Dt from the subtraction circuit (14) and the prediction error 5t from the filter (24) are ideally equal to Dt
= t5t, but in reality, Dt≠5t may be true, and in this case, the data D from the gain control circuit (15)
t/g is the normalization range.

Overflow may occur from -1≦D t /g < 1. Even if this is not the case, Dt/g=1 cannot be expressed and an overflow will occur.

Furthermore, data g is being transmitted, which is, for example, 16
It is the length of bits, and there are many bits.

Therefore, in the example shown in FIG. 2, the detection circuit (26)
The data f5 win from is supplied to the coefficient circuit (61) and multiplied by b times (0<b<1), for example b=0.9, and this b multiplied value becomes data g(=t)+in・b ).

Then, this data g is supplied to the bit compression circuit (62) and data I! is expressed by an exponent part and a mantissa part. XM
It is compressed to A. That is, now, for example, g−“0.0
00011011011010”, there are consecutive “0”s in the 4 bits from the decimal point, so
For example, 4'' is expressed as a 4-bit binary value and is expressed as 0100''--... as the exponent part EX.In other words, the exponent part EX is the number of consecutive 0's from the decimal point expressed in binary value. This is expressed data.

Furthermore, since the exponent part EX indicates the number of consecutive "0"s from the decimal point, the rEX+1" bit from the decimal point, the 5th bit in this example, is always "1", and therefore, this does not need to be transmitted to the decoder (40) as information.

Then, the lower bits from the rEX+24th bit (in this example, the 6th bit) are 0" or 1w" according to the data g.
Therefore, for example, the lower bit from rEX+2J bit
In the present example, the 4 bits from the 6th bit to the 9th bit are set as "1011"...the mantissa MA, and the remaining lower bits are truncated, for example.

Then, the exponent part EX and the mantissa part MA are serially arranged to form data EXMAHXMA-"01001011", that is, EXMA-EXX2' +MA, and data I! It is said to be XMA. Therefore, 16
Bit data g is 8-bit data t! This means that it is compressed to XMA.

Then, this data EXMA is processed by the bit expansion circuit (63
) and is decompressed into the original data by reverse processing (strictly speaking, the neighbor value with rEX+6J bits and below truncated), and this data g is sent to the gain control circuit (15).
, (17).

Further, data HXMA is further supplied to a bit expansion circuit (64) through a transmission image (3o) and a latch (52) and expanded into data g, and this data g is supplied to a gain control circuit (41). .

Thus, in this example, data g is also compressed and transmitted. Furthermore, when normalizing the error Dt, data g is obtained by multiplying by the coefficient S, so overflow does not occur.

Note that in the above, filters (19), (43
).

In order to be able to change the coefficients a1 to a4 of (241), the circuit for determining these coefficients a1 to a4 should be a memory or a register, and the coefficients 1 to 4 should be loaded into it. , α parameter etc. can also be used as a prediction coefficient.

Furthermore, the processing of the detection circuit (25) and the like can also be executed by a microcomputer and software. Furthermore, a limiter may be applied to the data j5 main to g.

H Effects of the invention According to the invention, the reciprocal g of the gain G when normalizing the prediction residual Dt is determined and this value g is transmitted, so that the gain control circuit (15).

(17), one circuit (15) of (41)
It is sufficient to use only the division circuit as a division circuit, which simplifies the configuration. Furthermore, since the calculation circuit (28), which was comprised of a division circuit, is no longer necessary, the configuration is also simplified from this point of view.

[Brief explanation of the drawing]

FIGS. 1 and 2 are system diagrams of an example of the present invention, and FIGS. 3 to 5 are diagrams for explaining the same. (10) is an encoder, (30) is a signal transmission system, (40
) is a decoder.

Claims (1)

[Claims] In a data transmission device using a line-wise predictive coding method, which transmits prediction residual data normalized by a normalization coefficient on the encoder side to the decoder side to restore original data, the data is transmitted to the decoder. The data transmission device performs the restoration using the reciprocal value of the normalization coefficient.