JPH01143356A - Gto thyristor - Google Patents

Abstract

PURPOSE:To prevent the breakdown of an element due to a spike voltage by forming a structure in which the thickness of the base layer of a GTO thyristor is set under the conditions of a spike voltage resistance at the time of turning OFF. CONSTITUTION:In a GTO thyristor having 4 layers and 3 junctions of P1-N1-P2-N2, the larger the thickness of an N-type base layer becomes, the higher the spike voltage resistance is increased, and the relationship between both is determined by a range surrounded by linear lines A, B. The line A becomes the characteristic of a gradient 1, the line B becomes the characteristic of gradient 1, 2, and it is understood that, to raise the spike voltage resistance required for the thyristor by 1 volt or more, the thickness of the N-type base may be increased by 1-1.2 micrometer. That is, the GTO thyristor can be realized by providing a predetermined spike voltage resistance by forming an element structure in which the ratio of the thickness d(mu) of the N-type base layer to the spike voltage resistance VSP (V) required for the element is d/VSP=1-1.2.

Description

DETAILED DESCRIPTION OF THE INVENTION A. INDUSTRIAL APPLICATION FIELD OF THE INVENTION The present invention relates to a GTO (gate turn-off) sirisk.

B9 Summary of the Invention The present invention provides a structure in which the thickness of the N and base layers is set based on the spike voltage withstand conditions at turn-off in a GTO SIRISK equipped with a 4-layer 3-junction of P+N+P*N2. It is possible to prevent element destruction due to voltage, and to ensure the manufacture of an element with an improved ratio of withstand voltage to controllable current.

C1 Conventional technology GTO (gate turn-off) SIRISK has a self-extinguishing ability using galvanic current, eliminates the need for a commutation circuit required for general SIRISK, and can be used in switch elements such as power converters. It is possible to improve the conversion efficiency and make the device smaller and lighter, and recently it has been widely applied to various power control devices. In particular, since the characteristics of GTO Cyrisk can be exhibited more effectively as the power control device becomes larger, it is desired that GTO Cyrisk has a higher withstand voltage and an increased controllable current.

The withstand voltage of GTO Cyrisk can be designed relatively easily from the specific resistance and thickness of the N base layer, the concentration gradient of the P base layer, etc., so it is a high withstand voltage GT with a withstand voltage class of 4500 volts.
The Othyristor has been put into practical use, and two other high-voltage GTO thyristors have also been announced at the research stage.

On the other hand, the controllable current I TGOM of GTO Cyrisk is
It is known that the following relationship exists.

I TGOM = Goff-1gr CCGoff-V
J+/ρspBwhere, Goff is the current gain, Igr is the gate reverse current, V, , +1 is the reverse voltage between the gate and cathode, and ρSPB is the sheet resistance of the P base layer.

From the above relationship, it is necessary to increase the reverse voltage V J I or decrease the sheet resistance ρSPB in order to increase the controllable current of the GTO Sirisk. Of these, the reverse voltage v
, 71 is limited by increasing the off-gate power supply voltage and increasing the control power.

Therefore, as a method for substantially reducing the sorting resistance .rho.Sr'B, there is a buried gate type GTO circuit not shown in FIG. This GTO thyristor is P.

N, P2 In the N24 layer 3 junction, a high concentration impurity layer P2' with an appropriate pattern such as radial or lattice pattern is provided in the P and base layer to increase the off-gate current from the gate electrode G and to make it similar to the split cathode type. Avoid current concentration. Note that K indicates a cathode electrode and A indicates an anode electrode.

D0 Problems to be solved by the invention The conventional buried gate type GTO silicon risk has a sheet resistance ρ
Although SPB is reduced and the off-gate current is increased by 1gr by using a low-voltage off-gate power supply, there is a problem that the spike voltage generated in the lead wire inductance of the snubber circuit at turn-off causes an excessive instantaneous value of turn-off power loss, causing element destruction.

FIG. 3 shows the waveforms of the anode current IA, the anode-cathode voltage VD, and the power loss Loss, which is the product of both, at the time of turn-off of a general GTO Cyrisk. As is clear from the figure, the power loss Lo of GTO Cyrisk
The instantaneous value of ss becomes the largest at the time when a spike voltage Vsp appears in the voltage VD waveform, and this spike voltage Vsp causes element destruction.

The spike voltage Vsp mentioned above is due to the fact that the snubber circuit component provided for suppressing the overvoltage dv/dt at the time of turn-off of the element includes an inductance component, and it is desired to reduce the inductance component. However, as the withstand voltage of GTO SiRisk becomes higher, the withstand voltage of the snubber circuit components must also be increased, which makes it difficult to reduce the inductance of the circuit components.

From the above, the conventional GTO Cyrisk has a withstand voltage of 3000 volts even if it is a buried gate type.

The controllable current is 30 in a 4500 volt class element.
Those exceeding 0.00 amperes were difficult to put into practical use.

An object of the present invention is to provide an element structure that improves element withstand capability against spike voltages and also improves the ratio of withstand voltage to controllable current.

E6 Means for Solving Problems The present invention has been made to achieve the above object, and
+ N+ P 2 GTo with 4 layers and 3 junctions of N2
In the thyristor, the above N, the thickness d (μ) of the base layer
The ratio with the maximum spike voltage Vsp (V) setting value that does not lead to element destruction at turn-off is d/Vsp = 1.0 ~
1.4.

F9 Effect The present inventors have conducted experiments and research on GTO Cyrisks having various withstand voltages, and have found that the maximum spike voltage that does not lead to element destruction at turn-off (referred to as spike voltage withstand capacity) has almost no relation to the diameter of the element. It was found that the thickness is almost proportional to the thickness of the N base layer. Figure 1 shows the measurement results of the spike voltage withstand capacity (in volts) for GTO Syllisks with various N base layer thicknesses (in micro units), and the spike voltage withstand capacity increases as the N base layer thickness increases. The relationship between the two is defined by the area surrounded by straight lines A and B. Straight line A is the characteristic of the gradient device, and straight line B
is the characteristic of gradient device 2, and it can be seen that the thickness of the N base should be increased by 1 to 1.2 microns in order to increase the spike voltage withstand capacity required for GTO Cyrisk by 1 volt. In other words, the GTO has the desired spike voltage withstand capacity by creating an element structure in which the thickness d (μ) of the N base layer is in proportion to the spike voltage withstand capacity Vsp (V) required for the device. Cyrisk can be realized.

d/Vsp in order to have some margin for practical use.
= 1 to 1.4, preferably 1.1 to 1.3. That is, the lower limit of d/Vsp is determined from the product yield and element withstand voltage with respect to the required spike voltage withstand capability, and the upper limit of d/Vsp is determined from other characteristics such as the rise in on-state voltage of the element.

From the facts up to the second series, it is possible to obtain the desired spike voltage withstand capacity by creating a structure in which the ratio d/Vsp between the thickness d of the N base layer and the spike voltage setting value Vsp is 1 to 1.4. Can be done.

Moreover, conventionally, the thickness d of the N base layer was determined mainly from the viewpoint of withstand voltage, and the controllable current I Tcox was 2000
It has been difficult to commercialize GTO cyrisks of ampere or higher and a ratio of withstand voltage VDM exceeding 8-. This is considered to be due to the fact that the thickness d of the N base layer was made too small considering only the withstand voltage, which led to device destruction due to spike voltage. Regarding this point as well, by limiting the lower limit of the thickness d of the N base layer to the above-mentioned range considering the spike voltage, it is possible to manufacture an element with a ratio of controllable current to withstand voltage exceeding 0.8. become.

G. EXAMPLE Hereinafter, an example of the present invention will be explained in detail in comparison with a conventional element.

In order to obtain a withstand voltage of 4,500 volts in GTO Cyrisk, the N base layer should have a specific resistance of 250 to 350 Ω to CR.
The thickness is approximately 800 lt, and the conventional design also has a thickness of approximately 800 lt.
The thickness of the base layer was set as above.

In this element, when controlling a cutoff current of 3000 amperes, the inductance of the snubber circuit is approximately 0.15
Under μH conditions, the spike voltage is approximately 800 volts.

This spike voltage is lower than the spike voltage withstand voltage of 800 to 960 volts when the thickness of the N base layer is 800 μm from the characteristics shown in FIG.
A controllable current of 3000 amperes can be achieved.

Here, the controllable current is 4500 A with a withstand voltage of 4500 volts.
(ITGOM/VDM=1, 0) requires increasing the element diameter, but the spike voltage Vsp also increases in proportion to this increase in current. This current 4-500
In case A, the spike voltage of the snubber circuit rises to about 1200 volts, and since this value exceeds the spike voltage resistance of the 800 μm thick N base layer, the spike voltage destroys the device.

Here, in the present invention, the device structure is such that the thickness d of the N base layer is limited based on the ratio between the thickness d and the spike voltage withstand capacity Vsp. In this structure, in order to obtain the above-mentioned withstand voltage of 4,500 pols and controllable current of 4,500 amperes, the thickness d of the N base layer is reduced from the spike voltage of 200 volts by the snubber circuit to 12
00 to 1680μ. As an experiment under these conditions,
As a result of prototyping a device in which the thickness d of the N base layer was set to 1300μ and other conditions were the same as before, the spike voltage withstand capacity was 1.
It achieved a controllable current of 4,500 amperes and a withstand voltage of 4,500 volts.

Note that the present invention is not limited to the embedded gate type GTO Cylisk-11, but can be applied to a general GTO Cylisk to obtain the same effect.

H3 Effects of the Invention As described above, according to the present invention, since the thickness of the N base layer is set based on the spike voltage withstand capacity, element breakdown due to spike voltage is more secure compared to the conventional structure where the thickness is set based on the withstand voltage. This has the effect of surely and easily realizing an element with a high ratio of controllable current to withstand voltage.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing the relationship between the thickness of the N base layer and the spike voltage withstand capacity according to the present invention, Fig. 2 is a cross-sectional structural diagram of a buried gate type GTO SIRISK, and Fig. 3 is a waveform diagram of various parts of the GTO SIRISK at turn-off. It is. Go to Figure 1 N.--F thickness and spike voltage resistance! rjI rent, charging layer thickness (2) 200 4006008001000120ON layer thickness j (μ)

Claims (1)

[Claims] GT with 4 layers and 3 junctions of P_1N_1P_2N_2
In the O thyristor, the thickness d (μ) of the N_1 layer is the maximum spike voltage V that does not cause device destruction at turn-off.
A GTO thyristor characterized by having a structure in which the ratio of sp (V) to a set value is d/Vsp=1.0 to 1.4.