JPH01143288A - Manufacture of thick film circuit - Google Patents
Manufacture of thick film circuitInfo
- Publication number
- JPH01143288A JPH01143288A JP62300978A JP30097887A JPH01143288A JP H01143288 A JPH01143288 A JP H01143288A JP 62300978 A JP62300978 A JP 62300978A JP 30097887 A JP30097887 A JP 30097887A JP H01143288 A JPH01143288 A JP H01143288A
- Authority
- JP
- Japan
- Prior art keywords
- thick film
- laser beam
- conductor
- circuit
- resistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title description 3
- 238000000034 method Methods 0.000 claims abstract description 39
- 238000001035 drying Methods 0.000 claims abstract description 13
- 238000010304 firing Methods 0.000 claims description 8
- 239000004020 conductor Substances 0.000 abstract description 29
- 239000000919 ceramic Substances 0.000 abstract description 6
- FFBHFFJDDLITSX-UHFFFAOYSA-N benzyl N-[2-hydroxy-4-(3-oxomorpholin-4-yl)phenyl]carbamate Chemical compound OC1=C(NC(=O)OCC2=CC=CC=C2)C=CC(=C1)N1CCOCC1=O FFBHFFJDDLITSX-UHFFFAOYSA-N 0.000 abstract 1
- 238000001459 lithography Methods 0.000 abstract 1
- 238000000059 patterning Methods 0.000 abstract 1
- 238000007639 printing Methods 0.000 description 8
- 238000009966 trimming Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000001678 irradiating effect Effects 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 2
- SWELZOZIOHGSPA-UHFFFAOYSA-N palladium silver Chemical compound [Pd].[Ag] SWELZOZIOHGSPA-UHFFFAOYSA-N 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000008642 heat stress Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/12—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns
- H05K3/1241—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns by ink-jet printing or drawing by dispensing
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は厚膜ハイブリッドＩｃの厚膜回路を形成する
厚膜回路形成方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a thick film circuit forming method for forming a thick film circuit of a thick film hybrid IC.
第５図および第６図はそれぞれ従来の厚膜回路形成方法
を示す構成図およびフローチャート図である０図におい
て、１４は導体回路１０ａ、１０ｂの印刷工程、１５．
１６は導体回路１０ａ、１０ｂの印刷後のそれぞれ乾燥
および焼成（８５０℃）工程である。１７は抵抗体１）
ａの印刷工程である。１８は回路パターン全体を保護す
るオーバーコート（第５図には図示せず）の印刷、乾燥
および焼成を行なうオーバーコート形成工程であり、１
９は抵抗体１）ａの抵抗値調整（トリミング）工程であ
る。5 and 6 are a block diagram and a flowchart, respectively, showing a conventional thick film circuit forming method. In FIG. 0, 14 is a printing process for conductive circuits 10a and 10b;
16 is a drying and baking (850° C.) step after printing the conductive circuits 10a and 10b, respectively. 17 is resistor 1)
This is the printing process in a. 18 is an overcoat forming step in which an overcoat (not shown in FIG. 5) that protects the entire circuit pattern is printed, dried, and fired;
9 is a resistance value adjustment (trimming) step of the resistor 1)a.
次に各工程について説明する。Next, each process will be explained.
まず導体印刷工程１４において、厚膜導体ペースト（例
えば銀−パラジウム）をセラミック基板９上にスクリー
ン又はマスクにより、電位の異なる回路パターンの導体
回路ｉｏａ、１０ｂを印刷する。次に乾燥工程１５にお
いて、印刷した導体ペースト中の有機溶剤成分揮発のた
め１２０℃前後で乾燥し、次いで焼成工程１６において
、導体ペースト中のガラス成分とセラミックのアルミナ
粒界層の融着結合のため焼成（８５０℃）加熱する０次
に抵抗体印刷工程１７において、抵抗ペーストを印刷し
、導体ペーストと同様、乾燥工程１５および焼成工程１
６を行なう。抵抗体印刷工程１７と次の乾燥工程１５は
抵抗体ペーストの種類毎（例えば１００Ω／０．１０に
Ω／口など）に繰り返して抵抗体１）ａ群を形成する。First, in a conductor printing step 14, conductor circuits ioa and 10b having circuit patterns having different potentials are printed using a thick film conductor paste (for example, silver-palladium) on the ceramic substrate 9 using a screen or a mask. Next, in a drying step 15, the printed conductor paste is dried at around 120°C to volatilize the organic solvent component, and then in a firing step 16, the glass component in the conductor paste and the alumina grain boundary layer of the ceramic are fused and bonded. In the zero-order resistor printing step 17 of heating (850° C.), the resistor paste is printed, and as with the conductor paste, it is subjected to a drying step 15 and a firing step 1.
Do step 6. The resistor printing step 17 and the subsequent drying step 15 are repeated for each type of resistor paste (for example, 100Ω/0.10, Ω/hole, etc.) to form resistor 1) a group.
次にオーバーコート形成工程１８においては、形成した
全部の導体１０ａ、１０ｂおよび抵抗体１）ａを保ｇｔ
（特に湿気環境）するため、保護膜（オーバーコート）
を印刷・乾燥・焼成する。最後にトリミング工程１９に
おいてオーバーコートの上から抵抗体１）ａの抵抗値を
所定値まで、レーザ光などを用いて、トリミング１３（
抵抗体カット調整）を行ない、厚膜回路基板を製造する
。Next, in the overcoat forming step 18, all the formed conductors 10a, 10b and resistor 1)a are maintained.
(especially in a humid environment), a protective film (overcoat)
Print, dry, and fire. Finally, in a trimming step 19, the resistance value of the resistor 1)a is reduced from above the overcoat to a predetermined value by using a laser beam or the like.
(resistance cut adjustment) to manufacture thick film circuit boards.
従来の厚膜回路基板は以上のように構成されているので
、回路パターン毎にスクリーンを準備しなければならず
、また使用ペーストの種類だけ（導体、抵抗体３〜４種
、オーバーコート）印刷。Conventional thick film circuit boards are constructed as described above, so a screen must be prepared for each circuit pattern, and only the type of paste used (conductor, 3 to 4 types of resistors, overcoat) can be printed. .
乾燥、焼成を繰り返すことが必要で製造時間が長く、さ
らに熱ストレス履歴による品質低下も避けられず、さら
に抵抗体の抵抗値は後工程で焼成してみないと分からな
いなどの問題点があった。There are other problems, such as requiring repeated drying and firing, which takes a long manufacturing time, and quality deterioration due to heat stress history is unavoidable.Furthermore, the resistance value of the resistor cannot be determined until it is fired in the subsequent process. Ta.
この発明は上記のような問題点を解消するためになされ
たもので、多種類の厚膜回路がスクリーンなしで形成で
きるとともに熱ストレスを軽減し、抵抗値を測定しなが
ら焼成できる厚膜回路形成方法を提供することを目的と
する。This invention was made to solve the above-mentioned problems, and it is possible to form many types of thick film circuits without a screen, reduce thermal stress, and make it possible to form thick film circuits while measuring resistance values. The purpose is to provide a method.
この発明に係る厚膜回路形成方法は、ベース上に厚膜直
接描画によって回路を描く描画工程と、該描画工程で描
かれた回路をレーザ光で走査することにより乾燥、焼成
を行なう乾燥、焼成工程とを含むものである。The method for forming a thick film circuit according to the present invention includes a drawing step in which a circuit is drawn on a base by direct drawing of a thick film, and a drying and baking process in which the circuit drawn in the drawing step is dried and baked by scanning it with a laser beam. It includes a process.
この発明における厚膜回路形成方法は、ベース上に厚膜
直接描画にて回路を描くとともに、該回路をレーザ光で
走査することにより乾燥、焼成を行なうようにしたから
、スクリーンが不要となるとともに乾燥、焼成工程が大
巾に縮減できる。The method for forming a thick film circuit according to the present invention involves drawing a circuit on a base by direct drawing of a thick film, and then drying and baking the circuit by scanning the circuit with a laser beam, which eliminates the need for a screen. Drying and firing processes can be greatly reduced.
以下、この発明の一実施例を図について説明する。第１
図、第２図はそれぞれ本発明の一実施例による厚膜回路
形成方法を示す構成図およびフローチャート図であり、
図において、１は厚膜描画機ノズル７によりセラミック
ベース９の上に導体回路１０ｃ、１０ｄを描く導体描画
工程、２はレーザ光ヘッド８により導体回路１０ｃ、１
０ｄを照射するレーザ光照射工程、３は導体描画工程と
同様に描画機ノズル７により抵抗体１）ｂを描く抵抗体
描画工程、４は抵抗値を測定しながら抵抗体１）ｂにレ
ーザ光を照射する工程である。５は描画機ノズルにより
オーバーコート（第３図には図示せず）を描くオーバー
コート描画工程である。An embodiment of the present invention will be described below with reference to the drawings. 1st
FIG. 2 is a block diagram and a flowchart diagram respectively showing a method for forming a thick film circuit according to an embodiment of the present invention.
In the figure, 1 is a conductor drawing process in which conductor circuits 10c and 10d are drawn on a ceramic base 9 by a thick film drawing machine nozzle 7, and 2 is a conductor circuit drawing process in which conductor circuits 10c and 10d are drawn by a laser beam head 8.
3 is a resistor drawing step in which the resistor 1) b is drawn using the drawing machine nozzle 7 in the same way as the conductor drawing step; 4 is a laser beam irradiation step to irradiate the resistor 1) b while measuring the resistance value. This is the process of irradiating. 5 is an overcoat drawing step in which an overcoat (not shown in FIG. 3) is drawn by a drawing machine nozzle.
６は抵抗体１）ｂの抵抗値を調整するトリミング工程で
ある。6 is a trimming step for adjusting the resistance value of the resistor 1)b.
次に各工程について説明する。Next, each process will be explained.
まず導体描画工程１において導体ベース）１０（例えば
銀−パラジウム）を、従来のようにスクリーンを用いて
印刷を行なう代わりに厚膜描画機ノズル７を用い、直接
セラミックベース９上に導体回路ｔｏｃ、１０ｄを描く
。次にレーザ光照射工程２において従来の乾燥（１２０
℃）、焼成に相当する工程をレーザ光を用いて行なう。First, in a conductor drawing step 1, a conductor base (for example, silver-palladium) is printed directly on a ceramic base 9 by using a thick film drawing machine nozzle 7 instead of printing using a screen as in the conventional case. Draw 10d. Next, in laser light irradiation step 2, conventional drying (120
℃), and a step corresponding to firing is performed using laser light.
レーザ光は例えば波長１．０６μｍの赤外線ＹＡＧレー
ザ光を照射し、焼成加熱（８５０’ｃ）を行う。レーザ
光ヘッド８は描画機ノズル７の動作情報（ＮＣ）（第４
図の実線経路）をそのまま適用する。導体回路９ｃ、９
ｄのレーザ光照射は一導体パターンづつでもよいし、全
ての導体回路を連続して行なってもよい、抵抗体描画工
程３及びこれに続く工程４による抵抗体形成は、導体の
形成工程１，２と同様に描画機ノズル７とレーザ光ヘッ
ド８を用いて行なうが、工程３で導体ペーストの代わり
に抵抗体ペーストを使用する点、及び工程４におけるレ
ーザ光照射方法が異なる。即ち、抵抗体１）ｂへのレー
ザ光照射は抵抗値を測定しなからレーザ光を抵抗体１）
ｂの端から、電流方向、次に反対方向と連続して走査し
、所望の抵抗値またはその手前まで照射する。（第４図
の点線経路）その際、設定抵抗値までの微調整は後工程
６で抵抗体のカプト調整（トリミング）により行なうの
で、レーザ光照射による抵抗値は設定値を越えないよう
にする。次にオーバーコート描画工程５とこれに続くレ
ーザ光照射工程２によるオーバーコート形成は導体の形
成工程１．２と同様に描画機ノズル７とレーザ光ヘッド
８を用いて行なうが、工程５において導体ペーストの代
わりにオーバーコートペーストを使用する。最後に、工
程６の抵抗トリミングは必要の場合のみ従来と同様、レ
ーザ光を用いて抵抗体１）ｂをカットする。抵抗体１）
ｂは前の工程４において抵抗値を測定しなからレーザ光
照射しているので、抵抗値精度が低くても構わない場合
（±１０％前後）には抵抗トリミング工程６が不要とな
る場合もある。The laser beam is, for example, an infrared YAG laser beam with a wavelength of 1.06 μm, and firing and heating (850'c) is performed. The laser light head 8 receives operation information (NC) (fourth
The solid line route in the figure) is applied as is. Conductor circuits 9c, 9
The laser beam irradiation in d may be applied to one conductor pattern at a time, or all conductor circuits may be irradiated continuously.The resistor formation in the resistor drawing step 3 and the subsequent step 4 is performed in the conductor forming steps 1 and 2. The drawing machine nozzle 7 and the laser beam head 8 are used in the same manner as in the above, but the difference is that in step 3, a resistor paste is used instead of the conductive paste, and in the method of laser beam irradiation in step 4. That is, before irradiating the laser beam onto the resistor 1)b, do not measure the resistance value before irradiating the laser beam onto the resistor 1).
Starting from the end of b, scan in the current direction and then in the opposite direction, and irradiate until the desired resistance value or just before it. (Dotted line path in Figure 4) At this time, fine adjustment to the set resistance value is performed by capt adjustment (trimming) of the resistor in the subsequent process 6, so make sure that the resistance value due to laser beam irradiation does not exceed the set value. . Next, overcoat formation in the overcoat drawing step 5 and the subsequent laser beam irradiation step 2 is performed using the drawing machine nozzle 7 and the laser beam head 8 in the same manner as in the conductor formation step 1.2. Use overcoat paste instead of paste. Finally, in step 6, resistor trimming involves cutting the resistor 1)b using a laser beam, as in the conventional method, only when necessary. Resistor 1)
In b, the laser beam is irradiated without measuring the resistance value in the previous step 4, so if the resistance value accuracy is low (around ±10%), the resistance trimming step 6 may not be necessary. be.
なお、上記実施例では、描画機ノズル７に円筒形のもの
を示したが、ノズル先端の形状が矩形であれば描画時間
が少なくてすみ、効率がよくなる。In the above embodiment, the drawing machine nozzle 7 is cylindrical, but if the shape of the nozzle tip is rectangular, the drawing time will be shorter and efficiency will be improved.
また、描画機ノズル７とレーザ光ヘッド８は同一の機械
装置としてＮＧ情報を共用する方式にて説明したが、各
別個の機械装置でもよく、上記実施例と同様の効果を奏
する。Further, although the drawing machine nozzle 7 and the laser beam head 8 are the same mechanical device and share the NG information, they may be separate mechanical devices, and the same effects as in the above embodiment can be obtained.
以上のようにこの発明によれば、従来の厚膜回路の印刷
〜焼成工程を直接描画とレーザ光照射工程に代替したの
で、スクリーンが不要となり、また、焼成時間（２０分
〜６０分）が大巾に縮減（焼成時間５分前後）でき、低
コスト、短納期化に効果がある。また従来のような焼成
の繰り返し熱履歴がないため、品質信軌性の高いものが
得られる。さらにスクリーンを用いないので、回路変更
に柔軟に対応でき、開発試作研究のような多種、短納期
の厚膜回路を形成するのに有効である。As described above, according to the present invention, the conventional thick film circuit printing to baking process is replaced with direct drawing and laser beam irradiation process, so a screen is not required and the baking time (20 minutes to 60 minutes) is shortened. It can be greatly reduced in width (baking time is around 5 minutes), which is effective in reducing costs and shortening delivery times. Furthermore, since there is no repeated thermal history of firing as in the past, products with high quality reliability can be obtained. Furthermore, since no screen is used, it is possible to flexibly respond to circuit changes, and is effective for forming thick film circuits of various types and with short delivery times, such as those used in development and prototyping research.
第１図はこの発明の一実施例による厚膜回路形成方法を
示すフローチャート図、第２図は本発明に用いる厚膜回
路形成装置の装置部分説明図、第３図は本発明の厚膜回
路形成方法により形成される厚膜回路基板の斜視図、第
４図はレーザ光ヘッド経路を示す図、第５図は従来の厚
膜回路形成方法により形成される厚膜回路基板を示す斜
視図、第６図は従来の厚膜回路形成方法を示すフローチ
ャート図である。
１は導体描画工程、２はレーザ光照射工程、３は抵抗体
描画工程、４はレーザ光照射と抵抗値測定工程、５はオ
ーバーコート描画工程、６は抵抗トリミング工程、７は
描画機ノズル、８はレーザ光ヘッド、９はセラミックベ
ース、１０は導体ペースト、１０ｃ及び１０ｄは導体回
路、１）は抵抗体ペースト、Ｉｌｂは抵抗体、１２はオ
ーバーコートペースト。
なお図中同一符号は同−又は相当部分を示す。FIG. 1 is a flowchart showing a thick film circuit forming method according to an embodiment of the present invention, FIG. 2 is a partial explanatory diagram of a thick film circuit forming apparatus used in the present invention, and FIG. 3 is a thick film circuit of the present invention. A perspective view of a thick film circuit board formed by the forming method, FIG. 4 is a diagram showing a laser beam head path, and FIG. 5 is a perspective view of a thick film circuit board formed by a conventional thick film circuit forming method. FIG. 6 is a flowchart showing a conventional thick film circuit forming method. 1 is a conductor drawing process, 2 is a laser beam irradiation process, 3 is a resistor drawing process, 4 is a laser beam irradiation and resistance value measurement process, 5 is an overcoat drawing process, 6 is a resistor trimming process, 7 is a drawing machine nozzle, 8 is a laser optical head, 9 is a ceramic base, 10 is a conductor paste, 10c and 10d are conductor circuits, 1) is a resistor paste, Ilb is a resistor, and 12 is an overcoat paste. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (1)
ドＩＣを作製する厚膜回路形成方法において、 厚膜直接描画法により回路を描画する工程と、描画され
た回路をレーザ光で走査して、乾燥・焼成を行なう乾燥
・焼成工程とを含むことを特徴とする厚膜回路形成方法
。(1) A thick film circuit forming method in which a circuit is formed using a thick film paste to produce a thick film hybrid IC, which includes a step of drawing a circuit using a thick film direct drawing method, scanning the drawn circuit with a laser beam, A method for forming a thick film circuit, comprising a drying and firing process.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62300978A JPH01143288A (en) | 1987-11-28 | 1987-11-28 | Manufacture of thick film circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62300978A JPH01143288A (en) | 1987-11-28 | 1987-11-28 | Manufacture of thick film circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01143288A true JPH01143288A (en) | 1989-06-05 |
Family
ID=17891365
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62300978A Pending JPH01143288A (en) | 1987-11-28 | 1987-11-28 | Manufacture of thick film circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01143288A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10050629B4 (en) * | 1999-10-13 | 2005-06-09 | Yazaki Corp. | Method for producing a three-dimensional circuit body and device for carrying out the method |
| JP2007143292A (en) * | 2005-11-18 | 2007-06-07 | Cosel Co Ltd | Parallel operation power supply system |
| US7311937B2 (en) | 2001-10-31 | 2007-12-25 | Seiko Epson Corporation | Method for forming a line pattern, line pattern, and electro-optic device |
-
1987
- 1987-11-28 JP JP62300978A patent/JPH01143288A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10050629B4 (en) * | 1999-10-13 | 2005-06-09 | Yazaki Corp. | Method for producing a three-dimensional circuit body and device for carrying out the method |
| US7311937B2 (en) | 2001-10-31 | 2007-12-25 | Seiko Epson Corporation | Method for forming a line pattern, line pattern, and electro-optic device |
| JP2007143292A (en) * | 2005-11-18 | 2007-06-07 | Cosel Co Ltd | Parallel operation power supply system |
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