JPH01142956A - Cache storage device - Google Patents

Abstract

PURPOSE:To attain a high speed access by arranging at least one side of a tag memory and a bit detecting part on the same substrate as a master device. CONSTITUTION:Ordinarily, the material to occupy almost the mounting area out of a cache memory device 3 is a data memory 11 and the mounting area of a tag memory 12 and a bit detecting part is comparatively small. Then, a tag memory 12 and a high detecting part 13 are arranged on a same board 14 as a processor 1. Thus, the exchanging can be executed without passing through a cable between the processor 1 and the tag memory 12 and the bit detecting part 13 and the propagation delaying between them can be canceled.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a cache storage device provided between a master device and a main storage device to enable high-speed access to memory.

(Prior Art) Conventionally, in order to improve the speed of memory access, a relatively small but high-speed device has been installed between a master device such as a central processing unit and a main storage device using a large-capacity memory IC. Equipped with accessible cache storage devices. This cache storage device is a memory that reads frequently accessed data from the main storage device and stores it, and contributes to improving overall memory access speed by being accessed by the central processing unit instead of the main storage device. It is something to do.

This cache storage device usually includes a data memory, a tag memory, and a hit detection section.

The tag memory also contains information about which address in the main memory the data stored in the data memory corresponds to.
Alternatively, it holds information such as whether the stored data is valid. To access the cache storage device, the tag memory is first referred to, and if the address stored in the tag memory matches the address from the central processing unit (cache hit), the cached data is accessed. is the read/write target, and if they do not match (mishit), the data is exchanged between the main storage device and the data memory, and at the same time, the contents of the tag memory are updated to the new address.

In this way, the access time to the cache storage device is determined by the reference processing time to the tag memory and the access time to the data memory. Therefore, in order to realize a high-speed cache storage device, not only is it necessary to use a high-speed data memory, but also a high-speed tag memory is required.

Furthermore, in a system using a cache storage device, the access time can be improved as the degree to which data to be accessed by the central processing unit is stored in the data memory (Hira1-ratio) is higher. Therefore, if the capacity of the cache storage device is small, the hit rate will not increase and the effectiveness of the cache storage device will not be obtained. For this reason, it is desirable for the cache storage device to have a large capacity, and as a result, the mounting area must also be relatively large. For this reason, this type of system typically uses cache storage as
It is configured independently on a board separate from the central processing unit, and this board and the central processing unit board are connected using a cable or the like.

However, with this configuration, the signal propagation delay between the central processing unit and the cache storage device is large due to the capacitive load of the cable, and the data memory and tag memory are However, there was a problem in that the access speed could not be increased.

(Problems to be Solved by the Invention) As described above, in the conventional cache storage device, it is difficult to improve the access speed due to the length of the transmission between the master device and the cache storage device. The problem was that I couldn't do it.

The present invention has been made to solve these problems, and is aimed at improving communication between the master device and the cache storage device.
It is an object of the present invention to provide a cache storage device that can improve access speed by eliminating N extension as much as possible.

[Structure of the Invention] (Means for Solving the Problems) The present invention provides a data memory consisting of a high-speed memory, a storage location of data stored in this data memory in a main storage device, and whether the stored data is valid or invalid. a tag memory that stores this information; and a human detection unit that outputs information as to whether access to the data memory by the master device is valid or invalid based on the address output from the master device and the contents of the tag memory. The cache storage device is characterized in that at least one of the tag memory and the hit detection section is disposed on the same board as the master device.

(Function) Normally, the data memory occupies most of the mounting area of the cache storage device, and the actual area of the tag memory and hit detection section is relatively small. Therefore, it is possible to arrange these on the same board as the master device.

According to the present invention, since the tag memory and the human detection section are arranged on the same board as the master device, communication can be performed between the master device and the tag memory and the human detection section without using a cable. , the propagation delay between them can be eliminated. Therefore, efficient tag detection processing can be performed and high-speed access is possible.

(Example) Hereinafter, an example of the present invention will be described based on the drawings.

FIG. 1 is a diagram showing a system using a cache storage device according to this embodiment.

That is, this system has a processor 1 which is a master device.
and a main memory 2 consisting of a large capacity memory, and a cache storage device 3 is arranged between the main memory 2 and the main memory 2 consisting of a large capacity memory.

The cache storage device 3 caches a part of the data stored in the main memory 2, and has a data memory 11 which has a smaller capacity than the main memory 2 and can be accessed at high speed, and a data memory 11 that caches a part of the data stored in the main memory 2. A tag memory 12 that stores an address field (upper bits of the address) on the main memory 2 and a valid flag indicating validity/invalidity of stored data; The hit detecting section 13 detects whether the access of the processor 1 is a cash hit or a miss based on the contents, and outputs an H/M signal indicating the access to the processor 1.

In this system, a processor 1, a tag memory 12, and a hit detection section 13 are configured on the same board 14, and the processor 1, tag memory 12, and hit detection section 1
3 are arranged close to each other so that the wiring connecting them is as short as possible. Furthermore, since the data memory 11 has a relatively large mounting area, it is configured on a separate board (not shown) from the board 14 described above. And board 14
An address bus 15, a data bus 16, and a control bus 17 connecting the data memory 11 and the data memory 11 are constructed using cables or the like.

Next, the operation of the cache storage device 3 when the processor 1 accesses the cache storage device 3 according to this embodiment will be described.

First, when the processor 1 outputs the address to be accessed, the address field specified by the lower bits of the address and the valid/invalid data indicating the validity/invalidity of the data are extracted from the tag memory 12 located close to the same board 14 as the processor 1. The flag is read out, and the hit detection unit 13
is output to.

The above address from the processor 1 is also input to the hit detection section 13 . If the upper bits of the address from the processor 1 match the address field read from the tag memory 12 and the validity flag is 1 (valid), the hit detection unit 13 outputs a hit signal H as a cash hit. , address field mismatch, or
When the valid flag is O (invalid), a miss signal M is output as a miss. The hit signal H or miss signal M from the hit detection section 13 is immediately input to the processor 1 disposed close to each other on the same board. The processor 1 immediately accesses the data memory 11 when the hit signal @H is input. Also,
When the mishit signal M is input, the correct data is read from the main memory 2, and the data memory 1
Load data from main memory 2 to tag memory 12.
The contents will be updated accordingly.

FIG. 2(a) shows a timing diagram of tag reference in the conventional cache storage device, and FIG. 2(b) shows a timing diagram of tag reference in the cache storage device 3 of this embodiment.

That is, in conventional cache storage devices, there is a delay T1 due to propagation delays caused by cables, etc., between when an address is output from the processor and when this address is given to the tag memory.
exists, and the output H/M of the hit detection unit from address assignment
There is a slight delay T2 until the output of
It took 2+T3 time.

However, according to the cache storage device 3 of this embodiment, all tag references are performed within the board 14, and the tag reference time does not include the propagation delay due to the cable.
As shown in b), the tag reference is completed in an extremely short time (TI'+T2+T3'), and processing corresponding to the cache hit/cache miss can be quickly executed.

In this way, according to this embodiment, the cache storage device 3
Since the tag reference time can be greatly reduced, the overall access speed can also be greatly improved.

Note that the present invention is not limited to the above embodiments.

For example, in the above embodiment, the processor 1, the tag memory 12, and the hit detection unit 13 are simply configured on the same board 14, but if you go further and configure them on the same chip, these will be further integrated. The propagation delay between the two is reduced, and the effects of the present invention are further improved.

Further, in the above embodiment, both the tag memory 12 and the hit detection section 13 are configured on the same board as the processor 1, but for example, only the tag memory 12 or the hit detection section 13 is configured on the same board.
It is possible to partially eliminate the propagation delay when referring to a tag by configuring only the processor 1 on the same board, and the effects of the present invention can be achieved.

Further, in the above embodiment, the present invention is applied to a system using a processor as a master device, but it goes without saying that the present invention can also be applied to a disk device having a DMA controller I/roller as a master device, etc. There is no.

[Effects of the Invention] As described above, according to the present invention, at least one of the tag memory and the hit detection section 13 is disposed on the same board as the master device, so that access to the cache storage device is easy. A 1M transmission line such as a cable is not included in the tag reference operation, and as a result, the tag reference time can be shortened without using an expensive high-speed memory, and high-speed access is possible.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a system using a cache storage device according to an embodiment of the present invention, and FIG. 2 is a diagram showing the timing of the tag reference operation of the same cache storage device in comparison with a conventional example. There is 1...processor, 2...
Main memory, 3... Cache storage device, 11... Data memory, 12... Tag memory, 13... Hit detection section, 14... Board, 15... Address bus,
16...Data bus, 17...Control bus. Applicant's agent Patent attorney Takehiko Suzue Figure 2

Claims (4)

[Claims] (1) A cache storage device disposed between a master device and a main storage device, which includes a data memory consisting of a high-speed memory, a storage location in the main storage device of the data stored in this data memory, and the storage location of the data stored in the data memory, and a tag memory that stores information on whether data is valid or invalid; and a tag memory that stores information on whether access to the data memory by the master device is valid or invalid based on the address output from the master device and the contents of the tag memory. A cache storage device comprising a hit detection section for outputting an output, wherein at least one of the tag memory and the hit detection section is arranged on the same substrate as the master device. . (2) The cache storage device according to claim 1, wherein at least one of the tag memory and the hit detection section is housed in the same chip as the master device. (3) The cache storage device according to claim 1, wherein the master device is a processor. (4) The master device is a DMA in a disk device.
2. The cache storage device according to claim 1, wherein the cache storage device is a (DirectMemoryAccess) controller.