JPH01142055U - - Google Patents

Info

Publication number
JPH01142055U
JPH01142055U JP3750488U JP3750488U JPH01142055U JP H01142055 U JPH01142055 U JP H01142055U JP 3750488 U JP3750488 U JP 3750488U JP 3750488 U JP3750488 U JP 3750488U JP H01142055 U JPH01142055 U JP H01142055U
Authority
JP
Japan
Prior art keywords
microprocessor
socket
circuit emulator
cpu
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3750488U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP3750488U priority Critical patent/JPH01142055U/ja
Publication of JPH01142055U publication Critical patent/JPH01142055U/ja
Pending legal-status Critical Current

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  • Test And Diagnosis Of Digital Computers (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案に係るインサーキツト・エミユ
レータの要部構成図、第2図はプロービング方式
についての構造を詳細に示す構成図、第3図は従
来のインサーキツト・エミユレータの一例を示す
概念的構成図である。 10……ピギーエバチツプ、11……エミユレ
ーシヨンCPU、12……メモリ、13……内蔵
入出力I/Oポート、20……インサーキツト・
エミユレーシヨン・プローブ、30……I/O信
号サンプル・プローブ、31……ソケツト。
Fig. 1 is a block diagram of the main parts of the in-circuit emulator according to the present invention, Fig. 2 is a block diagram showing the structure of the probing method in detail, and Fig. 3 is a conceptual block diagram showing an example of a conventional in-circuit emulator. It is. 10... Piggy Eva chip, 11... Emulation CPU, 12... Memory, 13... Built-in input/output I/O port, 20... In-circuit
Emulation probe, 30... I/O signal sample probe, 31... socket.

Claims (1)

【実用新案登録請求の範囲】 マイクロプロセツサのCPUにユーザの用途に
応じて設計された周辺デバイスをチツプ内に組み
込んだユーザオリジナルのマイクロプロセツサを
対象とするインサーキツト・エミユレータであつ
て、 前記CPUにプロービングするためのコネクタ
を持つインサーキツト・エミユレータ・プローブ
と、ターゲツトICソケツトと1対1に結合でき
前記チツプ内の周辺デバイスにプロービング可能
なソケツトを有するI/O信号サンプル・プロー
ブとを具備し、I/O信号サンプル・プローブの
ソケツトを介して前記マイクロプロセツサをター
ゲツトICソケツトに結合すると共にマイクロプ
ロセツサにはインサーキツト・エミユレータ・プ
ローブを接続することにより、CPUと周辺デバ
イスとの両方に同時にプロービングできるように
したことを特徴とするインサーキツト・エミユレ
ータ。
[Claims for Utility Model Registration] An in-circuit emulator intended for a user's original microprocessor in which peripheral devices designed according to the user's application are incorporated into the microprocessor's CPU chip, said CPU an in-circuit emulator probe having a connector for probing the chip; and an I/O signal sample probe having a socket that can be coupled one-to-one with a target IC socket and capable of probing peripheral devices within the chip; By coupling the microprocessor to a target IC socket via an I/O signal sample probe socket and connecting an in-circuit emulator probe to the microprocessor, both the CPU and peripheral devices can be probed simultaneously. An in-circuit emulator that is characterized by the ability to
JP3750488U 1988-03-22 1988-03-22 Pending JPH01142055U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3750488U JPH01142055U (en) 1988-03-22 1988-03-22

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3750488U JPH01142055U (en) 1988-03-22 1988-03-22

Publications (1)

Publication Number Publication Date
JPH01142055U true JPH01142055U (en) 1989-09-28

Family

ID=31264084

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3750488U Pending JPH01142055U (en) 1988-03-22 1988-03-22

Country Status (1)

Country Link
JP (1) JPH01142055U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04370840A (en) * 1991-06-19 1992-12-24 Matsushita Electric Ind Co Ltd System development assistance device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04370840A (en) * 1991-06-19 1992-12-24 Matsushita Electric Ind Co Ltd System development assistance device

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