JPH01140741A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To reduce a resistance value of a word line to be connected to a memory cell and to shorten an input/output delay time by a method wherein the word line is constituted by a metal line or a polysilicon line connected in parallel. CONSTITUTION:A word line 3a for bypass use extended in a longitudinal direction in parallel with a word line 3 is formed by a polysilicon layer; the word line 3 and the word line 3a are connected by a polysilicon layer 10 and are arranged in parallel. When the word line 3a is formed as wide as the word line 3 and the two word lines 3, 3a are connected commonly to three memory cells 6-1-6-3, a resistance value of the word lines 3, 3a per memory cell becomes 1/2 of a resistance value of the polysilicon layer; accordingly, a whole resistance value of the word lines 3, 3a becomes 1/2 of the word line 3. By this setup, the resistance value of the word line can be reduced, and an input/ output delay time of a memory device can be shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to ROM, FROM, EPROM% EEE F
ROM, RAM, PAL (Programma
The present invention relates to a semiconductor memory device including a large number of memory elements, such as BLE Array Logic).

(Prior Art) FIG. 5 shows one memory cell of a mask ROM memory device.

1 is a drain diffusion region, 2 is a source diffusion region, and between both diffusion regions 1 and 2, a word line 3 which also serves as a gate electrode is formed vertically in the figure.
The lower part of the gate electrode 3 in between is a channel region, and depending on whether or not ion implantation is performed in the channel region, the threshold value is controlled and information is recorded in the memory cell. Reference numeral 4 denotes a bit line extending laterally in the figure, and is connected to the drain region 1 via a contact hole. Reference numeral 5 denotes a ground line extending laterally in the figure, and is connected to the source region 2 via a contact hole. In the figure, field oxide films, interlayer oxide films, and the like are omitted.

The word line 3 is usually formed by a polysilicon layer. The word line 3 is commonly connected to a plurality of memory cells arranged vertically in the figure.

The bit line 4 and the ground line 5 are formed of a metal layer and are commonly connected to a plurality of memory cells arranged laterally in the figure.

FIG. 6 shows an equivalent circuit in which three memory cells are connected in the vertical direction.

6-1 to 6-3 each represent a memory cell, and 4-1
4-3 represents bit lines.

Word line 3 is commonly connected to three memory cells 6-1 to 6-3. 7 is a driver circuit for driving the word line 3;

If the resistance value of the polysilicon layer of word line 3 per memory cell is Rp, three memory cells 6-1 to 6-6
The resistance of word line 3 for -3 will be 3Rp.

As the memory capacity increases, the resistance value of the word line 3 increases, which adversely affects the input/output delay time of the memory device.

The good luck caused by increasing the resistance value of the word line 3 is not limited to ROM but also applies to other memory devices.

(Objective) An object of the present invention is to provide a memory device that can shorten input/output delay time by reducing the resistance value of word lines connecting memory cells with a polysilicon gate structure. be.

(Structure) In the present invention, the word line is formed of a metal line or a polysilicon line connected in parallel.

Examples will be specifically described below.

FIG. 1 is a diagram showing one memory cell in one embodiment. Similarly to FIG. 5, 1 is a drain diffusion region, 2 is a source diffusion region, 3 is a word line that also serves as a gate electrode,
4 is a bit line, and 5 is a ground line. The word line 3 is formed of a polysilicon layer, and the bit line 4 and ground line 5 are formed of a metal layer, for example an aluminum layer.

A bypass word line 3a extending vertically parallel to the word line 3 is formed of a polysilicon layer.

Word line 3 and word line 3a are polysilicon layer 1
They are connected by 0 and arranged in parallel.

FIG. 2 shows an equivalent circuit of this embodiment.

It is assumed that the word line 3a is formed to have the same width as the word line 3. Two word lines 3.3a are the sixth
Taking as an example the case where three memory cells 6-1 to 6-3 are commonly connected as shown in the figure, the resistance value of word lines 3 and 3a per memory cell is Rp/2, so ,
The resistance value of the word line 3.3a as a whole is 1/2 of the resistance value of the word line 3 in FIG.

FIG. 3 shows an embodiment in which the present invention is applied to a memory device having a two-layer metal structure.

In this case as well, 1 is the drain diffusion region, 2 is the same as in FIG.
is a source diffusion region, 4 is a bit line, and 5 is a ground line. The bit line 4 and the ground line 5 are formed of a first metal layer, for example, an aluminum layer.

Reference numeral 3' denotes a gate electrode made of a polysilicon layer, and the gate electrode 3' is formed independently for each memory cell. A word line 12 is formed of a second metal layer, for example an aluminum layer, and is connected to the gate electrode 3' via a through hole in an interlayer insulating film. The word line 12 extends vertically in the figure and is commonly connected to the gate electrodes 3' of a plurality of memory cells arranged vertically.

FIG. 4 shows an equivalent circuit of FIG. 3.

If the resistance value per memory cell of the word line 12 due to the metal layer is Rm, three memory cells 6-1 to 6-6
-3, the resistance value of word line 12 is 3Rm. The resistance value Rm of the metal layer is the resistance value Rm of the polysilicon layer.
It is possible to make it significantly smaller than p, and usually R
m << Rp. Although Rm varies somewhat depending on the manufacturing process, it can be set to 1/200 to 1/300 of Rp.

(Effects) In the semiconductor memory device of the present invention, since the word line is formed of a metal line or a polysilicon line connected in parallel, the resistance value of the word line can be reduced. This reduces the load on the driver circuit that drives the word line, and as a result, the input/output delay time of the memory device can be shortened.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing one memory cell in one embodiment, FIG. 2 is an equivalent circuit diagram of the same embodiment, and FIG. 3 is a plan view showing one memory cell in another embodiment. 4 is an equivalent circuit diagram of the same embodiment, FIG. 5 is a plan view showing one memory cell in a conventional memory device, and FIG. 6 is an equivalent circuit diagram of the conventional example. 1.2... Diffusion region, 3.3a, 12... Word line, 4...
...Bit line, 6-1 to 6-3...Memory cell.

Claims (1)

[Claims] In a semiconductor memory device in which a plurality of memory cells with polysilicon gates are arranged in a lattice pattern, and word lines and bit lines are arranged to cross each other in order to select an arbitrary memory cell, the word line is a metal line. Or a semiconductor memory device characterized by comprising polysilicon lines connected in parallel.