JPH01138739A - Integrated circuit package - Google Patents

Integrated circuit package

Info

Publication number
JPH01138739A
JPH01138739A JP62298274A JP29827487A JPH01138739A JP H01138739 A JPH01138739 A JP H01138739A JP 62298274 A JP62298274 A JP 62298274A JP 29827487 A JP29827487 A JP 29827487A JP H01138739 A JPH01138739 A JP H01138739A
Authority
JP
Japan
Prior art keywords
chip
integrated circuit
electromagnetic
lead
outside
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62298274A
Other languages
Japanese (ja)
Inventor
Kiyoshi Hiraizumi
平泉　清
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62298274A priority Critical patent/JPH01138739A/en
Publication of JPH01138739A publication Critical patent/JPH01138739A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Details Of Measuring And Other Instruments (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To form an electromagnetic shield between a chip in the interior of an IC and the outside and to reduce the erroneous operation of the IC and so on, which are caused by an electromagnetic field in the outside of the IC, by a method wherein an electromagnetic shielding part is added to an IC package consisting of a nonmetal. CONSTITUTION:A shielding plate 5 is arranged in such a way that a short-circuit is not caused between a lead 3 of an IC chip 2 and the plate 5 and in such a way as to cover the whole IC chip 2 and a lead 6 is earthed. Thereby, an electromagnetic-field shield between the chip 2 and the outside is formed.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、集積回路（ＩＣ）パッケージに関し、特にセ
ラミックおよびプラスチックなどの非金属パッケージに
関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention This invention relates to integrated circuit (IC) packages, and in particular to non-metallic packages such as ceramic and plastic.

（：従来の技術〕 従来、この種のバ・９ケージ材料としてセラミックある
いはプラスチックが使われたＩＣパッケージでは、電磁
界に対するシールドがされていない構造であった。(: Prior Art) Conventionally, this type of IC package in which ceramic or plastic was used as the cage material had a structure that was not shielded against electromagnetic fields.

その−例として従来のプラスチックパッケージの構造を
第２図に示す。図において、１はプラスチックパッケー
ジ、２はＩＣチップ、３はリードおよび４はボンディン
グワイヤである。As an example, the structure of a conventional plastic package is shown in FIG. In the figure, 1 is a plastic package, 2 is an IC chip, 3 is a lead, and 4 is a bonding wire.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来のＩＣパッケージは、電磁界に対するシー
ルド効果がないため、外部からの電磁界によってＩＣが
誤動作したり、ＩＣの動作信号電流によって電磁界を外
部へふく射するという欠点がある。The above-mentioned conventional IC package does not have a shielding effect against electromagnetic fields, and therefore has the disadvantage that the IC may malfunction due to an external electromagnetic field, or the electromagnetic field may be radiated to the outside due to the IC's operating signal current.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は、非金属材料で集積回路チ・・ノブを密封する
集積回路パ・ソケージにおいて、前記集積回路チップを
囲み接地用のリードに接続された電磁シールド部を含ん
で構成される。The present invention is an integrated circuit package that seals an integrated circuit chip with a non-metallic material, and includes an electromagnetic shielding part surrounding the integrated circuit chip and connected to a grounding lead.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第１図は本発明の一実施例の断面図である。１はＤＩＰ
形プラプラスチックパッケージ１２Ｃチップ、３はリー
ドでこれはＩＣを動作するなめに必要な信号、電源、グ
ランド端子を総称している。FIG. 1 is a sectional view of an embodiment of the present invention. 1 is DIP
12C chip in plastic plastic package, 3 is lead, which collectively refers to the signal, power, and ground terminals necessary to operate the IC.

４はＩＣチップとリード３を接続するボンディングワイ
ヤ、５はシールド板、６はシールド板と接続されたリー
ド、７はシールド板とリード６を接続するはんだ１寸部
である。4 is a bonding wire that connects the IC chip and the lead 3; 5 is a shield plate; 6 is a lead connected to the shield plate; and 7 is a one-dimensional solder portion that connects the shield plate and the lead 6.

以上の構成において、ＩＣチップ２のリード３と短絡し
ないようにしてＩＣチップ２の全体を覆うようにシール
ド板５を配置し、リード６をアースすることによりＩＣ
チップ２と外部との電磁界シールドを形成させるもので
ある。In the above configuration, the shield plate 5 is arranged to cover the entire IC chip 2 so as not to short-circuit with the lead 3 of the IC chip 2, and the lead 6 is grounded.
This forms an electromagnetic shield between the chip 2 and the outside.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、セラミックやプラスチッ
クなどの非金属のＩＣパッケージに電磁シールド部を付
加することにより、ＩＣ内部のチップと外界との間に電
磁シールドを形成することができ、これによりＩＣ外部
の電磁界によるＩＣの誤動作、およびＩＣの動作信号電
流による外部への電磁界ふく射を低減する効果がある。As explained above, the present invention can form an electromagnetic shield between the chip inside the IC and the outside world by adding an electromagnetic shield to a non-metallic IC package such as ceramic or plastic. This has the effect of reducing malfunction of the IC due to electromagnetic fields outside the IC and electromagnetic field radiation to the outside due to the IC's operating signal current.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例の断面図、第２図は１足来の
ＩＣパッケージの断面図である。 １・・・プラスチックパッケージ、２・・・ＩＣチップ
、３．６・・・リード、４・・・ボンディングワイヤ、
５・・・シールド板。FIG. 1 is a cross-sectional view of one embodiment of the present invention, and FIG. 2 is a cross-sectional view of a first-generation IC package. 1...Plastic package, 2...IC chip, 3.6...Lead, 4...Bonding wire,
5... Shield plate.

Claims (1)

【特許請求の範囲】[Claims] 非金属材料で集積回路チップを密封する集積回路パッケ
ージにおいて、前記集積回路チップを囲み接地用のリー
ドに接続された電磁シールド部を含むことを特徴とする
集積回路パッケージ。1. An integrated circuit package in which an integrated circuit chip is hermetically sealed with a non-metallic material, the integrated circuit package comprising an electromagnetic shielding part surrounding the integrated circuit chip and connected to a grounding lead.
JP62298274A 1987-11-25 1987-11-25 Integrated circuit package Pending JPH01138739A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62298274A JPH01138739A (en) 1987-11-25 1987-11-25 Integrated circuit package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62298274A JPH01138739A (en) 1987-11-25 1987-11-25 Integrated circuit package

Publications (1)

Publication Number Publication Date
JPH01138739A true JPH01138739A (en) 1989-05-31

Family

ID=17857513

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62298274A Pending JPH01138739A (en) 1987-11-25 1987-11-25 Integrated circuit package

Country Status (1)

Country Link
JP (1) JPH01138739A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0332045A (en) * 1989-06-29 1991-02-12 Mitsubishi Electric Corp Integrated circuit package
JPH0518759A (en) * 1991-07-08 1993-01-26 Murata Mfg Co Ltd Vibrating gyro
US5650659A (en) * 1995-08-04 1997-07-22 National Semiconductor Corporation Semiconductor component package assembly including an integral RF/EMI shield
JP2006319014A (en) * 2005-05-11 2006-11-24 Sharp Corp Electronic component for receiving high-frequency signal reception
WO2006126441A1 (en) * 2005-05-26 2006-11-30 Murata Manufacturing Co., Ltd. Package for electronic component, electronic component using such package, and method for producing package for electronic component
JP2007199049A (en) * 2005-12-27 2007-08-09 Yamaha Corp Semiconductor device

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0332045A (en) * 1989-06-29 1991-02-12 Mitsubishi Electric Corp Integrated circuit package
JPH0518759A (en) * 1991-07-08 1993-01-26 Murata Mfg Co Ltd Vibrating gyro
US5650659A (en) * 1995-08-04 1997-07-22 National Semiconductor Corporation Semiconductor component package assembly including an integral RF/EMI shield
JP2006319014A (en) * 2005-05-11 2006-11-24 Sharp Corp Electronic component for receiving high-frequency signal reception
WO2006126441A1 (en) * 2005-05-26 2006-11-30 Murata Manufacturing Co., Ltd. Package for electronic component, electronic component using such package, and method for producing package for electronic component
US7713783B2 (en) 2005-05-26 2010-05-11 Murata Manufacturing Co., Ltd. Electronic component package, electronic component using the package, and method for manufacturing electronic component package
JP2007199049A (en) * 2005-12-27 2007-08-09 Yamaha Corp Semiconductor device

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