JPH01138144U

JPH01138144U -

Info

Publication number: JPH01138144U
Application number: JP3430388U
Authority: JP
Priority date: 1988-03-15
Filing date: 1988-03-15
Publication date: 1989-09-21

Description

[Brief explanation of the drawing]

第１図から第３図までが本考案に関し、第１図
は本考案による計算機内バス接続デバイスへのア
クセス状況監視回路の実施例回路図、第２図はそ
の正常時の動作を示す波形図および動作状態図、
第３図はデバイスから確認応答が得られない場合
の動作を示す波形図および動作状態図である。第
４図はアクセス状況監視回路を備えない従来の計
算機の構成回路図である。図において、１０：中央処理ユニツトないしはＭＰＵ、１１
：異常処理プログラム、２０：バス、２１：アド
レスバス、２１ａ：バスドライバ、２２：データ
バス、２２ａ：バスドライバ、２３〜２５：制御
線、２３ａ〜２５ａ：バツフア、３０：デバイス
、３１：デバイスの本体、３２：アドレスセレク
タ、４０：時限回路、４１：カウンタ、４２：オ
アゲート、４３：設定器、５０：ノアゲート、Ａ
Ｄ：アドレス、ＡＫ：確認応答、ＡＫ１：仮の確
認応答、ＣＰ：クロツクパルス、ＩＳ：割込信号
、ＩＴ：ＭＰＵの割込入力、ＬＳ：待ち状態監視
、ＲＤ：アクセス指令としての読取指令、ＲＮ：
運転状態、τ：時限、ＷＲ：アクセス指令として
の書込指令、ＷＴ：ＭＰＵの待ち状態、：Ｍ
ＰＵの待ち状態解除入力、である。 Figures 1 to 3 relate to the present invention; Figure 1 is a circuit diagram of an embodiment of the access status monitoring circuit for an in-computer bus connection device according to the present invention, and Figure 2 is a waveform diagram showing its normal operation. and operating state diagram,
FIG. 3 is a waveform diagram and an operation state diagram showing the operation when no acknowledgment is obtained from the device. FIG. 4 is a configuration circuit diagram of a conventional computer without an access status monitoring circuit. In the figure, 10: central processing unit or MPU, 11
: Abnormality processing program, 20: Bus, 21: Address bus, 21a: Bus driver, 22: Data bus, 22a: Bus driver, 23-25: Control line, 23a-25a: Buffer, 30: Device, 31: Device Main body, 32: Address selector, 40: Time limit circuit, 41: Counter, 42: OR gate, 43: Setting device, 50: Noah gate, A
D: Address, AK: Acknowledgment response, AK1: Temporary acknowledgment response, CP: Clock pulse, IS: Interrupt signal, IT: MPU interrupt input, LS: Wait state monitoring, RD: Read command as access command, RN :
Operating status, τ: Time limit, WR: Write command as access command, WT: MPU waiting state, :M
This is an input to release the PU from waiting state.

Claims

[Scope of utility model registration request]

When a central processing unit accesses a device connected to a bus, it specifies the other device via the bus, gives an access command to each device, enters a waiting state for an acknowledgment, and receives an acknowledgment from one of the devices. A circuit for monitoring the status of access to a device in a computer which enters a state of data transfer via a bus when the access command is obtained, and includes a timer circuit that is activated by an access command and reset based on an acknowledgment response; When the time limit set in this time limit circuit has elapsed, a time limit end signal is given to the central processing unit as a temporary acknowledgment and an interrupt signal, and the central processing unit exits from its waiting state with this temporary acknowledgment and sends an interrupt signal. 1. An access status monitoring circuit for an internal bus-connected device in a computer, characterized in that an abnormal processing operation can be taken based on the following.