JPS6142624U

JPS6142624U - Computer system restart circuit

Info

Publication number: JPS6142624U
Application number: JP12830384U
Authority: JP
Inventors: 広海清水; 勝美宇田川
Original assignee: 新電元工業株式会社
Priority date: 1984-08-24
Filing date: 1984-08-24
Publication date: 1986-03-19

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

第１図は従来の計算機システムの概略図、第２図および
第３図は本考案の一実施例回路図および動作説明用の波
形図ミ第４図および第５図は本考案の他の実施例回路図
およびその動作説明用の波形図である。１・・・・・・演算装置、２・・・・・・制御回路、３
・・・・・・中央処理装置（ＣＰＵ）、４・・・・・・
ＲＡＭ，５・・・・・・ＲＯＭ，６・・・・・・記憶
回路、７・・・・・・入力回路、′８・・・・・・出力
回路、９・・・・・・入出力回路（ｉ／ｏ回路）
、１０・・・・・・、出力信号制御タイマ回路、１１・
・・・・・信号バス、１２・・・・・・クロツクパルス
発振器、１３・・・・・・Ｎ進カウンタ、１４・・・・
・・不揮発性スタティクＲＯＭ．ｌ５・・・・・−
ＲＡＭ，１６・・・・・・Ｅ２ＰＲＯＭ，１７
・・・・・・信号制御回路、１８・・・・・・オア回路
。FIG. 1 is a schematic diagram of a conventional computer system, FIGS. 2 and 3 are a circuit diagram of one embodiment of the present invention, and waveform diagrams for explaining the operation. FIGS. 4 and 5 are another embodiment of the present invention. FIG. 2 is an example circuit diagram and a waveform diagram for explaining its operation. 1... Arithmetic device, 2... Control circuit, 3
...Central processing unit (CPU), 4...
RAM, 5...ROM, 6...memory circuit, 7...input circuit, '8...output circuit, 9...input Output circuit (I/O circuit)
, 10..., output signal control timer circuit, 11.
... Signal bus, 12 ... Clock pulse oscillator, 13 ... N-ary counter, 14 ...
・Non-volatile static ROM. l5・・・−
RAM, 1 6...E2PROM, 1 7
......Signal control circuit, 18...OR circuit.

Claims

[Scope of utility model registration request]

(1) In a computer system consisting of a central processing unit, a program storage circuit, an input/output circuit, a timer circuit, etc., a clock pulse oscillator and the output pulses of this oscillator are counted and sent out from peripheral circuits such as the input/output circuit. The 6 count value is cleared by the normal instruction signal detected from the program state, and the clearing of the count value is stopped due to the loss of the normal instruction signal when an abnormality occurs, and the central processing unit reset signal is sent. A restart circuit for a computer system, characterized in that a counter circuit is provided to automatically restart a central processing unit. {2} Predetermined data is stored in the memory circuit when the central processing unit is normal.
In addition to providing a nonvolatile static RAM that is held in the 2FROM, the counter circuit is also provided with a function to send a transfer signal before sending out a reset signal for restarting the central processing unit, and this transfer signal makes the content held in the upper 12FROM nonvolatile. 2. The restart circuit for a computer system according to claim 1, wherein the restart circuit for a computer system is configured to restart the central processing unit after the data is transferred to the RAM of the static static RAM.