JPH01136415A - Programmable logic circuit - Google Patents

Abstract

PURPOSE:To reduce the defective factor to nearly 1/2 or below in comparison with that of an LSI without any test circuit by providing a means checking independently information programmed in an electrically programmable element and checking whether or not a bit memory circuit is operated normally. CONSTITUTION:A test output terminal 94 is provided via a transfer gate 13 comprising a MOS transistor(TR) to a connecting point whose voltage is changed by the information of an E<2>P element 31 programmably electrically in the bit memory circuit 51 and the element 31 is connected to an input of an inverter 40 comprising a complementary MOS circuit driving a switch element 10 via the control element 12. The transfer gate 13 is used to connect only the selected bit memory circuit to the test output line. The control element 12 is used to isolate the element 31 from the bit memory circuit electrically at test. Moreover, the output of the inverter 40 is fed back to the input through a logic inverting circuit to use the test data input terminal and the test output terminal in common at the bit memory circuit test.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a programmable logic circuit, and particularly has a test function. The present invention relates to electrically programmable switch circuits.

[Conventional technology]

Conventionally, it is used in programmable logic devices. For electrically programmable switch circuits, see
E.E., Journal of Solid State Circuits, Nis.C.21. Number 5 (19
October 1986) pages 766 to 744 (IEEE
Journal of 5 solid-State C1
rcuits, 5C-21, &5 (1986°10)
PP766-774). In this conventional example, a bit memory circuit for controlling a MOS switch is connected in parallel with a flip-flop circuit in which the inputs and outputs of two CMOS inverter circuits are connected together, and an nMOS transistor of one of the two inverters. Connected. Electrically programmable Mo
It is composed of S transistors. This conventional bit memory circuit is configured with a 0M08 circuit, and therefore has the characteristic that it does not consume power in principle in a steady state.

[Problem that the invention seeks to solve]

The above-mentioned conventional technology does not take into consideration the means for testing the information programmed in electrically programmable MOS transistors or for testing whether the bit memory circuit is operating normally. In integrated circuits, the number of elements integrated within one semiconductor substrate is becoming approximately 10B. Therefore, in order to provide a semiconductor integrated circuit including programmable elements with high reliability, a means for testing each circuit and programmable element included therein is required.

It is an object of the present invention to provide a bit memory circuit with means for independently testing whether the information programmed in the electrically programmable element and the bit memory circuit operate normally.

[Means to solve problems]

The above purpose is to achieve l! within the bit memory circuit. M at the connection point where the voltage changes depending on the information of the electrically programmable element.
OS) - providing a test output terminal via a transfer gate with a transistor and connecting an electrically programmable element via a control element to the input of an inverter with a complementary MOS circuit driving the switching element. , and by feeding back the output of the inverter to the input of the inverter through a logic inversion circuit.

[Function] A transnor gate using a MOS transistor installed between a connection point and a test output terminal whose voltage changes according to information from an electrically programmable element in a bit memory circuit can be used to test other bit memory circuits. It is used to connect only selected bit memory circuits to a test output line whose output terminals are commonly connected. This allows the information of a large number of bit memory circuits or the programmable elements contained therein to be tested in time v1 with a smaller number of test output lines.

In addition, a control element provided between the electrically programmable element and the input of the inverter by the complementary MO5 circuit that drives the switch element is configured to remove the electrically programmable element from the bit memory circuit during testing. It can be used to separate This allows the electrically programmable elements and the bit memory circuit to be tested independently.

Furthermore, by feeding back the output of the inverter to the input of the inverter through a logic inversion circuit, a test data input terminal and a test output terminal can be used in common when testing a bit memory circuit.

〔Example〕

The present invention will be explained in detail below. FIG. 1 shows a first embodiment of a bit memory circuit used in a programmable logic circuit according to the present invention. This bit memory circuit 51 has a switch control output terminal 9 that controls an n-type switch MOSIO.
7, to which the output of an inverter 40 formed by a complementary MOS circuit constituted by a 9MOS transistor 21 and an nMOS transistor 11 is connected. In addition, an electrically erasable E2P element 3 is connected to the input of the inverter 40 via a control element 12 made of a high voltage nMOS transistor.
1 is connected to the drain of the inverter 40, its source is connected to the Vs terminal 91, its gate is connected to the Va terminal 92, and the gate of the control cable 12 is connected to the vc terminal.6Furthermore, the input of the inverter 40 is an nMOS transistor 13 to a data input/output terminal 94, and the gate of the nMOS transistor 13 is connected to a Vn↑ terminal 95. Furthermore, the output of the inverter 40 is logically inverted by the PMOS transistor 22 and fed back to the input of the previous inverter. In addition, there is a power terminal 96 and a ground terminal 98.

Next, the operation of the bit memory circuit according to this embodiment will be explained. In the initial state, the electrically erasable E"P element 31 has a threshold value VTR of 0 to 1V. The program sets the source of the E"P element 31 to Ov and the gate to 10 to 1V.
This is done by setting the voltage to 20V and the drain voltage to 5V, and at this time the voltage of the VTR becomes 5V or more. Also, for erasing, the drain is open, the gate is set to OV, and the source is set to 10 to 20 V.
This is done by applying .

In the bit memory circuit 51, in the read state, a power supply voltage is applied, and at the same time, voltages shown in FIG. 3 are applied to each terminal. When the VTH of the E"P element 31 is low, the Va terminal is 5V, so it is in a conductive state, and the control element 12 is also Vc
Since the terminal is 2V, it becomes conductive and the inverter 40
The input of is at a low potential. Then, the output of the inverter 40, that is, the switch control output terminal 97 becomes a high potential, and n
The type switch MOSIO becomes conductive, and the wiring 81 and the wiring 82 are connected. At this time, since the 9MOS transistor 22 is in a non-conducting state, no steady current flows through the E"P element 31. On the other hand, the VTH of the E"P element 31
When is high, the inverter 40 becomes non-conductive and the input of the inverter 40 has a high potential. Then, the output of the inverter 40, that is, the switch control output terminal 97 becomes a low potential, the n-type switch MOSIO becomes non-conductive, and the wiring 81 and the wiring 8
2 is disconnected. At this time, the pMOSh transistor 22 becomes conductive and functions to keep the input of the inverter 40 at a high potential. Further, during the read state, VDT is Ov and the n MOS transistor 13 is non-conductive. In this way, in the read state, the bit memory circuit 41 controls the connection and disconnection of the wiring 81 and the wiring 82 according to the program state of the E''P element 31. At this time,
In a steady state, no current flows in principle.

In the erase state, voltages shown in FIG. 3 are applied to each terminal. At this time, the VC terminal 93 is Ov, and the high voltage nMOS
Transistor control wire 12 is non-conducting and serves to isolate E2P element 3'1 from the bit memory circuit and to prevent high voltages from being applied to the bit memory circuit. Also, since OV is applied to the Va terminal 92 and Vp=10 to 20V is applied to the Vs terminal 91, E”P
The information of the element 31 is erased, and VTII becomes O~1■.

When rewriting program data, it is executed by first erasing the data using the method described above and then programming. In the program state, voltages shown in FIG. 3 are applied to each terminal. Since the voltage at the Vc terminal 93 is 5V and the voltage at the Va terminal 92 is vP=10 to 20V, the control element 12 and the E"P element 31 are in a conductive state. At this time, the nMOS transistor 13 which is in a conductive state is When 5V is applied to the data input/output terminal 94 through the E2P connector 31, a current flows to the E2P cable 31 and enters the write state, and the VTR becomes 5V.
That's all. On the other hand, when the data input/output terminal 95 is set to 0■, no current flows through the E"P element 31 and writing does not occur, so its vTH remains at O~1v. In this way, the data input/output terminal Depending on the voltage of 94, E”
P element 31 can be programmed.

In the test state, voltages shown in FIG. 3 are applied to each terminal. First, when testing the information programmed in the E"P element 31, first set it to the above-mentioned read state, and then apply 5V to the VoT terminal 95.
This is done by turning on the MOS transistor 13 and taking out the input voltage of the inverter 40 from the data input/output terminal 94.

FIG. 4 is a timing chart during this E''P test.

On the other hand, when testing the bit memory circuit 51,
The E"P element 31 is separated from the bit memory circuit 51 by setting the Vc terminal 93 to Ov. Therefore, 5V is applied to the VDT terminal 95 and 5V or Ov is applied from the data input/output terminal 94.
Enter the data.

Then, the inverter 40 and the pMOS transistor 22
The data is held by the latch circuit. Thereafter, after setting the VDT terminal 95 to Ov for -1 time, the VDT terminal 95 is set to 5V again, and the held data is detected from the data input/output terminal 94.

The detection method may be to detect whether a current can flow from the data input/output terminal 94 depending on whether the pMOS transistor 22 is conductive or non-conductive.

According to this embodiment, the electrically programmable element is
Since it is composed of P elements 31, it is possible to change the program while the circuit is installed.
The package of I does not require a quartz glass window and can be an inexpensive plastic package.Furthermore, the bit memory circuit of this embodiment has a small number of elements, 6 elements. Furthermore, it has the characteristic that no power is consumed in principle in the steady state of the read state.

Next, a second embodiment of the present invention will be described. FIG. 2 shows a second embodiment of a bit memory circuit used in a programmable logic circuit according to the present invention. In this bit memory circuit 52, inverters 41 and 42 are the same circuits as inverter 40 which is a complementary MOS circuit shown in FIG. The gate length to gate width ratio W/L of the PMOS of the inverter 41 is smaller than the W/L of the PMOS of the inverter 42, and the W/L of the nMOS of the inverter 41 is W/L of the nMO5 of the inverter 42. L
It's bigger.

Therefore, in the read state, if the EzP element 32 is programmed to be non-conductive, 1f! When the power is turned on, the switch control output terminal 97 automatically becomes a low potential.

Also, compared to the first @ bit memory circuit 51, the pMOS
The inverter 42 performs the logic inversion that was performed by the transistor 22, and forms a complete latch circuit together with the inverter 41. Furthermore, the data input/output terminal 94 is connected to the switch control output terminal 97
The point connected via the transistor 14 is the first
This is different from the bit memory circuit 51 shown in the figure. The other parts are similar to the bit memory circuit 51 in FIG. Therefore, the operation is performed at the data input/output terminal 9 in the program state.
4 and the state programmed into the E2P circuit 32 is opposite to that of the bit memory circuit 51 shown in FIG.
The operation is the same as that of the bit memory circuit 51 in FIG. 1, except that the relationship between the state programmed in the element 32 and the data appearing at the data input/output terminal 94 is reversed.

Detailed description will be omitted.

According to this embodiment, since a complete latch circuit is configured by the inverters 41 and 42, by latching the write data in the plurality of bit memory circuits 52 in advance in the program state, one program cycle can be completed. It becomes possible to write to the E''P element 32 at the same time.

Next, an embodiment of a programmable logic circuit using a bit memory circuit according to the present invention will be described with reference to FIG.

This programmable logic circuit.

It consists of one wire 101, 102 running in the horizontal direction and m wires 8103, 104 running in the vertical direction, and there is an n-type switch MOSIO at the intersection of each wire.Each n-type switch MOS is a bit memory. The bit memory circuits 53 to 56 are either the bit memory circuits 51 or 52 of FIG. 1 or 2. The bit memory circuits 53 arranged horizontally
゜54 (1) VDT terminal 95, Vc terminal 93, Va
The terminals 92 are commonly connected to each other, and the VDT output 125, Vc output 123, and Va 122 of the control circuit 64 are connected through transfer MOS transistors 71 to 73 whose respective gates are commonly connected and connected to the output of the decoder 62.
connected to the output.

Furthermore, data input/output terminals 94 of the bit memory circuits 53 to 55 arranged in the vertical direction are commonly connected to a data input/output line 105 and connected to a data latch 63. Further, the vs terminals 91 of each bit memory circuit are all connected in common to the Vs output 121 of the control circuit 64. A control signal 113 and a high voltage 114 of 10 to 20V are connected to the control circuit 64. An address signal lll is applied to the decoder circuit 62 via the address latch 61. The data latch 63 has a control signal 113 and VDT.
An output 125 is provided, and data input or test output is performed depending on its state.

Next, the operation of this embodiment will be explained. The control circuit 64 outputs VDT output 125, Vc output 123,
The voltage shown in FIG. 3 is generated at the VG output]-22 and the Vs output 121. In the continuous state, each bit memory circuit 53-56 is separated from the data input/output line 105-106, and the E''P element 3 of each bit memory circuit 53-56 is separated from the data input/output line 105-106.
Each n-type switch MOS 10 is controlled according to the program state of 1 or 32, and the intersection of each wiring is set to a connected or non-connected state. In program form 1,
Program data is applied from the data latch to the data input/output terminal of the bit memory circuit of the row selected by the address signal 111, and programming is performed for each row. In the erase state, the E2P elements 31 or 32 of all bit memories are erased simultaneously according to instructions from the control circuit 64. In the test state, data input/output line 1 is input/output from the bit memory circuit in the row selected by the address signal 111.
Test data is output to the data latch 63 via 05-106. At this time, by controlling the Vc terminal 93 of each bit memory circuit, E"P
The program status of 2 and the bit memory circuits 53-54 can be tested independently.

In the embodiment described here, an E"P element was used as the electrically programmable element, but an EP element that is erased by ultraviolet irradiation or a fuse element that can be programmed only once may be used instead. However, it is clearly within the scope of the present invention.

In addition, in this embodiment, a switch matrix circuit with grid wiring is shown as a programmable logic circuit, but the present invention can also be applied to a circuit in which each bit memory circuit controls the connection between two mutually independent wirings. It is clear that it is within the range of .

〔Effect of the invention〕

According to the present invention, the bit memory circuit is bridged by a complementary MOS circuit, and the bit memory circuit is used without passing current through the electrically programmable elements in the read state, which is used for the longest time. The value of the current flowing in the circuit, which is only about the leakage current, is 1 when the bit memory circuit is
Even in a programmable logic LSI using number 0, it is 50
It is about μW.

Further, in the bit memory circuit according to the present invention, the electrically programmable elements and the bit memory circuit can be tested independently. Therefore, by using this circuit, a programmable logic LSI can be tested more completely, and the defect rate can be reduced to about 172 or less compared to an LSI that does not have such a test circuit.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a bit memory circuit according to a first embodiment of the present invention, FIG. 2 is a circuit diagram of a bit memory circuit according to a second embodiment, and FIG. 3 is a circuit diagram of a bit memory circuit according to a first embodiment. FIG. 4 is a timing chart for testing the bit memory circuit of the first embodiment, and FIG. 5 is a configuration diagram of an embodiment of the program logic circuit according to the present invention. 10- n-type switch MOS, 11, 13, 14...
nMOS transistor, 12.15... control element, 2
1.22...PMOS transistor, 31.32...
・E2P element, 40-42... Inverter, 51-
56...Bit memory circuit, 61...Address latch. 62...Address decoder, 63...Data latch. 64...Control circuit, 71-76...Transfer M
OS transistor, 81.82... wiring, 91...
Vs terminal, 92...Va terminal, 93...Vc terminal,
94...Data input/output terminal, 95...VDT terminal,
96... Power supply terminal, 97... Switch control output terminal, 98... Ground terminal, 99... VD terminal, 101,
102...Horizontal wiring, 103.104...Vertical wiring, 105,106...Data input/output lines, 11
1...Address signal, 112...Data input/output, 1
13... Control signal, 114... High voltage, 121...
・Va high output 122...Va high output 123-Vc high output 125-VDT output. ′-]) Agent Patent attorney Katsuma Ogawa =, ′ 躬 l Concave C/Zadai 2 Zuman 3 z Otozu Tokiyami

Claims (1)

[Scope of Claims] 1. A semiconductor integrated circuit including at least one switch element that connects or disconnects two conductor lines, and a bit memory circuit that controls the switch element, wherein the bit memory circuit includes at least one switch element that connects or disconnects two conductor lines. A programmable logic circuit comprising one or more electrically programmable elements. 2. The programmable logic circuit according to item 1, wherein the switch element is constituted by a MOS type semiconductor element. 3. The bit memory circuit is provided with at least one control terminal for programming the electrically programmable element, and a data input terminal for providing a state to be programmed. 2. The programmable logic circuit according to claim 1. 4. Clause 1, wherein the bit memory circuit comprises a test circuit for detecting a programmed state of the electrically programmable element and a test output terminal for outputting the detected signal. The programmable logic circuit described. 5. The programmable logic circuit according to item 1, wherein in the bit memory circuit, the data input terminal and the test output terminal are common. 6. In the bit memory circuit, the switch element is driven by an inverter circuit of a complementary MOS circuit, and the output of the inverter circuit is returned to the input of the inverter circuit through a logic inversion circuit. 2. The programmable logic circuit according to claim 1. 7. In the bit memory circuit, the electrically programmable element is connected to the input of the inverter circuit via a control element.
Programmable logic circuit as described in section. 8. The programmable logic circuit according to item 1, wherein the electrically programmable element is constituted by a floating gate type MOS semiconductor element, and the control element is constituted by a MOS type semiconductor element.