JPH01136257A - Storage device of set associative system - Google Patents

Abstract

PURPOSE:To realize storage of set associative system without generating malfunction even when one bit error is generated in a storage cell by fixing the content of a memory device group re-representing the state of a block which becomes a candidate of data substitution. CONSTITUTION:In case of selecting an address tag memory 5 generating the one bit error in a set selector 3 to which an address 1 is supplied from the outside, the content of the address tag memory 5 generating the one bit error is sent to a comparator 9. And the content of a valid bit memory 6 (the content of the valid memory 6 includes invalidity since no write is performed on an entry in which the one bit error is generated) is also sent, therefore, no coincidence is obtained in the content of the address tag memory 5 in which the one bit error is generated, thereby, no malfunction is generated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a set-associative storage device, and particularly to a set-associative cache memory that can repair bit defects during manufacturing.

[Conventional technology]

Figure 1 n, cQ publisher interface.

FIG. 2 is a block configuration diagram of a number set associative type cache memory described on page 250 of the August 1987 issue. In the figure, lit is the address to access the cache memory, (21 is an address tag that is part of the address Il+,] 3I is a set selector that is part of the address +11, and 411j is the address in the cache memory. +71 is a data block that holds the data in the cache memory; IB) is the data block; The valid pit mesori shown in (8) is an address tag comparator (41 is the word selector that is - of the address 111, and tlol is the word selector (41
to 1″ select, αυ is the way select selected by the address tag comparator, (
! is the data output from the way select u1J.

Next, the operation will be explained.

Set selector 1 to which address 11: is given from the outside
The contents of the address comparator (6) of each way selected in 31 are sent to the address tag comparator (91), and the contents of the data block (]) are also sent to the word select (lα). The word data is sent to the way select α1.Then, the address tag comparator (9) checks whether it matches the address tag (2:) together with the contents of the valid bit memory of the selected address tag memory 111). If a way exists, the data of that way is output from the way select Uυ to the data output (1). However, the address comparator (
If there is a mismatch in 91, the data is read to the main memory outside the cache memory, and the data is sent to the MPH and stored in the data block 1]1 in the cache memory. At this time, the LRσ algorithm is used to decide which way to store the data, and the information is
It is stored in the RU bit memory (8).

Next, an example of the LRσ bit 18) will be explained.

FIG. 3 is a diagram showing the relationship between the number way (7) and the LRσ bit (to) in the 4-set associative system.

In the figure (to) each way is 1kA, B.

This bit represents information on LRσ of each way (to) of the way (to) in the cache memory set to 0 and D.

Next, the operation of the LRσ bit memory (8) will be explained.

If way A has been accessed more recently than way B in relation to the three ways a19A and B, data full of (AB) at the LRσ bit end.

If way B has been accessed recently, data O is stored. Similarly, the relationship between way A and way C is that the LRσ bit- [information is stored in AC3 and way A
Information is stored in [AD] of the relationship dLRσ bit (to) and way D. Now, the LRσ bit (to) (”
AB) If the state is 0, [”Ac1-0.CAD]-0, it is the least recently used 9 ray #
: r no ei A, and becomes the top priority i replacement candidate. Conversely, LR4 bits (to) rAB)-t, (ha'3-
1. [If the state is ADl=x, the most recently used way becomes way A, and becomes the candidate with the lowest priority. Other ways can also express the priority of replacement candidates in the state of the LRσ bit ■.

[Problem that the invention seeks to solve]

In such a conventional set associative type memory device, there is a problem in that when the number of memory elements is increased, the yield rate decreases due to bit defects in the memory elements. This invention is
This invention was developed to solve this problem, and the object is to obtain a set associative type storage device that does not operate even if there is a 1-bit defect in the storage element.

[Means for solving problems]

In the set-associative storage device of the present invention, the contents of a storage device of a candidate state storage device group indicating the state of a block that is a candidate for data replacement? It is provided with the candidate state storage device group R7 which can be fixed to prevent it from being rewritten to content 1.

[Effect]

In this invention, the 2/3 way with a bit defect does not become a top priority replacement candidate during operation, does not store data, and therefore does not malfunction.

〔Example〕

An embodiment of this invention will be described below.

I will explain the 4-set associative cache memory, but I will explain the block configuration diagram and 4 ways (towards).
The diagrams showing the relationship between and LRσ bit (to) are as shown in FIG. 1 and FIG. 3 described in the prior art section.If there is no bit defect in the memory element, the operation remains the same as in the conventional case.<151. In Fig. 3, if there is a 1-bit defect in the memory element of one entry of way A among ways (to), way A has a LRσ bit (to) to make it the replacement candidate with the lowest priority. ["AB)-1, rAc]-+l, CAD]-1. This fixes the value as ["AB]-1, rAc]-+l, CAD]-1. As a result, other ways (7), for example, are fixed as LRσpi)(AB]flll, so [B] -1, rB(1-1, [BD)-1, but I
, Rσ bits (to) [muB)-1, r AO)-1,
[”AD]-1. Therefore, way A always remains the replacement candidate with the lowest priority and never goes to the data 1kIF. In Fig. 1, the address +
When the set selector given 11 (address tag memory 16 that caused an L pit defect at 3:) is selected,
Address tag memory that caused the above 1-bit failure +51
The contents of the address tag comparator (91) are sent to the address tag comparator (91), but the contents of the valid-pid memory (6) are also sent to the address tag comparator (91). Pidmemory (61
Since the contents of address tag memory +51 that caused the 1-bit failure must match, a malfunction will not occur.

Next, FIG. 2 shows an example of a memory element whose state can be fixed according to the present invention.

In the figure, (211 is a bit line, - is an inverted signal bit line of the bit line circle, nh word-y line,
The trowel is an N-channel metal oxide field effect transistor (hereinafter referred to as NCh MO8FR1?), the hammer is pchMO8F]lC
T% example is a resistor made of high resistance polysilicon, etc.
Reference numeral 71 indicates a breakable wiring made of aluminum or the like.

Next, the operation will be explained.

Normally, it operates in the same way as a static RAM, but when data is to be fixed, the data is fixed by cutting the disconnectable wiring (271) and turning on Pah MO8IFKT @f.

For example, when fixing to 0, disconnectable wiring (1?, b
), and even if you perform the action of writing summer, it will not become l.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to obtain a set associative type memory device tt- which does not malfunction even if there is a 1-bit defect in the memory element, and the manufacturing yield is the same as above.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of an Lr14 set associative type cache memory.・FIG. 8 is a circuit diagram of a memory element capable of fixing the shape g according to the present invention. FIG. 3 is a diagram showing the relationship between four way LRσ bits in the 4-set associative system. +111fi address, l address tag, 13: set selector, +41ri word selector, +51t!
Address tag memory (61 is valid bit memory,
17) is a data block, f81#fLRU pit memory, (9) is an address tag comparator, 101 is a word F select, αυ is a way select, IIfJIr! Data output, circle is bit line, @ is bit line, tsu is word line, e24I is Nch MO8FFiT, m is Pch MO day FET, example is resistance, punishment is wire that can be disconnected, C111 is way, 08 is I, RU It's a bit. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] A tag storage device group, a data storage device group, a valid status storage device group indicating whether the storage contents in the data storage device group are valid or invalid, and a candidate for data replacement from among the data storage device group. In a set-associative storage device including a group of candidate state storage devices indicating the state of a block that is a candidate for data replacement, the contents of the storage device of the group of candidate state storage devices that indicate the state of a block that is a candidate for data replacement are fixed. A set associative type storage device comprising the candidate state storage device group whose state can be prevented from being rewritten during operation.